Commit Graph

52636 Commits

Author SHA1 Message Date
Max Kazantsev 7790d6cbff [NFC] Use FileCheck in test
llvm-svn: 330684
2018-04-24 04:42:37 +00:00
Craig Topper 19b85103a3 [X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.
This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register.

llvm-svn: 330682
2018-04-24 04:28:02 +00:00
Chandler Carruth 0ace148ca6 [PM/LoopUnswitch] Remove another over-aggressive assert.
This code path can very clearly be called in a context where we have
baselined all the cloned blocks to a particular loop and are trying to
handle nested subloops. There is no harm in this, so just relax the
assert. I've added a test case that will make sure we actually exercise
this code path.

llvm-svn: 330680
2018-04-24 03:27:00 +00:00
George Burgess IV 8e807bf3fa Reland r301880(!): "[InstSimplify] Handle selects of GEPs with 0 offset"
I was reminded today that this patch got reverted in r301885. I can no
longer reproduce the failure that caused the revert locally (...almost
one year later), and the patch applied pretty cleanly, so I guess we'll
see if the bots still get angry about it.

The original breakage was InstSimplify complaining (in "assertion
failed" form) about getting passed some crazy IR when running `ninja
check-sanitizer`. I'm unable to find traces of what, exactly, said crazy
IR was. I suppose we'll find out pretty soon if that's still the case.
:)

Original commit:

  Author: gbiv
  Date: Mon May  1 18:12:08 2017
  New Revision: 301880

  URL: http://llvm.org/viewvc/llvm-project?rev=301880&view=rev
  Log:
  [InstSimplify] Handle selects of GEPs with 0 offset

  In particular (since it wouldn't fit nicely in the summary):
  (select (icmp eq V 0) P (getelementptr P V)) -> (getelementptr P V)

  Differential Revision: https://reviews.llvm.org/D31435

llvm-svn: 330667
2018-04-24 00:25:01 +00:00
Robert Widmann 21fc15d553 [LLVM-C] DIBuilder Bindings For Variable Expressions
Summary: Add DIBuilder bindings for (global) variable expressions, variable value expressions, and debug value intrinsic insertion.

Reviewers: harlanhaskins, deadalnix, whitequark

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45979

llvm-svn: 330661
2018-04-23 22:31:49 +00:00
Roman Tereshin 3c6ea7e28c [GlobalISel][Legalizer] Look thro copies while combining G_UNMERGE's
As we're becoming stricter w/ respect to not allowing vregs having LLTs
and regclasses assigned both mid-globalisel pipeline, the number of
extra copies grows, some of which separate G_UNMERGE's from their
corresponding G_MERGE's, becoming a performance concern.

It's worth mentioning that we're already looking through copies while
combining legalization artifacts for every kind of artifact but
G_UNMERGE.

Reviewed By: aditya_nandakumar

Reviewers: ab, t.p.northover, volkan, javed.absar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45644

llvm-svn: 330660
2018-04-23 22:28:36 +00:00
Roman Lebedev 95c6eaf530 [DAGCombiner] Unfold scalar masked merge if profitable
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].

[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`)
Now, they would no longer be generated  (see `@in`).
So we need to make sure that they are still generated.

If the mask is constant, we do nothing. InstCombine should have unfolded it.
Else, i use `hasAndNot()` TLI hook.

For now, only handle scalars.

https://rise4fun.com/Alive/bO6

----

I *really* don't like the code i wrote in `DAGCombiner::unfoldMaskedMerge()`.
It is super fragile. Is there something like IR Pattern Matchers for this?

Reviewers: spatel, craig.topper, RKSimon, javed.absar

Reviewed By: spatel

Subscribers: andreadb, courbet, kristof.beyls, javed.absar, rengolin, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D45733

llvm-svn: 330646
2018-04-23 20:38:49 +00:00
Roman Lebedev bf18cc56d3 [X86][AArch64][NFC] Add tests for masked merge unfolding
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].

[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andl`+`andn`/`andps`+`andnps` / `bic`/`bsl` would be generated. (see `@out`)
Now, they would no longer be generated  (see `@in`).
I'm guessing `llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp` should be able to unfold this.

Reviewers: spatel, craig.topper, RKSimon, javed.absar

Reviewed By: spatel

Subscribers: nemanjai, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45563

llvm-svn: 330645
2018-04-23 20:38:42 +00:00
Sanjay Patel fa8f5ad9f3 [AggressiveInstCombine] add tests for PR37098; NFC
I'm not sure if this is where we should try to fold these
patterns inspired by:
https://bugs.llvm.org/show_bug.cgi?id=37098
...if this isn't the right place, we can move the tests.

llvm-svn: 330642
2018-04-23 20:20:32 +00:00
Xin Tong 8edff27923 [CallSiteSplit] Make sure we remove nonnull if the parameter turns out to be a constant.
Summary: We do not need nonull attribute if we know an argument is going to be constant.

Reviewers: junbuml, davide, fhahn

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45608

llvm-svn: 330641
2018-04-23 20:09:08 +00:00
Gabor Buella 1a2ce572bf [X86] Revert r330638 - accidental commit
llvm-svn: 330640
2018-04-23 20:05:51 +00:00
Gabor Buella 213a7cda1f [X86] movdiri and movdir64b instructions
Reviewers: craig.topper
llvm-svn: 330638
2018-04-23 20:00:59 +00:00
Bjorn Pettersson 8e484dc531 [MemCpyOpt] Skip optimizing basic blocks not reachable from entry
Summary:
Skip basic blocks not reachable from the entry node
in MemCpyOptPass::iterateOnFunction.

Code that is unreachable may have properties that do not exist
for reachable code (an instruction in a basic block can for
example be dominated by a later instruction in the same basic
block, for example if there is a single block loop).
MemCpyOptPass::processStore is only safe to use for reachable
basic blocks, since it may iterate past the basic block
beginning when used for unreachable blocks. By simply skipping
to optimize unreachable basic blocks we can avoid asserts such
as "Assertion `!NodePtr->isKnownSentinel()' failed."
in MemCpyOptPass::processStore.

The problem was detected by fuzz tests.

Reviewers: eli.friedman, dneilson, efriedma

Reviewed By: efriedma

Subscribers: efriedma, llvm-commits

Differential Revision: https://reviews.llvm.org/D45889

llvm-svn: 330635
2018-04-23 19:55:04 +00:00
Peter Collingbourne 5ab4a4793e Reland r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses.", with a fix for the bot failure.
This reland includes a check to prevent the DAG combiner from folding an
offset that is smaller than the existing one. This can cause oscillations
between two possible DAGs, which was the cause of the hang and later assertion
failure observed on the lnt-ctmark-aarch64-O3-flto bot.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

Original commit message:
> This is a code size win in code that takes offseted addresses
> frequently, such as C++ constructors that typically need to compute
> an offseted address of a vtable. This reduces the size of Chromium
> for Android's .text section by 108KB.

Differential Revision: https://reviews.llvm.org/D45199

llvm-svn: 330630
2018-04-23 19:09:34 +00:00
Daniel Neilson cc45e923c5 [DSE] Teach the pass that atomic memory intrinsics are stores.
Summary:
This change teaches DSE that the atomic memory intrinsics are stores
that can be eliminated, and can allow other stores to be eliminated.
This change specifically does not teach DSE that these intrinsics
can be partially eliminated (i.e. length reduced, and dest/src changed);
that will be handled in another change.

Reviewers: mkazantsev, skatkov, apilipenko, efriedma, rsmith

Reviewed By: efriedma

Subscribers: dmgreen, llvm-commits

Differential Revision: https://reviews.llvm.org/D45535

llvm-svn: 330629
2018-04-23 19:06:49 +00:00
Matthew Simpson 3fd67df3f8 [AArch64] Add cost model test case for transpose
This patch adds a cost model test case for vector shuffles having transpose
masks. The given costs are inaccurate and will be updated in a follow-on patch.

llvm-svn: 330625
2018-04-23 18:21:29 +00:00
Craig Topper ff5ddf75e3 [X86] Add disassembler test cases for bswap.
This demonstrates a bug where the encoding for a 16-bit bswap prints a 16-bit register and a 32-bit mnemonic. Intel docs say 16-bit bswap is undefined. We should either claim it as an invalid encoding or we should print a 16-bit mnemonic.

objdump does print the encoding as bswap with a 16-bit register. But it doesn't seem to ever print a suffix.

llvm-svn: 330621
2018-04-23 17:47:33 +00:00
Vedant Kumar f17720633b [SelectionDAG] Dump debug locs in SDNodes
This helps debug issues where selection-dag assigns the wrong location
to an instruction.

Differential Revision: https://reviews.llvm.org/D45913

llvm-svn: 330618
2018-04-23 17:18:24 +00:00
Matt Arsenault b21f9592be AMDGPU: Move a flawed assert when spilling SGPRs
It's possible to validly spill the frame offset register
in a call sequence to a VGPR. There are definitely issues
with SGPR spilling to memory, so move the assert later.

llvm-svn: 330612
2018-04-23 16:13:30 +00:00
Adrian Prantl bbe980dfe1 Fix computeSymbolSizes SEGFAULT on invalid file
We use llvm-symbolizer in some production systems, and we run it
against all possibly related files, including some that are not
ELF. We noticed that for some of those invalid files, llvm-symbolizer
would crash with SEGFAULT. Here is an example of such a file.

It is due to that in computeSymbolSizes, a loop uses condition

  for (unsigned I = 0, N = Addresses.size() - 1; I < N; ++I) {

where if Addresses.size() is 0, N would overflow and causing the loop
to access invalid memory.

Instead of patching the loop conditions, the commit makes so that the
function returns early if Addresses is empty.

Validated by checking that llvm-symbolizer no longer crashes.

Patch by Teng Qin!

Differential Revision: https://reviews.llvm.org/D44285

llvm-svn: 330610
2018-04-23 16:08:01 +00:00
Robert Widmann 6978db7800 [LLVM-C] DIBuilderBindings for Subrange and Arrays
Summary: Move Go bindings for subranges and DINode arrays.

Reviewers: harlanhaskins, whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45933

llvm-svn: 330594
2018-04-23 14:29:33 +00:00
Nico Weber 514837cc6e Sort a target list a bit better.
llvm-svn: 330593
2018-04-23 14:28:49 +00:00
Alexey Bataev 6b2a5a6dd0 [DEBUGINFO, NVPTX] Add the test for the debug info of the local
variables, NFC.

llvm-svn: 330592
2018-04-23 14:00:53 +00:00
Robert Widmann b02fe644d4 [LLVM-C] Finish Up Scope Bindings
Summary: Adds bindings for Module and NameSpace scopes and LLVMDIBuilderCreateForwardDecl, a counterpart to LLVMDIBuilderCreateReplaceableCompositeType.

Reviewers: harlanhaskins, whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45934

llvm-svn: 330591
2018-04-23 13:51:43 +00:00
Nicolai Haehnle 5a995664f0 AMDGPU: Fix a corner case crash in SIOptimizeExecMasking
Summary:
See the new test case; this is really unlikely to happen with real code,
but I ran into this while attempting to bugpoint-reduce a different issue.

Change-Id: I9ade1dc1aa8fd9c4d9fc83661d7b80e310b5c4a6

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45885

llvm-svn: 330585
2018-04-23 13:05:50 +00:00
Sander de Smalen 7893f722b2 [AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45684

llvm-svn: 330583
2018-04-23 12:43:19 +00:00
Max Kazantsev 91f481665e [LoopRotate] Fix incorrect SCEV invalidation in loop rotation
LoopRotate only invalidates innermost loops while the changes that it makes may
also affert any of this parents. With patch rL329047, SCEV becomes much smarter
about calculation of exit counts for outer loops, so we cannot assume that they are
not affected.

Differential Revision: https://reviews.llvm.org/D45945

llvm-svn: 330582
2018-04-23 12:33:31 +00:00
Max Kazantsev b1137c42fa [LoopSimplify] Fix incorrect SCEV invalidation
In the function `simplifyOneLoop` we optimistically assume that changes in the
inner loop only affect this very loop and have no impact on its parents. In fact,
after rL329047 has been merged, we can now calculate exit counts for outer
loops which may depend on inner loops. Thus, we need to invalidate all parents
when we do something to a loop.

There is an evidence of incorrect behavior of `simplifyOneLoop`: when we insert
`SE->verify()` check in the end of this funciton, it fails on a bunch of existing
test, in particular:

    LLVM :: Transforms/LoopUnroll/peel-loop-not-forced.ll
    LLVM :: Transforms/LoopUnroll/peel-loop-pgo.ll
    LLVM :: Transforms/LoopUnroll/peel-loop.ll
    LLVM :: Transforms/LoopUnroll/peel-loop2.ll

Note that previously we have fixed issues of this variety, see rL328483.
This patch makes this function invalidate the outermost loop properly.

Differential Revision: https://reviews.llvm.org/D45937
Reviewed By: chandlerc

llvm-svn: 330576
2018-04-23 10:32:37 +00:00
Sander de Smalen 1b6d374422 [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+imm) store instructions.
Reviewers: fhahn, rengolin, javed.absar, SjoerdMeijer, t.p.northover, echristo, evandro, huntergr

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45681

llvm-svn: 330565
2018-04-23 07:50:35 +00:00
Chandler Carruth bf7190a154 [PM/LoopUnswitch] Remove a buggy assert in the new loop unswitch.
The condition this was asserting doesn't actually hold. I've added
comments to explain why, removed the assert, and added a fun test case
reduced out of 403.gcc.

llvm-svn: 330564
2018-04-23 06:58:36 +00:00
Craig Topper 3f1d538165 [X86] Add VEX_WIG to VEX encoded version of VCMPPSY/VCMPPDY.
llvm-svn: 330563
2018-04-23 04:50:01 +00:00
Simon Pilgrim 87ba905fe9 [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant models
The SandyBridge BMI tests are actually run on IvyBridge as that's the first lowest CPU that actually support the ISAs (but still use the SandyBridge model).

llvm-svn: 330556
2018-04-22 20:42:24 +00:00
Robert Widmann 12e367b6db [LLVM-C] Add DIBuilder Bindings For Variable Creation
Summary: Wrap LLVMDIBuilderCreateAutoVariable, LLVMDIBuilderCreateParameterVariable, LLVMDIBuilderCreateExpression, and move and correct LLVMDIBuilderInsertDeclareBefore and LLVMDIBuilderInsertDeclareAtEnd from the Go bindings to the C bindings.

Reviewers: harlanhaskins, whitequark, deadalnix

Reviewed By: harlanhaskins, whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45928

llvm-svn: 330555
2018-04-22 19:24:44 +00:00
Simon Pilgrim 06e16541ba [X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides.
Fixed a lot of the default classes which were being completely overridden.

llvm-svn: 330554
2018-04-22 18:35:53 +00:00
Simon Pilgrim 091680b6e7 [X86] Remove unnecessary WriteFMul/WriteFRcp/WriteFRsqrt InstRW overrides.
llvm-svn: 330553
2018-04-22 18:09:50 +00:00
Sanjay Patel 30be665e82 [PatternMatch] allow undef elements when matching a vector zero
This is the last step in getting constant pattern matchers to allow
undef elements in constant vectors.

I'm adding a dedicated m_ZeroInt() function and building m_Zero() from
that. In most cases, calling code can be updated to use m_ZeroInt()
directly when there's no need to match pointers, but I'm leaving that
efficiency optimization as a follow-up step because it's not always
clear when that's ok.

There are just enough icmp folds in InstSimplify that can be used for 
integer or pointer types, that we probably still want a generic m_Zero()
for those cases. Otherwise, we could eliminate it (and possibly add a
m_NullPtr() as an alias for isa<ConstantPointerNull>()).

We're conservatively returning a full zero vector (zeroinitializer) in
InstSimplify/InstCombine on some of these folds (see diffs in InstSimplify),
but I'm not sure if that's actually necessary in all cases. We may be 
able to propagate an undef lane instead. One test where this happens is 
marked with 'TODO'.
 

llvm-svn: 330550
2018-04-22 17:07:44 +00:00
Sanjay Patel c1265ab99e [InstCombine] add vector test with undef elts; NFC
llvm-svn: 330547
2018-04-22 15:59:14 +00:00
Simon Pilgrim ef8d3ae4b5 [X86] Fix (completely overridden) WriteFHAdd/WritePHAdd classes to allow us to remove unnecessary instrw overrides.
llvm-svn: 330546
2018-04-22 15:25:59 +00:00
Simon Pilgrim 2fd8269c6f [X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd
llvm-svn: 330545
2018-04-22 15:02:23 +00:00
Simon Pilgrim 96855ec39e [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.
This also fixes some of the ReadAfterLd issues due to InstRW.

llvm-svn: 330544
2018-04-22 14:43:12 +00:00
Sanjay Patel e187cd3273 [InstSimplify, InstCombine] add vector tests with undef elts; NFC
llvm-svn: 330543
2018-04-22 14:19:37 +00:00
Simon Pilgrim a41ae2f005 [X86] Fix WriteMPSAD/WritePSADBW values to allow us to remove unnecessary instrw overrides.
llvm-svn: 330542
2018-04-22 10:39:16 +00:00
Simon Pilgrim 5e9f1da0cd [llvm-mca][X86] Add POPCNT resource test
llvm-svn: 330540
2018-04-22 09:58:00 +00:00
Jonas Devlieghere 3eecf73b10 [test] Fix MC/ELF/nocompression.s
Unbreak the linux build bots:
  http://lab.llvm.org:8011/builders/clang-lld-x86_64-2stage/builds/5165/
  http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/28775
  http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/8227

llvm-svn: 330539
2018-04-22 08:46:27 +00:00
Jonas Devlieghere c976aa7dc7 [llvm-mc] Make error handling more consistent.
Makes error handling more consistent by using the helpers in support.

llvm-svn: 330536
2018-04-22 08:01:35 +00:00
Craig Topper e33ed7d667 [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode.
Improve the error messages to match GNU assembler.

This also allows us to remove the hack from the disassembler table building.

llvm-svn: 330531
2018-04-22 00:52:02 +00:00
Brian Gesiak b13588982f [bcanalyzer] Recognize more stream types
Summary:
`llvm-bcanalyzer` prints out the stream type of the file it is
analyzing. If the file begins with the LLVM IR magic number, it reports
a stream type of "LLVM IR". However, any other bitstream format is
reported as "unknown".

Add some checks for two other common bitstream formats: Clang AST
files, which begin with 'CPCH', and Clang serialized diagnostics, which
begin with 'DIAG'.

Test Plan: `check-llvm`

Reviewers: pcc, aprantl, mehdi_amini, davide, george.karpenkov, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: JDevlieghere, bruno, davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D41979

llvm-svn: 330529
2018-04-21 23:52:04 +00:00
Craig Topper fe59bea07b [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.
Ultimately I want to use this to remove the intrinsics for these instructions.

llvm-svn: 330520
2018-04-21 18:39:21 +00:00
Craig Topper 1b223e75da [X86] Add test cases that show the current codegen for (trunc (srl (mul ext, ext), 16)). NFC
A future patch will turn this into MULHU/MULHS.

llvm-svn: 330519
2018-04-21 18:39:20 +00:00
Sanjay Patel 5f845732ed [InstSimplify] move tests for shifts; NFC
llvm-svn: 330516
2018-04-21 16:58:00 +00:00
Sanjay Patel d0b27a1156 [InstSimplify] move/add/regenerate checks for tests; NFC
llvm-svn: 330515
2018-04-21 16:23:47 +00:00
Simon Pilgrim e25aa02bc4 [llvm-mca][X86] Add AVX2 resource tests
llvm-svn: 330512
2018-04-21 16:12:42 +00:00
Simon Pilgrim d73bd154d9 [llvm-mca][X86] Add SSE resource tests to all models
llvm-svn: 330506
2018-04-21 14:16:57 +00:00
Simon Pilgrim 26178d4336 [llvm-mca][X86] Add MMX resource tests
llvm-svn: 330502
2018-04-21 11:28:59 +00:00
Simon Pilgrim 1264066cd7 [llvm-mca][X86] Add X87 resource tests
llvm-svn: 330499
2018-04-21 10:36:19 +00:00
Simon Pilgrim 342cf58668 [X86][X87] Add missing fldlg2 schedule test
llvm-svn: 330498
2018-04-21 10:35:04 +00:00
Hiroshi Inoue 33486787cb [PowerPC] fix incorrect vectorization of abs() on POWER9
Vectorized loops with abs() returns incorrect results on POWER9. This patch fixes it.
For example the following code returns negative result if input values are negative though it sums up the absolute value of the inputs.

int vpx_satd_c(const int16_t *coeff, int length) {
  int satd = 0;
  for (int i = 0; i < length; ++i) satd += abs(coeff[i]);
  return satd;
}

This problem causes test failures for libvpx.
For vector absolute and vector absolute difference on POWER9, LLVM generates VABSDUW (Vector Absolute Difference Unsigned Word) instruction or variants.
Since these instructions are for unsigned integers, we need adjustment for signed integers.
For abs(sub(a, b)), we generate VABSDUW(a+0x80000000, b+0x80000000). Otherwise, abs(sub(-1, 0)) returns 0xFFFFFFFF(=-1) instead of 1. For abs(a), we generate VABSDUW(a+0x80000000, 0x80000000).

Differential Revision: https://reviews.llvm.org/D45522

llvm-svn: 330497
2018-04-21 09:32:17 +00:00
Eli Friedman 0644130612 [AArch64] Don't crash trying to resolve __stack_chk_guard.
In certain cases, the compiler might try to merge __stack_chk_guard with
another global variable.  (Or someone could theoretically define
__stack_chk_guard as an alias.)  In that case, make sure we don't crash.

Differential Revision: https://reviews.llvm.org/D45746

llvm-svn: 330495
2018-04-21 00:07:46 +00:00
Jessica Paquette e5d279e6d6 Fix typo in test (verify-machine-instrs -> verify-machineinstrs)
llvm-svn: 330494
2018-04-20 23:37:48 +00:00
Jessica Paquette d442c3a632 [MachineOutliner] XFAIL machine-outliner-noredzone.ll
The verifier began complaining about an undefined physical register in this
test. XFAILing for the purposes of getting a bot up while I look into it.

Failure:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/11385/

llvm-svn: 330493
2018-04-20 23:35:54 +00:00
Shoaib Meenai d64b83266b [ObjCARC] Account for funclet token in storeStrong transform
When creating a call to storeStrong in ObjCARCContract, ensure the call
gets the correct funclet token, otherwise WinEHPrepare will turn the
call (and all subsequent instructions) into unreachable.

We already have logic to do this for the ARC autorelease elision marker;
factor that out into a common function that's used for both. These are
the only two places in this transform that create call instructions.

Differential Revision: https://reviews.llvm.org/D45857

llvm-svn: 330487
2018-04-20 22:11:03 +00:00
Simon Pilgrim 1803bfb75f [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests
llvm-svn: 330486
2018-04-20 22:04:11 +00:00
Simon Pilgrim d14d2e7b18 [X86] Add WriteFSign/WriteFLogic scheduler classes
Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.

This unearthed a couple of things that are also handled in this patch:

(1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.

Differential Revision: https://reviews.llvm.org/D45629

llvm-svn: 330480
2018-04-20 21:16:05 +00:00
Alexander Shaposhnikov 52db4335b3 [llvm-objcopy] Fix sh_link
This diff fixes sh_link for various types of sections 
(i.e. for SHT_ARM_EXIDX, SHT_HASH). In particular, this change enables us
to use llvm-objcopy with clang -gsplit-dwarf for the target android-arm.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D45851

llvm-svn: 330478
2018-04-20 20:46:04 +00:00
Alex Shlyapnikov 99cf54baa6 [HWASan] Introduce non-zero based and dynamic shadow memory (LLVM).
Summary:
Support the dynamic shadow memory offset (the default case for user
space now) and static non-zero shadow memory offset
(-hwasan-mapping-offset option). Keeping the the latter case around
for functionality and performance comparison tests (and mostly for
-hwasan-mapping-offset=0 case).

The implementation is stripped down ASan one, picking only the relevant
parts in the following assumptions: shadow scale is fixed, the shadow
memory is dynamic, it is accessed via ifunc global, shadow memory address
rematerialization is suppressed.

Keep zero-based shadow memory for kernel (-hwasan-kernel option) and
calls instreumented case (-hwasan-instrument-with-calls option), which
essentially means that the generated code is not changed in these cases.

Reviewers: eugenis

Subscribers: srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D45840

llvm-svn: 330475
2018-04-20 20:04:04 +00:00
Sean Fertile 18f17333dd [PartialInlining] Fix Crash from holding a reference to a destructed ORE.
The callback used to create an ORE for the legacy PI pass caches the allocated
object in a unique_ptr in the runOnModule function, and returns a reference to
that object. Under certian circumstances we can end up holding onto that
reference after the OREs destruction. Rather then allowing the new and legacy
passes to create ORE object in diffrent ways, create the ORE at the point of
use.

Differential Revision: https://reviews.llvm.org/D43219

llvm-svn: 330473
2018-04-20 19:56:26 +00:00
Krzysztof Parzyszek 41a24b7b13 [Hexagon] Improve HVX instruction selection (bitcast, vsplat)
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.

llvm-svn: 330471
2018-04-20 19:38:37 +00:00
Krzysztof Parzyszek 642120122c [Hexagon] Skip fixed-stack indexes in HexagonConstExtenders
Fixed slots have negative values, and TRI::stackSlot2Index and
TRI::index2StackSlot do not handle negative numbers.

llvm-svn: 330468
2018-04-20 19:06:46 +00:00
Gabor Buella 31fa8025ba [X86] WaitPKG instructions
Three new instructions:

umonitor - Sets up a linear address range to be
monitored by hardware and activates the monitor.
The address range should be a writeback memory
caching type.

umwait - A hint that allows the processor to
stop instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.

tpause - Directs the processor to enter an
implementation-dependent optimized state
until the TSC reaches the value in EDX:EAX.

Also modifying the description of the mfence
instruction, as the rep prefix (0xF3) was allowed
before, which would conflict with umonitor during
disassembly.

Before:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
mfence

After:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
umonitor        %rax

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45253

llvm-svn: 330462
2018-04-20 18:42:47 +00:00
Jessica Paquette 2e5ada5c81 [MachineOutliner] Change B instruction for tail calls to TCRETURNdi
First off, this is more correct than having the B. Second off, this was making
a bot upset. This fixes that.

Update the test to include -verify-machineinstrs as well to prevent stuff like
this slipping by non debug/assert builds in the future.

llvm-svn: 330459
2018-04-20 18:03:21 +00:00
Sanjay Patel f04ab64b25 [x86] auto-generate checks; NFC
There's a proposal to change/add to this file in D45653,
so we should know exactly what those differences would be. 

llvm-svn: 330445
2018-04-20 16:46:58 +00:00
Florian Hahn 773872fd67 [NewGVN] Split OpPHI detection and creation.
It also adds a check making sure PHIs for operands are all in the same
block.

Patch by Daniel Berlin <dberlin@dberlin.org>

Reviewers: dberlin, davide

Differential Revision: https://reviews.llvm.org/D43865

llvm-svn: 330444
2018-04-20 16:37:13 +00:00
Andrew Ng 7a2fa74ab0 [DebugInfo] Use WithColor for more debug line warnings
Updated two more debug line related warnings to use WithColor. This was
necessary to ensure consistent output order of the warnings on Windows
for debug line tests.

Differential Revision: https://reviews.llvm.org/D45871

llvm-svn: 330440
2018-04-20 15:29:47 +00:00
Simon Pilgrim ab9798765c [CostModel][X86] Add vector element insert/extract cost tests
llvm-svn: 330439
2018-04-20 15:26:59 +00:00
Douglas Yung 51db3abac8 Fix test by allowing it to accept an upper or lower case letter as the first character.
Windows for some reason uses a lower case letter, while linux uses upper case.

llvm-svn: 330438
2018-04-20 15:23:57 +00:00
Sanjay Patel 3d453ad711 [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This was originally committed at rL328921 and reverted at rL329920 to
investigate failures in Chrome. This time I've added to the ReleaseNotes
to warn users of the potential of exposing UB and let me repeat that
here for more exposure:

  Optimization of floating-point casts is improved. This may cause surprising
  results for code that is relying on undefined behavior. Code sanitizers can
  be used to detect affected patterns such as this:

    int main() {
      float x = 4294967296.0f;
      x = (float)((int)x);
      printf("junk in the ftrunc: %f\n", x);
      return 0;
    }

    $ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out
    ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of 
                   representable values of type 'int'
    junk in the ftrunc: 0.000000


Original commit message:

fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.

Differential Revision: https://reviews.llvm.org/D44909

llvm-svn: 330437
2018-04-20 15:07:55 +00:00
Simon Pilgrim 863ffeb750 [CostModel][X86] Add srem/urem constant cost tests
llvm-svn: 330436
2018-04-20 15:01:03 +00:00
Simon Pilgrim 8a15d72550 [CostModel][X86] Add SLM/GLM/BtVer2 compare + division/remainder cost tests
llvm-svn: 330435
2018-04-20 14:50:34 +00:00
Michael Zolotukhin f79d15e432 Fix typo in a test.
llvm-svn: 330434
2018-04-20 13:51:36 +00:00
Simon Pilgrim cd9ccf8824 [CostModel][X86] Split off BtVer2 cost checks
llvm-svn: 330433
2018-04-20 13:50:33 +00:00
Simon Pilgrim 25b7782975 [CostModel][X86] Add GoldmontPlus cost tests
Just reuses goldmont costs atm

llvm-svn: 330432
2018-04-20 13:42:53 +00:00
Michael Zolotukhin a2c9af0209 Revert "Revert r330403 and r330413."
Reapply the patches with a fix. Thanks Ilya and Hans for the reproducer!
This reverts commit r330416.

The issue was that removing predecessors invalidated uses that we stored
for rewrite. The fix is to finish manipulating with CFG before we select
uses for rewrite.

llvm-svn: 330431
2018-04-20 13:34:32 +00:00
Sander de Smalen 30f9f11d51 [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45690

llvm-svn: 330423
2018-04-20 12:52:01 +00:00
Florian Hahn 3085cdc99e Require asserts for stats-file-option tests.
llvm-svn: 330417
2018-04-20 11:21:13 +00:00
Ilya Biryukov afe822bd6d Revert r330403 and r330413.
Revert r330413: "[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites."
Revert r330403 "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."

r330403 commit seems to crash clang during our integrate while doing PGO build with the following stacktrace:
      #2 llvm::SSAUpdaterBulk::RewriteAllUses(llvm::DominatorTree*, llvm::SmallVectorImpl<llvm::PHINode*>*)
      #3 llvm::JumpThreadingPass::ThreadEdge(llvm::BasicBlock*, llvm::SmallVectorImpl<llvm::BasicBlock*> const&, llvm::BasicBlock*)
      #4 llvm::JumpThreadingPass::ProcessThreadableEdges(llvm::Value*, llvm::BasicBlock*, llvm::jumpthreading::ConstantPreference, llvm::Instruction*)
      #5 llvm::JumpThreadingPass::ProcessBlock(llvm::BasicBlock*)
The crash happens while compiling 'lib/Analysis/CallGraph.cpp'.

r3340413 is reverted due to conflicting changes.

llvm-svn: 330416
2018-04-20 10:52:54 +00:00
Roman Lebedev f6934d725b [NFC][InstCombine] Regenerate two tests that are affected by folding masked merge
llvm-svn: 330415
2018-04-20 10:49:19 +00:00
Andrew Ng a6763bfd6d [DebugInfo] Fix for split dwarf test on Windows (NFC)
On Windows, %llc_dwarf automatically adds -mtriple causing this test to
error. Changed %llc_dwarf to llc.

Differential Revision: https://reviews.llvm.org/D45869

llvm-svn: 330414
2018-04-20 10:44:42 +00:00
Florian Hahn d4332eb3b7 [LTO] Add stats-file option to LTO/Config.h.
This patch adds a StatsFile option to LTO/Config.h and updates both
LLVMGold and llvm-lto2 to set it.

Reviewers: MatzeB, tejohnson, espindola

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D45531

llvm-svn: 330411
2018-04-20 10:18:36 +00:00
Sander de Smalen 137efb231e [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:
Diagnostic:
  'index must be multiple of 3 in range [-32, 28]'

Must be:
  'index must be multiple of 4 in range [-32, 28]'

llvm-svn: 330407
2018-04-20 09:45:50 +00:00
Michael Zolotukhin 79e4f7fadb Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
Hopefully, changing set to vector removes nondeterminism detected by
some bots, or the new assert will catch something.

This reverts commit r330180.

llvm-svn: 330403
2018-04-20 08:01:08 +00:00
Daniel Cederman 4557178061 Revert "This pass, fixing an erratum in some LEON 2 processors..."
Summary:
Reading Atmel's AT697E errata document this does not seem like a valid
workaround. While the text only mentions SDIV, it says that the ICC flags
can be wrong, and those are only generated by SDIVcc. Verification on
hardware shows that simply replacing SDIV with SDIVcc does not avoid
the bug with negative operands.

This reverts r283727.

Reviewers: lero_chris, jyknight

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45813

llvm-svn: 330397
2018-04-20 07:53:27 +00:00
Daniel Cederman c67b3ffba7 [Sparc] Use synthetic instruction clr to zero register instead of sethi
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45810

llvm-svn: 330396
2018-04-20 07:47:12 +00:00
Nicolai Haehnle 7a87977fb2 AMDGPU: Legalize the operand of SI_INIT_M0
Summary:
This fixes a case where the argument to a sendmsg intrinsic
ends up in a VGPR, for whatever reason.

The underlying performance issue is that a multiplication that
can be an s_mul_i32 is instead needlessly generated as
v_mul_u32_u24, but this is not addressed by this patch.

Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45826

llvm-svn: 330393
2018-04-20 07:14:25 +00:00
Daniel Cederman 793af3b9f0 [Sparc] Fix addressing mode when using 64-bit values in inline assembly
Summary:
If a 64-bit register is used as an operand in inline assembly together
with a memory reference, the memory addressing will be wrong. The
addressing will be a single reg, instead of reg+reg or reg+imm. This
will generate a bad offset value or an exception in printMemOperand().

For example:

```
long long int val = 5;
long long int mem;
__asm__ volatile ("std %1, %0":"=m"(mem):"r"(val));
```
becomes:

```
std %i0, [%i2+589833]
```

The problem is that SelectInlineAsmMemoryOperand() is never called for
the memory references if one of the operands is a 64-bit register.
By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc
version of  SelectInlineAsmMemoryOperand() gets called for each memory
reference.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45761

llvm-svn: 330392
2018-04-20 06:57:49 +00:00
Vlad Tsyrklevich 5d15230c37 Fix build failures for r330387 on buildbots that don't build the X86 target
llvm-svn: 330388
2018-04-20 02:26:12 +00:00
Vlad Tsyrklevich 230b256783 LowerTypeTests: Propagate symver directives
Summary:
This change fixes https://crbug.com/834474, a build failure caused by
LowerTypeTests not preserving .symver symbol versioning directives for
exported functions. Emit symver information to ThinLTO summary data and
then propagate symver directives for exported functions to the merged
module.

Emitting symver information to the summaries increases the size of
intermediate build artifacts for a Chromium build by less than 0.2%.

Reviewers: pcc

Reviewed By: pcc

Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc

Differential Revision: https://reviews.llvm.org/D45798

llvm-svn: 330387
2018-04-20 01:36:48 +00:00
Simon Pilgrim 0a6bfb1843 [llvm-mca][X86] Add prefetch instruction resource tests
llvm-svn: 330371
2018-04-19 22:11:58 +00:00
Sam Clegg f009da2448 [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF directive parser.
This is a temporary solution until a proper WASM implementation of
MCAsmParserExtension is in place, but at least for now will unblock this
path.

Added test to make sure this path works with the WASM Assembler.

Patch By Wouter van Oortmerssen!

Differential Revision: https://reviews.llvm.org/D45386

llvm-svn: 330370
2018-04-19 22:00:53 +00:00
Sanjay Patel ad8976db16 [Reassociate] add baseline tests for binop swapping; NFC
Similar to rL330086, I don't know if we want to do these 
transforms here, but we might as well have the tests
here either way to show that this pass is missing 
potential functionality (intentionally or not).

llvm-svn: 330368
2018-04-19 21:56:17 +00:00
Simon Pilgrim 7209117868 [llvm-mca][FMA] Add FMA resource tests
llvm-svn: 330366
2018-04-19 21:32:22 +00:00