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Author SHA1 Message Date
Vladimir Medic 64828a1f73 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
llvm-svn: 186397
 2013-07-16 10:07:14 +00:00
Vladimir Medic bcf1ca08e0 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 186151
 2013-07-12 09:25:35 +00:00
Vladimir Medic 524ad0e46e Reverting commit r185999 due to buildboot failure. 
llvm-svn: 186000
 2013-07-10 12:26:26 +00:00
Vladimir Medic e84de1e101 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 185999
 2013-07-10 10:18:10 +00:00
Akira Hatanaka 1cb024207f [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
 2013-05-20 18:07:43 +00:00
Akira Hatanaka f0aa6c9101 [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180241
 2013-04-25 01:21:25 +00:00
Akira Hatanaka cd9b74a599 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180238
 2013-04-25 01:11:15 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
 2013-04-19 19:03:11 +00:00
Akira Hatanaka 061d1ea5da [mips] Add definition of JALR instruction which has two register operands. Change the 
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
 2013-02-07 19:48:00 +00:00
Akira Hatanaka 556135d813 [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0". 
llvm-svn: 174546
 2013-02-06 21:50:15 +00:00
Akira Hatanaka e067e5a13f [mips] 80 columns. 
llvm-svn: 171515
 2013-01-04 19:38:05 +00:00
Akira Hatanaka e36e2f6876 [mips] Refactor instructions which move data from or to coprocessors. 
llvm-svn: 171510
 2013-01-04 19:13:49 +00:00
Akira Hatanaka 6ac2fc4976 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.

llvm-svn: 170956
 2012-12-21 23:21:32 +00:00
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions. 
llvm-svn: 170955
 2012-12-21 23:17:36 +00:00
Akira Hatanaka 31ddec5887 [mips] Refactor BAL instructions. 
llvm-svn: 170954
 2012-12-21 23:15:59 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
llvm-svn: 170952
 2012-12-21 23:03:50 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction. 
llvm-svn: 170944
 2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions. 
llvm-svn: 170942
 2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions. 
llvm-svn: 170940
 2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers. 
llvm-svn: 170939
 2012-12-21 22:39:17 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 

llvm-svn: 170664
 2012-12-20 04:27:52 +00:00
Akira Hatanaka bbd197e9c4 [mips] Refactor unconditional branch instruction. Separate encoding information 
from the rest. 

llvm-svn: 170663
 2012-12-20 04:22:39 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.

llvm-svn: 170648
 2012-12-20 03:40:03 +00:00
Akira Hatanaka 1b37c4af01 [mips] Refactor arithmetic and logic instructions. Separate encoding 
information from the rest.

llvm-svn: 170647
 2012-12-20 03:34:05 +00:00
Akira Hatanaka b2cc8a756f [mips] Delete all floating point instruction classes that are no longer used. 
No functionality change.

llvm-svn: 170084
 2012-12-13 02:05:02 +00:00
Akira Hatanaka 6262bbf819 [mips] Modify definitions of floating point conditional move instructions. 
No functionality change.

llvm-svn: 170080
 2012-12-13 01:41:15 +00:00
Akira Hatanaka 79e1cdb00b [mips] Modify definitions of floating point comparison instructions. 
No functionality change.

llvm-svn: 170077
 2012-12-13 01:34:09 +00:00
Akira Hatanaka fd9163b74c [mips] Modify definitions of floating point branch instructions. 
No functionality change.

llvm-svn: 170076
 2012-12-13 01:32:36 +00:00
Akira Hatanaka cd3dfd238e [mips] Modify definitions of floating point indexed load and store instructions. 
No functionality change.

llvm-svn: 170075
 2012-12-13 01:30:49 +00:00
Akira Hatanaka b0d4acbc65 [mips] Modify definitions of floating point multiply-add/sub instructions. 
No functionality change.

llvm-svn: 170073
 2012-12-13 01:27:48 +00:00
Akira Hatanaka 92994f4846 [mips] Modify definitions of floating point load and store instructions. 
No functionality change.

llvm-svn: 170072
 2012-12-13 01:24:00 +00:00
Akira Hatanaka 2b75dde5fa [mips] Modify definitions of move from/to coprocessor instructions. 
No functionality change.

llvm-svn: 170071
 2012-12-13 01:16:49 +00:00
Akira Hatanaka dea8f61ae0 [mips] Modify definitions of two register operand floating point instructions. 
No functionality change.

llvm-svn: 170069
 2012-12-13 01:14:07 +00:00
Akira Hatanaka 29b513871a [mips] Modify definitions of three register operand floating point instructions 
and separate encoding information from the rest.

llvm-svn: 170066
 2012-12-13 01:07:37 +00:00
Akira Hatanaka 84693d5606 [mips] Move classes that do not belong in MipsInstrFormats.td into 
MipsInstrFPU.td.
 

llvm-svn: 170061
 2012-12-13 00:49:23 +00:00
Akira Hatanaka caaf4dd516 [mips] Remove single-precision floating point instruction from multiclass 
FFR2P_M.
 

llvm-svn: 170055
 2012-12-13 00:35:54 +00:00
Akira Hatanaka e986a59ad9 [mips] Remove single-precision floating point instructions from multiclasses 
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053
 2012-12-13 00:29:29 +00:00
Akira Hatanaka 97e179f9e4 [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Jack Carter e948ec52d1 Adding support for instructions mfc0, mfc2, mtc0, mtc2 
move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic
llvm-svn: 165351
 2012-10-06 01:17:37 +00:00
Jack Carter 30a5982e75 Implement methods that enable expansion of load immediate 
macro instruction (li) in the assembler.

We have identified three possible expansions depending on 
the size of immediate operand:
  1) for 0 ≤ j ≤ 65535.
     li d,j =>
     ori d,$zero,j

  2) for −32768 ≤ j < 0.
     li d,j =>
     addiu d,$zero,j

  3) for any other value of j that is representable as a 32-bit integer.
     li d,j =>
     lui d,hi16(j)
     ori d,d,lo16(j)

All of the above have been implemented in ths patch.

Contributer: Vladimir Medic
llvm-svn: 165199
 2012-10-04 04:03:53 +00:00
Akira Hatanaka a66d676b20 Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether 
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071
 2012-07-31 19:13:07 +00:00
Akira Hatanaka 3a810eda91 Change name of class MipsInst to InstSE to distinguish it from mips16's 
instruction class. SE stands for standard encoding.

llvm-svn: 161069
 2012-07-31 18:55:01 +00:00
Akira Hatanaka cdf4fd8267 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Akira Hatanaka 71928e681b Add disassembler to MIPS. 
Patch by Vladimir Medic. 

llvm-svn: 154935
 2012-04-17 18:03:21 +00:00
Akira Hatanaka 55059262aa Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00
Akira Hatanaka e2498d014b MIPS disassembler support. 
Patch by Vladimir Medic.

llvm-svn: 153924
 2012-04-03 02:20:58 +00:00
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode 
load and store instructions.

llvm-svn: 151611
 2012-02-28 02:55:02 +00:00
Akira Hatanaka 60f7a8e710 Add definitions of floating point multiply add/sub and negative multiply 
add/sub instructions.

llvm-svn: 151415
 2012-02-25 00:21:52 +00:00
Bruno Cardoso Lopes 0c24d8a406 Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter 
llvm-svn: 145912
 2011-12-06 03:34:48 +00:00
Bruno Cardoso Lopes 2312a3aaa0 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Akira Hatanaka 975bfc9b45 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka 4b6ac98fcf Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Akira Hatanaka 2365f90676 Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka 13ae13bdc2 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Akira Hatanaka bb050745e7 Mark MipsPseudo isPseudo. 
llvm-svn: 140598
 2011-09-27 04:57:54 +00:00
Akira Hatanaka eea541ce4e Changed definition of EXT and INS per Bruno's comments. 
llvm-svn: 137892
 2011-08-17 22:59:46 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Eric Christopher 5dc19f916c Fix td file comments for Mips. 
Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086
 2011-05-09 18:16:46 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Akira Hatanaka a535270d91 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Bruno Cardoso Lopes 7ceec57703 Fixe typos and 80 column size problems 
llvm-svn: 53272
 2008-07-09 04:45:36 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most 
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
 2008-07-05 19:05:21 +00:00
Bruno Cardoso Lopes 041604ba9f Added FP instruction formats. 
llvm-svn: 52086
 2008-06-08 01:39:36 +00:00
Bruno Cardoso Lopes 4eed3afda0 Added custom SELECT_CC lowering 
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC

llvm-svn: 52031
 2008-06-06 00:58:26 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes 5cef9cfd09 Position Independent Code (PIC) support [1] 
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778
 2007-10-09 02:55:31 +00:00
Bruno Cardoso Lopes d4b9945a21 Instruction Itinerary attribution fixed 
llvm-svn: 41224
 2007-08-21 16:06:45 +00:00
Bruno Cardoso Lopes 5792189590 Added InstrItinClass support for instruction formats 
llvm-svn: 41156
 2007-08-18 02:01:28 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Bruno Cardoso Lopes 35e43c49b0 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00