21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
f98f124a73
Sink InstructionSelect() out of each target into SDISel, and rename it
...
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
2010-03-02 06:34:30 +00:00
5e73ff2e3a
Split SelectionDAGISel::IsLegalAndProfitableToFold to
...
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
2010-02-15 19:41:07 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
ea6f91ff64
Change SelectCode's argument from SDValue to SDNode *, to make it more
...
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
d91a14dba5
Fix invalid chain folding for memory variant of sdiv / udiv
...
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
...
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
32f71d714b
Rename getTargetNode to getMachineNode, for consistency with the
...
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
llvm-svn: 82790
2009-09-25 18:54:59 +00:00
34ee203337
Fix some refactos for iostream changes (in -Asserts mode).
...
- The world needs better C++ refactoring tools, can I get an Amen!?
llvm-svn: 79843
2009-08-23 08:50:52 +00:00
317dbbcfb1
eliminate uses of cerr()
...
llvm-svn: 79834
2009-08-23 07:05:07 +00:00
af29ea6d57
eliminate the last DOUTs from the targets.
...
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
7ecc62d8c1
Fix 'may be used uninitialized' warning.
...
- Anton, please review.
llvm-svn: 76144
2009-07-17 02:19:26 +00:00
02fc607d54
Unbreak
...
llvm-svn: 76064
2009-07-16 14:36:52 +00:00
3ae30e08ef
Fix logic inversion for RI-mode address selection
...
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
70d0bceed6
Unbreak mvi and friends - emit only 'significant' part of the operand
...
llvm-svn: 76041
2009-07-16 14:26:38 +00:00
b25949b0f5
Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
...
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
e5b04d7102
Use divide single for 32 bit signed divides
...
llvm-svn: 76010
2009-07-16 14:17:52 +00:00
e0ad108f04
Remove redundand register move
...
llvm-svn: 76004
2009-07-16 14:14:54 +00:00
fe8df8ff61
Properly handle divides. As a bonus - implement memory versions of them.
...
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
34ad780d0d
32 bit shifts have only 12 bit displacements
...
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
d8458e6c09
Typos
...
llvm-svn: 75991
2009-07-16 14:10:35 +00:00
1eb6262b4b
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
...
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
62f8515b1c
Add support for 12 bit displacements
...
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
ec66c122e0
32-bit ri addressing mode has only 12-bit displacement
...
llvm-svn: 75973
2009-07-16 14:03:41 +00:00
8a095bf56d
Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common
...
llvm-svn: 75937
2009-07-16 13:48:42 +00:00
19911b338a
Do not truncate sign bits for negative imms
...
llvm-svn: 75936
2009-07-16 13:48:23 +00:00
405833dfb6
Add address computation stuff
...
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
44f8bbfb3f
Add stores and truncstores
...
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
11b91b4e2e
Add patterns for various extloads
...
llvm-svn: 75930
2009-07-16 13:44:30 +00:00
0179364392
Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
...
llvm-svn: 75929
2009-07-16 13:44:00 +00:00
04be818918
Add shifts and reg-imm address matching
...
llvm-svn: 75927
2009-07-16 13:43:18 +00:00
ebe2de0e14
Add bunch of reg-imm movs
...
llvm-svn: 75921
2009-07-16 13:34:50 +00:00
28234bcde2
Provide masked reg-imm 'or' and 'and'
...
llvm-svn: 75919
2009-07-16 13:33:57 +00:00
c334c28b3b
Let's start another backend :)
...
llvm-svn: 75909
2009-07-16 13:27:25 +00:00
Dan Gohman