OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
308,693 Commits 32 Branches 0 Tags 2.2 GiB
Commit Graph

18337 Commits

Author SHA1 Message Date
Chris Lattner e86f98e06c Add load/store instructions 
llvm-svn: 4711
 2002-11-17 20:33:12 +00:00
Chris Lattner 09fddd97fb Switch visitRet to use getClass() 
llvm-svn: 4710
 2002-11-17 20:07:45 +00:00
Brian Gaeke e74543584a include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline 
convenience method.  Fix typo in comment.
lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses.
 Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions.
 Take out LEAVE instructions.
 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo).
 Fix typo in comment and remove some FIXME comments.
lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h.
 Add some simple code to Printer::runOnFunction to iterate over
  MachineBasicBlocks and call X86InstrInfo::print().
lib/Target/X86/X86InstrInfo.def: Make some more instructions with
 implicit defs "Void".  Add more sign/zero extending "move" insns
 (movsx, movzx).
lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register.

llvm-svn: 4707
 2002-11-14 22:32:30 +00:00
Brian Gaeke b2687880e2 InstSelectSimple.cpp: (visitReturnInst) Add return instructions with return 
values.
X86InstrInfo.def: add LEAVE instruction.

llvm-svn: 4691
 2002-11-11 19:37:09 +00:00
Brian Gaeke 9cbe229704 Add instruction selection code and tests for setcc instructions 
llvm-svn: 4603
 2002-11-07 17:59:21 +00:00
Chris Lattner 781986c436 Implement signed and unsigned division and remainder 
llvm-svn: 4508
 2002-11-02 20:54:46 +00:00
Chris Lattner d12e1bc777 Implement multiply operator 
llvm-svn: 4506
 2002-11-02 20:28:58 +00:00
Chris Lattner e823fb32f4 * Implement subtract 
* Merge add code into logical code

llvm-svn: 4503
 2002-11-02 20:13:22 +00:00
Chris Lattner dd873d2179 shuffle code around a bit, implement and, or, xor 
llvm-svn: 4502
 2002-11-02 20:04:26 +00:00
Chris Lattner abe3280ad9 Add PHI node support, add comment for branch function 
llvm-svn: 4500
 2002-11-02 19:45:49 +00:00
Chris Lattner 16af2d5aa8 Implement unconditional branching support 
llvm-svn: 4498
 2002-11-02 19:27:56 +00:00
Chris Lattner cfb187f6bb * Fix nonconstant shift case 
* Turn table into 2d table

llvm-svn: 4496
 2002-11-02 01:41:55 +00:00
Chris Lattner ff3d28f403 Use a more table driven approach to handling types. Seems to simplify the 
code a bit

llvm-svn: 4493
 2002-11-02 01:15:18 +00:00
Chris Lattner 63f4e752cd Make switch statements denser, but only because of the follow-on patch 
llvm-svn: 4492
 2002-11-02 00:49:56 +00:00
Chris Lattner 122b73b7a6 * Remove dead variable 
* Shift amount is always guaranteed to be 8 bits

llvm-svn: 4491
 2002-11-02 00:44:25 +00:00
Brian Gaeke 6e2d676829 InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst. 
Add ISel::visitShiftInst() to instruction select shift instructions.
 Add a comment in visitAdd about how to do 64 bit adds.

X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes.

llvm-svn: 4477
 2002-10-31 23:03:59 +00:00
Chris Lattner 6c34c0baf5 Add lots more info 
llvm-svn: 4450
 2002-10-30 06:04:46 +00:00
Chris Lattner c9e1efd0f8 Make sure to set the destination register correctly 
llvm-svn: 4444
 2002-10-30 01:49:01 +00:00
Chris Lattner 87b84a6913 Set the destination register field based on the target specific flags 
llvm-svn: 4442
 2002-10-30 01:15:31 +00:00
Chris Lattner 60c59d5b4e Add flag to specify when no value is produced by an instruction 
llvm-svn: 4441
 2002-10-30 01:09:34 +00:00
Chris Lattner 858a4a6595 Implement the new optional getRegisterInfo 
llvm-svn: 4437
 2002-10-30 00:56:18 +00:00
Chris Lattner d7a855668d Print machine code after instruction selection 
llvm-svn: 4434
 2002-10-30 00:47:49 +00:00
Chris Lattner e3ceb17d54 Make sure to pass the LLVM basic block in 
llvm-svn: 4433
 2002-10-30 00:47:40 +00:00
Chris Lattner 7ee171b717 Construct annotation, to make sure it's attached to function 
llvm-svn: 4429
 2002-10-29 23:40:58 +00:00
Chris Lattner 02a3d837c2 Convert backend to use passes, implement X86TargetMachine 
llvm-svn: 4421
 2002-10-29 22:37:54 +00:00
Chris Lattner 27d247978b Rename X86InstructionInfo to X86InstrInfo 
llvm-svn: 4413
 2002-10-29 21:05:24 +00:00
Chris Lattner f57420ee17 Minor renaming 
llvm-svn: 4410
 2002-10-29 20:48:56 +00:00
Chris Lattner 2990e9b6cd Switch to generating machineinstr's instead of MInstructions 
llvm-svn: 4396
 2002-10-29 17:43:55 +00:00
Chris Lattner 6c3f9c1b8f Be compatible with sparc backend 
llvm-svn: 4395
 2002-10-29 17:43:38 +00:00
Chris Lattner 16cbd41c21 Implement MachineInstrInfo interface 
llvm-svn: 4394
 2002-10-29 17:43:19 +00:00
Chris Lattner f4b122dbc5 Switch to different flag set 
llvm-svn: 4393
 2002-10-29 17:42:40 +00:00
Chris Lattner 1303f2f057 Initial stab at MachineInstr'ication 
llvm-svn: 4367
 2002-10-28 23:55:19 +00:00
Misha Brukman d5b45791a4 Fixed spelling and grammar. 
llvm-svn: 4353
 2002-10-28 20:01:52 +00:00
Chris Lattner 52c2d10a19 Remove dead fixme 
llvm-svn: 4300
 2002-10-27 21:23:43 +00:00
Chris Lattner 7d3e5dbf2b Instruction select constant arguments correctly 
llvm-svn: 4297
 2002-10-27 21:16:59 +00:00
Chris Lattner 407582dc5a Add instruction definitions for mov r, imm instructions 
llvm-svn: 4296
 2002-10-27 21:16:44 +00:00
Chris Lattner d92fb0058b Initial checkin of X86 backend. 
We can instruction select exactly one instruction 'ret void'.  Wow.

llvm-svn: 4284
 2002-10-25 22:55:53 +00:00