454258671d
[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'
...
The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'.
llvm-svn: 341278
2018-09-01 12:23:00 +00:00
8b0f9d2e58
[AVR] Define the ROL instruction as an alias of ADC
...
The 'rol Rd' instruction is equivalent to 'adc Rd'.
This caused compile warnings from tablegen because of conflicting bits
shared between each instruction.
llvm-svn: 341275
2018-09-01 12:22:07 +00:00
820553fdb1
[AVR] Fix the testsuite after '%' changed to '$' in MIR
...
llvm-svn: 324583
2018-02-08 09:17:11 +00:00
f1141285eb
MIRTests: Remove unnecessary 2>&1 redirection
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llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.
llvm-svn: 295859
2017-02-22 18:47:41 +00:00
a5d49dfbb3
[AVR] Add tests for a large number of pseudo instructions
...
This adds MIR tests for 24 pseudo instructions.
llvm-svn: 289191
2016-12-09 07:49:04 +00:00
Dylan McKay