llvm-project

Commit Graph

Author	SHA1	Message	Date
Aleksandar Beserminji	f8f00e5065	[mips] Add missing instructions Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920	2018-08-29 11:35:03 +00:00
Daniel Sanders	07cdea2baa	[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546	2014-05-12 12:52:44 +00:00

Author

SHA1

Message

Date

Aleksandar Beserminji

f8f00e5065

[mips] Add missing instructions

Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.

Differential Revision: https://reviews.llvm.org/D50437

llvm-svn: 340920

2018-08-29 11:35:03 +00:00

Daniel Sanders

07cdea2baa

[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them

Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2

Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.

Depends on D3694

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3695

llvm-svn: 208546

2014-05-12 12:52:44 +00:00

2 Commits