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3 Commits

Author SHA1 Message Date
Simon Pilgrim e91feeed21 [AMDGPU] Add ISD::FSHR -> ALIGNBIT support 
This patch allows ISD::FSHR(i32) patterns to lower to ALIGNBIT instructions.

This improves test coverage of ISD::FSHR matching - x86 has both FSHL/FSHR instructions and we prefer FSHL by default.

Differential Revision: https://reviews.llvm.org/D76070
 2020-03-12 20:16:57 +00:00
Stanislav Mekhanoshin 7bec57300c [AMDGPU] Corrected computeKnownBits for V_PERM_B32 
Differential Revision: https://reviews.llvm.org/D48133

llvm-svn: 334640
 2018-06-13 18:52:54 +00:00
Stanislav Mekhanoshin 8fd3c4e431 [AMDGPU] DAG combine to produce V_PERM_B32 
Differential Revision: https://reviews.llvm.org/D48099

llvm-svn: 334559
 2018-06-12 23:50:37 +00:00