14c53b45f5
Added field noResults to Instruction.
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Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
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support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
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* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
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llvm-svn: 24556
2005-12-01 00:12:04 +00:00
e479ccb27b
fit into 80 columns
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llvm-svn: 24554
2005-11-30 23:58:18 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
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operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
63dc7f569a
spell this variable right
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llvm-svn: 23095
2005-08-26 20:42:52 +00:00
3d9fbefbf7
Expose a new flag to TargetInstrInfo
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llvm-svn: 23094
2005-08-26 20:40:46 +00:00
220d00109b
For now, just emit empty operand info structures.
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llvm-svn: 22910
2005-08-19 16:57:28 +00:00
17727bad02
Figure out how many operands each instruction has, keep track of whether
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or not it's variable.
llvm-svn: 22885
2005-08-18 23:38:41 +00:00
650ba8eb56
Remove trailing whitespace
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llvm-svn: 21428
2005-04-22 00:00:37 +00:00
733c82bfbf
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
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llvm-svn: 19243
2005-01-02 02:29:04 +00:00
996ddbc98e
Add support for the isLoad and isStore flags, needed by the instruction scheduler
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llvm-svn: 16554
2004-09-28 21:01:45 +00:00
9b0dfa3c0d
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
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llvm-svn: 16553
2004-09-28 18:38:01 +00:00
6ffa501d9f
Make the AsmWriter a first-class tblgen object. Allow targets to specify
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name of the generated asmwriter class, and the name of the format string.
llvm-svn: 15747
2004-08-14 22:50:53 +00:00
3bc477a237
Start parsing more information from the Operand information
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llvm-svn: 15644
2004-08-11 02:22:39 +00:00
5572682faa
Parse the operand list of the instruction. We currently support register and immediate operands.
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llvm-svn: 15390
2004-08-01 07:42:39 +00:00
c860ecafe1
Add, and start using, the CodeGenInstruction class. This class represents
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an instance of the Instruction tablegen class.
llvm-svn: 15385
2004-08-01 05:04:00 +00:00
Evan Cheng