0a1a7b6b23
Revert "AMDGPU: Enable ConstrainCopy DAG mutation"
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This reverts commit r287146.
This breaks few conformance tests.
llvm-svn: 287233
2016-11-17 16:41:49 +00:00
3b36bb1d87
AMDGPU: Enable ConstrainCopy DAG mutation
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This fixes a probably unintended divergence from the default
scheduler behavior.
llvm-svn: 287146
2016-11-16 20:35:23 +00:00
5d8eb25e78
AMDGPU: Use unsigned compare for eq/ne
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For some reason there are both of these available, except
for scalar 64-bit compares which only has u64. I'm not sure
why there are both (I'm guessing it's for the one bit inputs we
don't use), but for consistency always using the
unsigned one.
llvm-svn: 282832
2016-09-30 01:50:20 +00:00
bbb47da8a1
AMDGPU: Support commuting with immediate in src0
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llvm-svn: 280970
2016-09-08 17:19:29 +00:00
0d23ebe888
AMDGPU/SI: Implement a custom MachineSchedStrategy
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Summary:
GCNSchedStrategy re-uses most of GenericScheduler, it's just uses
a different method to compute the excess and critical register
pressure limits.
It's not enabled by default, to enable it you need to pass -misched=gcn
to llc.
Shader DB stats:
32464 shaders in 17874 tests
Totals:
SGPRS: 1542846 -> 1643125 (6.50 %)
VGPRS: 1005595 -> 904653 (-10.04 %)
Spilled SGPRs: 29929 -> 27745 (-7.30 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 36688188 -> 37034900 (0.95 %) bytes
LDS: 1913 -> 1913 (0.00 %) blocks
Max Waves: 254101 -> 265125 (4.34 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 1338220 -> 1438499 (7.49 %)
VGPRS: 886221 -> 785279 (-11.39 %)
Spilled SGPRs: 29869 -> 27685 (-7.31 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size: 34315716 -> 34662428 (1.01 %) bytes
LDS: 1551 -> 1551 (0.00 %) blocks
Max Waves: 188127 -> 199151 (5.86 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23688
llvm-svn: 279995
2016-08-29 19:42:52 +00:00
cb6ba62d6f
AMDGPU/SI: Enable the post-ra scheduler
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Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
2016-04-30 00:23:06 +00:00
f924dd6f3c
AMDGPU/SI: use S_AND for i1 trunc
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llvm-svn: 251630
2015-10-29 15:05:03 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Konstantin Zhuravlyov