Commit Graph

6252 Commits

Author SHA1 Message Date
Bill Wendling 4787efa380 Revert "Reapply: Add an error message to the default SIGPIPE handler"
This patch is spamming compiles with unhelpful and confusing messages.
E.g. the Linux kernel uses "grep -q" in several places. It's meant to
quit with a return code of zero when the first match is found. This can
cause a SIGPIPE signal, but that's expected, and there's no way to turn
this error message off to avoid spurious error messages.

UNIX03 apparently doesn't require printing an error message on SIGPIPE,
but specifically when there's an error on the stdout stream in a normal
program flow, e.g. when SIGPIPE trap is disabled.

A separate patch is planned to address the specific case we care most
about (involving llvm-nm).

This reverts commit b89bcefa62.

Link: https://github.com/llvm/llvm-project/issues/59037
Link: https://github.com/ClangBuiltLinux/linux/issues/1651

Differential Revision: https://reviews.llvm.org/D138244
2022-11-18 11:17:25 -08:00
Tomas Matheson 70dbd7bb12 [ARM][AArch64] Use StringRef in TargetParser structs
The invalid case is now represented by an empty StringRef rather than
a nullptr.

Previously ARCH_FEATURE was build from SUB_ARCH by prepending "+".
This is now reverse, so that the "+arch-feature" is now visible in
the .def, which is a bit clearer. This meant converting one StringSwitch
into a loop.

Removed getters which are now mostly unnecessary.

Removed some old FIXMEs.

Differential Revision: https://reviews.llvm.org/D138026
2022-11-17 18:44:06 +00:00
Tomas Matheson 6cff86ff7e [ARM][AArch64] De-template TargetParser types
Differential Revision: https://reviews.llvm.org/D138019
2022-11-17 16:12:38 +00:00
Tomas Matheson f15de14060 [ARM][AArch64] Move common code into ARMTargetParserCommon
Differential Revision: https://reviews.llvm.org/D138017
2022-11-16 18:40:23 +00:00
Muhammad Omair Javaid 332c4af35d Revert "[NFC] Make format() more amenable to format attributes"
This reverts commit cf239c2f17.
It has broken tools/llvm-dwarfdump/X86/simplified-template-names.s on
following buildbot:
https://lab.llvm.org/buildbot/#/builders/178/builds/3148
2022-11-16 19:09:49 +04:00
Ties Stuij 983f63f7f0 [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.

For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/

People who contributed to this patch:
- Keith Walker
- Ties Stuij

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D138010
2022-11-16 10:20:14 +00:00
Serge Pavlov 1f67dc8b7c [Driver] Enable nested configuration files
Users may partition parameters specified by configuration file and put
different groups into separate files. These files are inserted into the
main file using constructs `@file`. Relative file names in it are
resolved relative to the including configuration file and this is not
convenient in some cases. A configuration file, which resides in system
directory, may need to include a file with user-defined parameters and
still provide default definitions if such file is absent.

To solve such problems, the option `--config=` is allowed inside
configuration files. Like `@file` it results in insertion of
command-line arguments but the algorithm of file search is different and
allows overriding system definitions with user ones.

Differential Revision: https://reviews.llvm.org/D136354
2022-11-16 13:32:27 +07:00
Reed 88eb3c62f2 Add FP8 E4M3 support to APFloat.
NVIDIA, ARM, and Intel recently introduced two new FP8 formats, as described in the paper: https://arxiv.org/abs/2209.05433. The first of the two FP8 dtypes, E5M2, was added in https://reviews.llvm.org/D133823. This change adds the second of the two: E4M3.

There is an RFC for adding the FP8 dtypes here: https://discourse.llvm.org/t/rfc-add-apfloat-and-mlir-type-support-for-fp8-e5m2/65279. I spoke with the RFC's author, Stella, and she gave me the go ahead to implement the E4M3 type. The name of the E4M3 type in APFloat is Float8E4M3FN, as discussed in the RFC. The "FN" means only Finite and NaN values are supported.

Unlike E5M2, E4M3 has different behavior from IEEE types in regards to Inf and NaN values. There are no Inf values, and NaN is represented when the exponent and mantissa bits are all 1s. To represent these differences in APFloat, I added an enum field, fltNonfiniteBehavior, to the fltSemantics struct. The possible enum values are IEEE754 and NanOnly. Only Float8E4M3FN has the NanOnly behavior.

After this change is submitted, I plan on adding the Float8E4M3FN type to MLIR, in the same way as E5M2 was added in https://reviews.llvm.org/D133823.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D137760
2022-11-15 20:26:42 +01:00
Tomas Matheson 1ebfe9b264 [TargetParser] Split AArch64TargetParser from ARMTargetParser
AArch64TargetParser reuses data structures and some data from ARMTargetParser,
which causes more problems than it solves. This change separates them.

Code which is common to ARM and AArch64 is moved to ARMTargetParserCommon
which both ARMTargetParser and AArch64TargetParser use.

Some of the information in AArch64TargetParser.def was unused or nonsensical
(CPU_ATTR, ARCH_ATTR, ARCH_FPU) because it reused data strutures from
ARMTargetParser where some of these make sense. These are removed.

Differential Revision: https://reviews.llvm.org/D137924
2022-11-15 08:59:54 +00:00
Jonas Devlieghere 17737437ed
[dsymutil] Fix assertion in the Reproducer/FileCollector when TMPDIR is empty
Fix a assertion in dsymutil coming from the Reproducer/FileCollector.
When TMPDIR is empty, the root becomes a relative path, triggering an
assertion when adding a relative path to the VFS mapping. This patch
fixes the issue by resolving the relative path and also moves the
assertion up to make it easier to diagnose these issues in the future.

rdar://102170986

Differential revision: https://reviews.llvm.org/D137959
2022-11-14 19:11:34 -08:00
Jonas Devlieghere fd824bdc5e
Revert "[dsymutil] Fix assertion in the Reproducer/FileCollector when TMPDIR is empty"
This reverts commit 68efb4772c because the
test fails on some of the buildbots.
2022-11-14 13:03:47 -08:00
Jonas Devlieghere 68efb4772c
[dsymutil] Fix assertion in the Reproducer/FileCollector when TMPDIR is empty
Fix a assertion in dsymutil coming from the Reproducer/FileCollector.
When TMPDIR is empty, the root becomes a relative path, triggering an
assertion when adding a relative path to the VFS mapping. This patch
fixes the issue by resolving the relative path and also moves the
assertion up to make it easier to diagnose these issues in the future.

rdar://102170986

Differential revision: https://reviews.llvm.org/D137959
2022-11-14 12:34:16 -08:00
Yabin Cui 22339e52da [Support] Use thread safe version of getpwuid and getpwnam.
OpenGroup specification doesn't require getpwuid and getpwnam
to be thread-safe. And musl libc has a not thread-safe implementation.
When building clang with musl, this can make clang-scan-deps crash.

Reviewed By: pirama

Differential Revision: https://reviews.llvm.org/D137864
2022-11-14 17:48:44 +00:00
Philip Reames 780c539844 [RISCV] Implement assembler support for XVentanaCondOps
This change provides an implementation of the XVentanaCondOps vendor extension. This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

In addition to the technical contribution, this change is intended to be a test case for our vendor extension policy.

Once this lands, I plan to use this extension to prototype selection lowering to conditional moves. There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.

Differential Revision: https://reviews.llvm.org/D137350
2022-11-14 09:01:54 -08:00
Ying Yi ca875cb4fe [ThinLTO] a ThinLTO warning is added if cache_size_bytes or cache_size_files is too small for the current link job. The warning recommends the user to consider adjusting --thinlto-cache-policy.
A specific case for ThinLTO cache pruning is that the current build is huge, and the cache wasn't big enough to hold the intermediate object files of that build. So in doing that build, a file would be cached, and later in that same build it would be evicted. This was significantly decreasing the effectiveness of the cache. By giving this warning, the user could identify the required cache size/files and improve ThinLTO link speed.

Differential Revision: https://reviews.llvm.org/D135590
2022-11-14 12:27:29 +00:00
River Riddle 46fab76788 [MemoryBuffer] Allow optionally specifying desired buffer alignment
Underlying data may have requirements/expectations/etc. about
the run-time alignment. WritableMemoryBuffer currently uses
a 16 byte alignment, which works for many situations but not all.
Allowing a desired alignment makes it easier to reuse WritableMemoryBuffer
in situations of special alignment, and also removes a problem when
opening files with special alignment constraints. Large files generally
get mmaped, which has ~page alignment, but small files go through
WritableMemoryBuffer which has the much smaller alignment guarantee.

Differential Revision: https://reviews.llvm.org/D137820
2022-11-12 14:38:45 -08:00
Weining Lu 6890b9b71e Add missing changes for "[Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options"
Some changes in D136146 were lost by an accidentally sumbit. So recover
them.
2022-11-11 09:06:53 +08:00
Simon Pilgrim 261b3f71c0 [X86] Add missing Zen3 model subtypes
This patch adds support for detecting all current Zen/Zen3+ submodels

Based off a mixture of https://github.com/torvalds/linux/blob/master/drivers/hwmon/k10temp.c#L436 and InstLatx64 https://github.com/InstLatx64/InstLatx64/tree/master/AuthenticAMD CPUID dumps and confirmed by @GGanesh

Differential Revision: https://reviews.llvm.org/D137695
2022-11-10 10:36:09 +00:00
Weining Lu 135a9272a4 [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options
This patch adds options -march, -msingle-float, -mdouble-float,
-msoft-float and -mfpu for LoongArch.

Clang options `msingle_float` and `mdouble_float` are moved from
`m_mips_Features_Group` to `m_Group` because now more than targets use
them.

Reference:
https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-toolchain-conventions-EN.adoc

TODO: add -mtune.

Differential Revision: https://reviews.llvm.org/D136146
2022-11-10 17:27:28 +08:00
WANG Xuerui d480271729 [ADT][Triple] Add environment kinds for LoongArch GNU multiarch tuples
The canonical multiarch tuples for LoongArch are defined in [the
LoongArch toolchain conventions][1] document. As the musl port is still
WIP, only the GNU triples are added for now.

The spec mentions `loongarch64-linux-gnuf64`, which is functionally the
same as the existing `loongarch64-linux-gnu` triple, only with the
floating-point ABI part explicitly spelled out. Both forms are
supported, but normalization of one into another is not implemented in
this patch, to give the ecosystem some time to experiment and discuss.

[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-toolchain-conventions-EN.html

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D135751
2022-11-10 15:05:04 +08:00
Tomas Matheson 103bbddde6 [ARM] Move Triple::getARMCPUForArch into ARMTargetParser
This is very backend specific so either belongs in Toolchains/ARM or in
ARMTargetParser. Since it is used in lldb, ARMTargetParser made more sense.

This is part of an effort to move information about ARM/AArch64 architecture
versions, extensions and CPUs into their respective TargetParsers.

Differential Revision: https://reviews.llvm.org/D137564
2022-11-09 11:52:35 +00:00
Victor Campos 9d1ff787e5 [AArch64] Add support for the Cortex-X3 CPU
Cortex-X3 is an Armv9-A AArch64 CPU.

This patch introduces support for Cortex-X3.

Technical Reference Manual: https://developer.arm.com/documentation/101593/latest

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D136589
2022-11-09 11:33:48 +00:00
Freddy Ye 84a18a260e [X86] Support -march=sierraforest, grandridge, graniterapids.
Reviewed By: skan, pengfei, MaskRay

Differential Revision: https://reviews.llvm.org/D137153
2022-11-09 16:56:03 +08:00
Nathan James 6aa050a690 Reland "[llvm][NFC] Use c++17 style variable type traits"
This reverts commit 632a389f96.

This relands commit
1834a310d0.

Differential Revision: https://reviews.llvm.org/D137493
2022-11-08 14:15:15 +00:00
Nathan James 632a389f96 Revert "[llvm][NFC] Use c++17 style variable type traits"
This reverts commit 1834a310d0.
2022-11-08 13:11:41 +00:00
Nathan James 1834a310d0
[llvm][NFC] Use c++17 style variable type traits
This was done as a test for D137302 and it makes sense to push these changes

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D137493
2022-11-08 12:22:52 +00:00
Fangrui Song 6c927f2a86 Canonicalize PowerPC detection macros to __powerpc__ 2022-11-06 17:29:45 -08:00
Freddy Ye a806fc2767 [X86] Support -march=raptorlake, meteorlake
Reviewed By: pengfei, skan, MaskRay

Differential Revision: https://reviews.llvm.org/D135937
2022-11-04 09:32:17 +08:00
Sam James fa981b5413 Set LLVM_ATOMIC_LIB variable for convenient linking against libatomic
* Set LLVM_ATOMIC_LIB to keep track of when we need to link against libatomic.
* Add detection of mold linker which is required for this.
* Use --as-needed when linking against libatomic as a bonus. On some platforms,
  libatomic may be required only sometimes.

Bug: https://bugs.gentoo.org/832675
Thanks-to: Arfrever Frehtes Taifersar Arahesis <Arfrever@Apache.Org>
Tested-by: erhard_f@mailbox.org <erhard_f@mailbox.org>

Differential Revision: https://reviews.llvm.org/D136280
2022-11-03 21:07:43 +01:00
Simi Pallipurath fa8aeab606 [AArch64] Add support for the Cortex-A715 CPU
Cortex-A715 is an Armv9-A AArch64 CPU.

This patch introduces support for Cortex-A715.

Technical Reference Manual: https://developer.arm.com/documentation/101590/latest.

Reviewed By: vhscampos

Differential Revision: https://reviews.llvm.org/D136957
2022-11-03 09:28:46 +00:00
Serge Pavlov fdab9f1203 [Clang] Check for response file existence prior to check for recursion
As now errors in file operation are handled, check for file existence
must be done prior to check for recursion, otherwise reported errors are
misleading.

Differential Revision: https://reviews.llvm.org/D136090
2022-11-03 14:49:58 +07:00
Félix Cloutier cf239c2f17 [NFC] Make format() more amenable to format attributes
This change modifies the implementation of the format() function
so that vendor forks committed to building with compilers that
support __attribute__((format)) on non-variadic functions can
check the format() function with it.

rdar://84571523
2022-11-02 13:56:51 -07:00
Freddy Ye aee2a35ac4 [X86] Add AVX-NE-CONVERT instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D135930
2022-10-31 23:39:38 +08:00
Serge Pavlov fd3d7a9f8c Handle errors in expansion of response files
Previously an error raised during an expansion of response files (including
configuration files) was ignored and only the fact of its presence was
reported to the user with generic error messages. This made it difficult to
analyze problems. For example, if a configuration file tried to read an
inexistent file, the error message said that 'configuration file cannot
be found', which is wrong and misleading.

This change enhances handling errors in the expansion so that users
could get more informative error messages.

Differential Revision: https://reviews.llvm.org/D136090
2022-10-31 15:36:41 +07:00
Nicolai Hähnle 0629cce293 ManagedStatic: remove from DebugCounter
[Re-submit after earlier revert due to a test failure. Commit dce78646f0
("clang-tblgen build: avoid duplicate inclusion of libLLVMSupport")
is believe to address the root cause of the test failure.]

Follow the pattern used in MLIR for the cl::opt instances.

v2:
- make DebugCounter::isCountingEnabled public so that the
  DebugCounterOwner doesn't have to be a nested class. This simplifies
  later changes

v3:
- remove the indirection via DebugCounterOwner::instance()

Differential Revision: https://reviews.llvm.org/D129116
2022-10-30 20:47:12 +01:00
Serge Pavlov c1728a40aa Revert "Handle errors in expansion of response files"
This reverts commit 17eb198de9.
Reverted for investigation, because ClangDriverTests failed on some builders.
2022-10-30 02:03:12 +07:00
Serge Pavlov 17eb198de9 Handle errors in expansion of response files
Previously an error raised during an expansion of response files (including
configuration files) was ignored and only the fact of its presence was
reported to the user with generic error messages. This made it difficult to
analyze problems. For example, if a configuration file tried to read an
inexistent file, the error message said that 'configuration file cannot
be found', which is wrong and misleading.

This change enhances handling errors in the expansion so that users
could get more informative error messages.

Differential Revision: https://reviews.llvm.org/D136090
2022-10-29 22:01:47 +07:00
Freddy Ye 23f02693ec [X86] Add AVX-VNNI-INT8 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135938
2022-10-28 10:39:54 +08:00
Freddy Ye 0e720e6ada [X86] Add AVX-IFMA instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135932
2022-10-28 09:42:30 +08:00
Kito Cheng ae116f43ff [RISCV] Drop single letter b extension support
It splited into several zb* extensions, and `b` is dropped after
0.93, so it time to retired that as other non-ratified zb* extensions.

Currntly clang can accept that with warning:

$ clang -target riscv64-elf ~/hello.c -S  -march=rv64gcb
'+b' is not a recognized feature for this target (ignoring feature)
'+b' is not a recognized feature for this target (ignoring feature)
'+b' is not a recognized feature for this target (ignoring feature)

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D136812
2022-10-27 23:53:32 +08:00
Phoebe Wang b51b90d6e2 [X86][1/2] SUPPORT RAO-INT
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Initial authored by Liu Chen (@LiuChen3)

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D135951
2022-10-27 17:20:07 +08:00
Tatsuyuki Ishi 826f385348 [Support] Use find() for faster StringRef::count (NFC)
While profiling InclusionRewriter, it was found that counting lines was
so slow that it took up 20% of the processing time. Surely, calling
memcmp() of size 1 on every substring in the window isn't a good idea.

Use StringRef::find() instead; in the case of N=1 it will forward to
memcmp which is much more optimal. For 2<=N<256 it will run the same
memcmp loop as we have now, which is still suboptimal but at least does
not regress anything.

Differential Revision: https://reviews.llvm.org/D133658
2022-10-27 10:22:25 +02:00
Félix Cloutier bca75abc01 Revert "[NFC] Make format() more amenable to format attributes"
This reverts commit fb1e90ef07.
2022-10-26 12:53:14 -07:00
Félix Cloutier fb1e90ef07 [NFC] Make format() more amenable to format attributes
This change modifies the implementation of the format() function
so that vendor forks committed to building with compilers that
support __attribute__((format)) on non-variadic functions can
check the format() function with it.

Reviewed By: ahatanak
Differential Revision: https://reviews.llvm.org/D132413
rdar://84571523
2022-10-26 12:10:42 -07:00
Piyou Chen 7d7940fd77 [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction

Note: the svinval instructions defined in https://reviews.llvm.org/D117654

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136571
2022-10-26 09:45:30 -07:00
Sjoerd Meijer 9bd273047d [Clang][AArch64] Add TargetParser support for defining CPU aliases
This adds AArch64 TargetParser support to define CPU aliases, and
ports the definition of Grace over to that. This is following up
on D136425.

Differential Revision: https://reviews.llvm.org/D136611
2022-10-25 15:08:15 +05:30
David Green 9c48b7f0e7 [AArch64][ARM] Alter v8.1a neon intrinsics to be target-based, not preprocessor based
As a continuation of D132034, this switches the QRDMX v8.1a neon
intrinsics over from preprocessor defines to be target-gated. As there
is no "rdma" or "qrdmx" target feature, they use the "v8.1a"
architecture feature directly.

This works well for AArch64, but something needs to be done for Arm at
the same time, as they both use the same header and tablegen emitter.
This patch opts for adding "v8.1a" and all dependant target features to
the Arm TargetParser, similar to what was recently done for AArch64 but
through initFeatureMap when the Architecture is parsed. I attempted to
make the code similar to the AArch64 backend.

Otherwise this is similar to the changes made in D132034.

Differential Revision: https://reviews.llvm.org/D135615
2022-10-25 09:02:52 +01:00
Freddy Ye fdac4c4e92 [X86] Add CMPCCXADD instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewed By: pengfei, skan

Differential Revision: https://reviews.llvm.org/D135933
2022-10-25 14:33:39 +08:00
Piyou Chen f8b8426861 [RISCV] Add Svnapot extension
Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D136570
2022-10-24 01:27:04 -07:00
Simon Pilgrim e35d50b7f2 [ADT] APInt.cpp - remove <cstring> duplicate. NFC.
This is already included in APInt.h
2022-10-23 12:44:20 +01:00