Commit Graph

270 Commits

Author SHA1 Message Date
Chris Lattner ac5881295c Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes fd5458d4bd More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field

llvm-svn: 105859
2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.

llvm-svn: 105652
2010-06-08 22:51:23 +00:00
Chris Lattner fdd2614330 revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes 594fa26317 Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.

llvm-svn: 105521
2010-06-05 03:53:24 +00:00
Daniel Dunbar 5661c0c755 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

llvm-svn: 104270
2010-05-20 20:20:32 +00:00
Sean Callanan e7e1cf9fbd Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
2010-05-06 20:59:00 +00:00
Sean Callanan 1efe661b46 Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

llvm-svn: 100694
2010-04-07 21:42:19 +00:00
Evan Cheng 44be5362d6 Check in tablegen changes to fix disassembler related failures caused by r98465.
llvm-svn: 98468
2010-03-14 05:15:39 +00:00
Sean Callanan 69c0226ba8 Changed the table generator so that the X86
disassembler never recognizes InitReg instructions.

llvm-svn: 97017
2010-02-24 02:56:25 +00:00
Sean Callanan 4d804d794f Added the rdtscp instruction to the x86 instruction
tables.

llvm-svn: 96073
2010-02-13 02:06:11 +00:00
Sean Callanan 44232af55a Fixed encodings for invlpg, invept, and invvpid.
llvm-svn: 96065
2010-02-13 01:48:34 +00:00
Chris Lattner 140caa7240 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
fix swapgs to be spelled right.

llvm-svn: 96058
2010-02-13 00:41:14 +00:00
Chris Lattner 064e926362 Remove special cases for [LM]FENCE, MONITOR and MWAIT from
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
2010-02-12 23:54:57 +00:00
Sean Callanan dde9c12307 Reworked the Intel disassembler to support instructions
whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043
2010-02-12 23:39:46 +00:00
Chris Lattner f7477e599f add a bunch of mod/rm encoding types for fixed mod/rm bytes.
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960
2010-02-12 02:06:33 +00:00
Chris Lattner a9dfb1bc07 Introduce a new CodeGenInstruction::ConstraintInfo class
for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file.  Fix X86RecognizableInstr to use this instead of
parsing C code :).

llvm-svn: 95753
2010-02-10 01:45:28 +00:00
Sean Callanan 36eab80875 Fixes to the X86 disassembler:
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.

llvm-svn: 91919
2009-12-22 21:12:55 +00:00
Daniel Dunbar f008ea5fa0 Add missing newlines at EOF (for clang++).
llvm-svn: 91756
2009-12-19 04:16:48 +00:00
Sean Callanan 04cc307edd Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
incarnations), integrated into the MC framework.  

The disassembler is table-driven, using a custom TableGen backend to 
generate hierarchical tables optimized for fast decode.  The disassembler 
consumes MemoryObjects and produces arrays of MCInsts, adhering to the 
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).

The disassembler is documented in detail in

- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)

You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets.  Please let me know if you encounter any problems
with it.

llvm-svn: 91749
2009-12-19 02:59:52 +00:00