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70083 Commits

Author SHA1 Message Date
zhoujing 47fc50bb92 Add pass to support VX/VF instruction generation 
Summary: Add pass to support VX/VF instruction generation

Test Plan: none

Reviewers: hualin

Reviewed By: hualin

Subscribers: yanming

Differential Revision: http://www.tpt.com/D583
 2023-02-07 14:00:15 +08:00
zhoujing e74aafb0d6 Change vftta&vfexp instructions' encoding formats 2023-01-28 10:46:31 +08:00
Aries 9318d5354f [NFC] Fix coding style 2023-01-28 09:53:19 +08:00
Aries 192ee0187a [NFC] Fix coding style 2023-01-28 09:49:39 +08:00
zhoujing 93143b5b35 Add definition for vfexp/vftta 2023-01-20 09:57:19 +08:00
Aries 438f1c92c4 Fix some build warnings 2023-01-19 09:45:27 +08:00
Aries 890dddc205 Add missing C ext feature to Ventus GPGPU 2023-01-18 15:09:38 +08:00
Aries 71979c7b0d [NFC] Add comment to FLW/FSW 2023-01-18 15:09:18 +08:00
zhoujing eecbe33eb1 Fix instruction encoding conflicts 2023-01-18 11:20:14 +08:00
zhoujing 229b27b714 Update instructions for vector load/store 2023-01-17 17:46:59 +08:00
Aries 2c6aaa910c Add endprg, vid.v instruction definition 2023-01-17 14:39:57 +08:00
zhoujing 23821f9116 Change some patterns' format 2023-01-17 09:34:59 +08:00
Aries 2d601dc47f Fix bug for Ventus TTI getRegisterBitWidth 2023-01-16 16:06:53 +08:00
Aries f933867e85 Fix linking error with pocl when llvm is built as shared libraries 2023-01-16 16:03:17 +08:00
zhoujing a81a56274f Update float point instructions test case 2023-01-12 16:43:47 +08:00
zhoujing fcd285daae Modify file formats && add predicate for float point instruction 
* Based on zcc commit: 6e63555df68b5ce96d0af3dceb822abb2a2c9481
 2023-01-10 10:25:58 +08:00
zhoujing 7e701d4ba1 Add support for float point trunc instruction match 2023-01-09 18:06:39 +08:00
zhoujing 899ca9fd8e Add support for 12 bits immediate 2023-01-09 11:59:45 +08:00
zhoujing cfc9476c48 Update pattern and test cases for floating-point sign-injection Instruction 2023-01-05 17:44:06 +08:00
zhoujing 02392af08a Update pattern and test cases for float/integer arithmetic instructions 2023-01-05 13:35:58 +08:00
zhoujing c635182266 Update pattern and test cases for float/integer convert instructions 2023-01-04 15:04:36 +08:00
Aries a173844ae5 Grow Ventus GPGPU stack upwards instead of downwards 2023-01-04 10:29:53 +08:00
zhoujing eb54dc382c Update pattern for float select instructions && update test cases 2023-01-04 10:21:49 +08:00
Aries f9dd113822 Turn on ABI register naming 2023-01-03 11:36:49 +08:00
Aries 78434601d8 Generate vlw/vsw instructions for private memory access 2023-01-03 11:08:24 +08:00
Aries 0b43b70327 Fix bug in addressing space mapping 2023-01-03 10:45:58 +08:00
zhoujing dcf8ab214e Typo fixes 2022-12-30 17:25:15 +08:00
zhoujing 8f6c31ea7d Add pattern for integer select instructions 2022-12-30 16:22:59 +08:00
zhoujing 1fab7b80f3 Legalize operation for SETCC 2022-12-29 17:13:49 +08:00
Aries d6ca871320 Add 'regext' instruction definition and insertion pass. 
As the VentusRegExtInsertion pass will break the def-use chain, so it should
only run without -verify-machineinstrs and should only be run at the very end
of codegen pass.
 2022-12-29 16:53:18 +08:00
zhoujing 734f087a82 Update test cases and fix the bug of wrong move from GPR to VGPR 2022-12-29 13:46:34 +08:00
Aries 17adb707e6 Fix bug in kernel arg memory offset calculation 2022-12-29 11:53:29 +08:00
zhoujing 64b95e02f9 Add pattern for float point ternary operation and add test cases 
* fneg operation need to be added, need to define uniform pattern to simplify code
* VX instructions need to be added later
 2022-12-28 17:57:24 +08:00
Aries 9925e4e511 Define callee saved registers for Ventus GPGPU. 
Initially implemented 2 stacks support for sGPR spill/restore stack and per-thread stack,
but stack size calculation is computed as a sum of 2 stacks(this works but wastes lot of
spaces).
Now TP register is used as per-thread stack pointer, SP register is used for sGPR spill/restore.
Clean up RVV related stack frame code etc.
 2022-12-28 16:37:38 +08:00
Aries 424ea45e4f Update Ventus GPGPU ABI: X4 as stack pointer, V0-V31 as arguments registers etc 2022-12-28 13:11:22 +08:00
Aries 228be521e5 Add initial different stack frame support for sALU and vALU. 
FIXME: The stack pointer RISCV::X4 for vALU is not yet correctly used, but related infrastructure
should work(MFI.isEntryFunction() is used to check RISCV::X2 or RISCV::X4 to be used as stack pointer).
 2022-12-27 18:28:51 +08:00
Aries e8368c07e1 Fix kernel argument lowering alignment bug. 2022-12-27 17:00:46 +08:00
Aries 3a9c32a024 Add initial vector support(calling convention fix). 2022-12-27 16:35:12 +08:00
Aries da5006ca8d Add support to lowering BITCAST and Constant Pool for zfinx etc 2022-12-27 13:39:46 +08:00
Aries 9be2c54215 Add initial vGPR + sGPRF32 (zfinx) support 2022-12-27 12:00:30 +08:00
Aries 7d7ef235fd Support f32 return type in VGPR 2022-12-27 11:21:08 +08:00
Aries 7fb5ae0a92 Add very initial vALU floating point support. 2022-12-27 11:19:14 +08:00
Aries 4d387117be Add multi data type support for VGPR register class. 2022-12-27 11:01:26 +08:00
Aries c734a517f4 Fix bug in building VSUXEI32 MI for stack slot load/restore 2022-12-23 10:17:52 +08:00
Aries 67109cea5b Add LegancyDivergenceAnalysis pass as prerequisite to SelectionDAG pass. 2022-12-23 10:03:43 +08:00
Aries 1b3dcad1b5 Simple vALU branch now works. 2022-12-22 18:01:55 +08:00
Aries 2f946d86ad Fix basicblock insertion ordering for ISD::SELECT lowering. 2022-12-22 17:47:03 +08:00
Aries 73846a1613 Do not try to merge branches for vALU execution path, 
as explicit branch and join instructions are required for SIMT stack working correctly.
 2022-12-22 17:42:10 +08:00
Aries cb6f30fbd7 Add initial support to lower ISD::SELECT into branch instructions in divergent execution path. 2022-12-22 17:17:02 +08:00
Aries b9da010dd5 [NFC] Refactor messy switch...case 2022-12-22 14:50:13 +08:00