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6198 Commits

Author SHA1 Message Date
Dan Gohman c4ce336205 Make LowerSubregs' debug output for EXTRACT_SUBREG consistent with 
that of INSERT_SUBREG and SUBREG_TO_REG.

llvm-svn: 61218
 2008-12-18 22:11:34 +00:00
Dan Gohman d38c00c85b Fix a copy+pasto in an assertion message. 
llvm-svn: 61217
 2008-12-18 22:07:25 +00:00
Dan Gohman 451afdd9fe Fix indentation level. 
llvm-svn: 61216
 2008-12-18 22:06:01 +00:00
Dan Gohman 0ab1144c79 Print subreg information in MachineInstr::dump. 
llvm-svn: 61213
 2008-12-18 21:51:27 +00:00
Mon P Wang a501640ffa Added support for vector widening. 
llvm-svn: 61209
 2008-12-18 20:03:17 +00:00
Dan Gohman 83682a9441 Give MachineLICM a name, for -time-passes etc. 
llvm-svn: 61184
 2008-12-18 01:37:56 +00:00
Dan Gohman b0ef9140e5 Move post-RA scheduling before branch folding for now, because branch 
folding's tail merging doesn't currently preserve liveness information
which post-RA scheduling requires.

llvm-svn: 61183
 2008-12-18 01:36:42 +00:00
Owen Anderson ad4d2ab15b Re-apply r61158 in a form that no longer breaks tests. 
llvm-svn: 61182
 2008-12-18 01:27:19 +00:00
Owen Anderson 59727c0496 Revert r61158 for now, as it caused some test failures. 
llvm-svn: 61159
 2008-12-17 22:17:27 +00:00
Owen Anderson 9389176009 Fix miscompilations caused by renumbering, and enable it as part of prealloc splitting. 
llvm-svn: 61158
 2008-12-17 22:06:59 +00:00
Mon P Wang 015a7f57b2 Fix expansion of vsetcc to set the high bit for true instead of 1. 
llvm-svn: 61129
 2008-12-17 08:49:47 +00:00
Dan Gohman ce70fe2e25 Double the amount of memory reserved for SUnits. This is a 
temporary workaround for an obscure bug. When node cloning is
used, it is possible that more SUnits will be created, and
if the SUnits std::vector has to reallocate, it will
invalidate all the graph edges.

llvm-svn: 61122
 2008-12-17 04:30:46 +00:00
Dan Gohman 2a16bbe394 Use getDepth() and getHeight() instead of accessing the 
Depth and Height members directly, as they may not be
current.

llvm-svn: 61121
 2008-12-17 04:25:52 +00:00
Eli Friedman 6cf404f2d1 Fix for PR3225: disable a broken optimization in 
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

In terms of restoring the optimization, the best fix here isn't 
obvious... any ideas?

llvm-svn: 61119
 2008-12-17 03:35:17 +00:00
Dale Johannesen f51dcef803 A new dag combine; several permutations of this 
are there under ADD, this one was missing.

llvm-svn: 61107
 2008-12-16 22:13:49 +00:00
Owen Anderson 5121ec3821 Add code to renumber split intervals into new vregs. This is disabled for now until I finish working out some iterator invalidation issues. 
llvm-svn: 61104
 2008-12-16 21:35:08 +00:00
Dan Gohman b4d41e802f Eliminate the loop that walks the critical path. Instead, just track the 
position in the critical path during the main instruction walk.  This
eliminates the need for the CritialAntiDep DenseMap.

llvm-svn: 61096
 2008-12-16 19:27:52 +00:00
Dan Gohman 4476ef810b Preserve SourceValue information when lowering produces multiple loads from 
different offsets within the same stack slot.

llvm-svn: 61093
 2008-12-16 18:25:36 +00:00
Evan Cheng c35fc49477 We have decided not to support inline asm where an output operand with a matching input operand with incompatible type (i.e. either one is a floating point and the other is an integer or the sizes of the types differ). SelectionDAGBuild will catch these and exit with an error. 
llvm-svn: 61092
 2008-12-16 18:21:39 +00:00
Dan Gohman 51559185f1 Enable anti-dependence breaking by default when post-RA scheduling is enabled. 
llvm-svn: 61078
 2008-12-16 06:21:45 +00:00
Dan Gohman 4302b4a63c When breaking an anti-dependency, don't use a register which has seen 
one of its aliases defined. This is conservative, but tricky subreg
corner cases are outside the primary aim of this pass.

llvm-svn: 61077
 2008-12-16 06:20:58 +00:00
Dan Gohman b9a012156b Add initial support for back-scheduling address computations, 
especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075
 2008-12-16 03:35:01 +00:00
Dan Gohman 405f2197a4 Remove some special-case logic in ScheduleDAGSDNodes's 
latency computation code that is no longer needed with the
new method for handling latencies.

llvm-svn: 61074
 2008-12-16 03:31:11 +00:00
Dan Gohman dddc1ac7ea Fix some register-alias-related bugs in the post-RA scheduler liveness 
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.

Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.

Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.

llvm-svn: 61073
 2008-12-16 03:25:46 +00:00
Dan Gohman 8f782bbb28 Add a simple target-independent heuristic to allow targets with no 
instruction itinerary data to back-schedule loads.

llvm-svn: 61070
 2008-12-16 02:38:22 +00:00
Dan Gohman e3a6351f34 Move addPred and removePred out-of-line. 
llvm-svn: 61067
 2008-12-16 01:05:52 +00:00
Dan Gohman 17214e633d Make addPred and removePred return void, since the return value is not 
currently used by anything.

llvm-svn: 61066
 2008-12-16 01:00:55 +00:00
Dan Gohman cb6accfea9 This getEdgeAttributes doesn't need a template argument. 
llvm-svn: 61065
 2008-12-16 00:55:00 +00:00
Mon P Wang 580f2c7b61 Added support for splitting and scalarizing vector shifts. 
llvm-svn: 61050
 2008-12-15 21:44:00 +00:00
Dan Gohman a7e139a3e6 Fix printing of PseudoSourceValues in SDNode graphs. 
llvm-svn: 61036
 2008-12-15 17:28:10 +00:00
Mon P Wang ac4e120912 Added support to LegalizeType for expanding the operands of scalar to vector 
and insert vector element.  Modified extract vector element to extend the
result to match the expected promoted type.

llvm-svn: 61029
 2008-12-15 06:57:02 +00:00
Duncan Sands f312dc7729 Reapply r60997, this time without forgetting that 
target constants are allowed to have an illegal
type.

llvm-svn: 61006
 2008-12-14 09:43:15 +00:00
Bill Wendling e5af6f1990 Temporarily revert r60997. It was causing this failure: 
Running /Users/void/llvm/llvm.src/test/CodeGen/Generic/dg.exp ...
FAIL: /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll
Failed with exit(1) at line 1
while running:  llvm-as < /Users/void/llvm/llvm.src/test/CodeGen/Generic/asm-large-immediate.ll |  llc | /usr/bin/grep 68719476738
Assertion failed: ((TypesNeedLegalizing || getTypeAction(VT) == Legal) && "Illegal type introduced after type legalization?"), function HandleOp, file /Users/void/llvm/llvm.src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 493.
0   llc               0x0085392e char const* std::find<char const*, char>(char const*, char const*, char const&) + 98
1   llc               0x00853e63 llvm::sys::PrintStackTraceOnErrorSignal() + 593
2   libSystem.B.dylib 0x96cac09b _sigtramp + 43
3   libSystem.B.dylib 0xffffffff _sigtramp + 1765097359
4   libSystem.B.dylib 0x96d24ec2 raise + 26
5   libSystem.B.dylib 0x96d3447f abort + 73
6   libSystem.B.dylib 0x96d26063 __assert_rtn + 101
7   llc               0x004f9018 llvm::cast_retty<llvm::SubprogramDesc, llvm::DebugInfoDesc*>::ret_type llvm::cast<llvm::Sub
...

llvm-svn: 61001
 2008-12-13 23:53:00 +00:00
Duncan Sands 24092271cc LegalizeDAG is not supposed to introduce illegal 
types into the DAG if they were not already there.
Check this with an assertion.

llvm-svn: 60997
 2008-12-13 22:33:38 +00:00
Mon P Wang 472cd640fa Remove assertion to allow promotion of a truncating store operand 
llvm-svn: 60975
 2008-12-13 08:16:43 +00:00
Mon P Wang f95bd2078d Added basic support for expanding VSETCC 
llvm-svn: 60974
 2008-12-13 08:15:14 +00:00
Duncan Sands b6f09933c0 On big-endian machines it is wrong to do a full 
width register load followed by a truncating
store for the copy, since the load will not place
the value in the lower bits.  Probably partial
loads/stores can never happen here, but fix it
anyway.

llvm-svn: 60972
 2008-12-13 07:18:38 +00:00
Devang Patel 42828e8168 Do not print empty DW_AT_comp_dir. 
llvm-svn: 60965
 2008-12-12 21:57:54 +00:00
Duncan Sands 8f352fe100 When expanding unaligned loads and stores do not make 
use of illegal integer types: instead, use a stack slot
and copying via integer registers.  The existing code
is still used if the bitconvert is to a legal integer
type.

This fires on the PPC testcases 2007-09-08-unaligned.ll
and vec_misaligned.ll.  It looks like equivalent code
is generated with these changes, just permuted, but
it's hard to tell.

With these changes, nothing in LegalizeDAG produces
illegal integer types anymore.  This is a prerequisite
for removing the LegalizeDAG type legalization code.

While there I noticed that the existing code doesn't
handle trunc store of f64 to f32: it turns this into
an i64 store, which represents a 4 byte stack smash.
I added a FIXME about this.  Hopefully someone more
motivated than I am will take care of it.

llvm-svn: 60964
 2008-12-12 21:47:02 +00:00
Evan Cheng 3270a1dec3 Fix add/sub expansion: don't create ADD / SUB with two results (seems like everyone is doing this these days :-). Patch by Daniel M Gessel! 
llvm-svn: 60958
 2008-12-12 18:49:09 +00:00
Duncan Sands e4bcb8e2dd When using a 4 byte jump table on a 64 bit machine, 
do an extending load of the 4 bytes rather than a
potentially illegal (type) i32 load followed by a
sign extend.

llvm-svn: 60945
 2008-12-12 08:13:38 +00:00
Mon P Wang 9c2d26d208 Added support for SELECT v8i8 v4i16 for X86 (MMX) 
Added support for TRUNC v8i16 to v8i8 for X86 (MMX)

llvm-svn: 60916
 2008-12-12 01:25:51 +00:00
Bill Wendling 1a317678bc Redo the arithmetic with overflow architecture. I was changing the semantics of 
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.

llvm-svn: 60915
 2008-12-12 00:56:36 +00:00
Mon P Wang bcdbfa854a Avoid generating a convert_rndsat node when the src and dest type are the same. 
llvm-svn: 60869
 2008-12-11 03:30:13 +00:00
Bill Wendling 40d2476adc Clarify FIXME. 
llvm-svn: 60867
 2008-12-11 01:26:44 +00:00
Mon P Wang c68b3c4fc1 Whitespace clean up (tabs with spaces) 
llvm-svn: 60866
 2008-12-11 00:44:22 +00:00
Mon P Wang b5eb7205ea Make fix for r60829 less conservative to allow the proper optimization for 
vec_extract-sse4.ll.

llvm-svn: 60865
 2008-12-11 00:26:16 +00:00
Bill Wendling d8681df4e7 Add a newline after this debug output. 
llvm-svn: 60861
 2008-12-10 23:24:43 +00:00
Bill Wendling 0864a75ebf If ADD, SUB, or MUL have an overflow bit that's used, don't do transformation on 
them. The DAG combiner expects that nodes that are transformed have one value
result.

llvm-svn: 60857
 2008-12-10 22:36:00 +00:00
Duncan Sands 09ed3bba2b For amusement, implement SADDO, SSUBO, UADDO, USUBO 
for promoted integer types, eg: i16 on ppc-32, or
i24 on any platform.  Complete support for arbitrary
precision integers would require handling expanded
integer types, eg: i128, but I couldn't be bothered.

llvm-svn: 60834
 2008-12-10 12:30:42 +00:00