llvm-project

Commit Graph

Author	SHA1	Message	Date
Stanislav Mekhanoshin	3bffb1cd0e	[AMDGPU] Use single cache policy operand Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469	2021-03-15 13:00:59 -07:00
dfukalov	b3cdaef518	[MIR] Fix out of bounds access in MIRPrinter. Fixes: SWDEV-256460 Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D90239	2020-10-29 14:35:06 +03:00

Author

SHA1

Message

Date

Stanislav Mekhanoshin

3bffb1cd0e

[AMDGPU] Use single cache policy operand

Replace individual operands GLC, SLC, and DLC with a single cache_policy
bitmask operand. This will reduce the number of operands in MIR and I hope
the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Differential Revision: https://reviews.llvm.org/D96469

2021-03-15 13:00:59 -07:00

dfukalov

b3cdaef518

[MIR] Fix out of bounds access in MIRPrinter.

Fixes: SWDEV-256460

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D90239

2020-10-29 14:35:06 +03:00

2 Commits