80c345927e
delete a forwarding function.
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llvm-svn: 100815
2010-04-08 21:34:17 +00:00
433d40695b
remove the TargetLoweringObjectFileMachO::getMachoSection
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api and update clients to use MCContext instead.
llvm-svn: 100808
2010-04-08 20:40:11 +00:00
03549ee5af
Added support for ARM disassembly to edis.
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I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
llvm-svn: 100735
2010-04-08 00:48:21 +00:00
4b1b4205ed
Update CMake build.
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llvm-svn: 100714
2010-04-07 23:05:23 +00:00
2104b8d36e
rename llvm::llvm_report_error -> llvm::report_fatal_error
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llvm-svn: 100709
2010-04-07 22:58:41 +00:00
85ce9f4f30
Missed this one line for the previous checkin to fix build warnings.
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llvm-svn: 100697
2010-04-07 22:21:03 +00:00
8b04b550df
Fixed warnings pointed out by clang.
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llvm-svn: 100696
2010-04-07 22:03:27 +00:00
80f8c3d533
Fixed warnings pointed out by clang.
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Next to work on is ARMDisassemblerCore.cpp.
llvm-svn: 100695
2010-04-07 21:52:48 +00:00
3f253e2cb1
Fixed 3 warnings pointed out by clang.
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llvm-svn: 100693
2010-04-07 21:23:48 +00:00
4e2f8722c4
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
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ARMDecoderEmitter.cpp, with FIXME comment.
llvm-svn: 100690
2010-04-07 20:53:12 +00:00
643a55708f
Added an AsmLexer for the ARM target, which uses
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a simple mapping of register names to IDs to
identify register tokens.
llvm-svn: 100685
2010-04-07 20:29:34 +00:00
60b289709e
Educate GetInstrSizeInBytes implementations that
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DBG_VALUE does not generate code.
llvm-svn: 100681
2010-04-07 19:51:44 +00:00
6e01726eae
Remove late ARM codegen optimization pass committed by accident.
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It is not ready for public yet.
llvm-svn: 100673
2010-04-07 18:23:27 +00:00
090323aee5
Split A8/A9 itins - they already were too big.
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llvm-svn: 100672
2010-04-07 18:22:11 +00:00
32457d6c5e
Add some crude itin approximation for VFP load / stores on A9
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llvm-svn: 100671
2010-04-07 18:22:03 +00:00
d351104f19
Add some crude approximation for neon load/store instructions
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llvm-svn: 100670
2010-04-07 18:21:58 +00:00
4acfad7c1b
Add some A8-based approximation for instructions with unknown cycle times
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llvm-svn: 100669
2010-04-07 18:21:52 +00:00
4fb6a66c8f
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
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llvm-svn: 100668
2010-04-07 18:21:46 +00:00
982f0ceaf8
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
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llvm-svn: 100667
2010-04-07 18:21:41 +00:00
4050d69dcf
Fix A8 FP NEON MAC itins
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llvm-svn: 100666
2010-04-07 18:21:33 +00:00
9ff2f8f7a5
A9 NEON FP itins
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llvm-svn: 100665
2010-04-07 18:21:27 +00:00
03b317a286
Some permute goodness for A9
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llvm-svn: 100664
2010-04-07 18:21:22 +00:00
7ab31047a7
More shift itins for A9
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llvm-svn: 100663
2010-04-07 18:21:16 +00:00
4d36f8890f
More fixes for itins
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llvm-svn: 100662
2010-04-07 18:21:10 +00:00
ceb54d5ab0
Fix invalid itins for 32-bit varians of VMLAL and friends
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llvm-svn: 100661
2010-04-07 18:21:04 +00:00
f64c7ca5c3
Add MAC stuff for A9
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llvm-svn: 100660
2010-04-07 18:20:58 +00:00
2ef0a12fa1
Fix invalid NEON MAC itins on A8
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llvm-svn: 100659
2010-04-07 18:20:53 +00:00
5e208dc21b
Fix itins for VPAL
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llvm-svn: 100658
2010-04-07 18:20:47 +00:00
a248becd6c
Fix itins for VABA
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llvm-svn: 100657
2010-04-07 18:20:42 +00:00
a3e4989ad8
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
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llvm-svn: 100656
2010-04-07 18:20:36 +00:00
140a65ce0b
More A9 itineraries
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llvm-svn: 100655
2010-04-07 18:20:29 +00:00
1a1af5a830
Correct itinerary class for VPADD
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llvm-svn: 100654
2010-04-07 18:20:24 +00:00
4650fd5fc6
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
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llvm-svn: 100653
2010-04-07 18:20:18 +00:00
7d4fad5942
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
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llvm-svn: 100652
2010-04-07 18:20:13 +00:00
2cba05bbe1
Some easy NEON scheduling goodness for A9
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llvm-svn: 100651
2010-04-07 18:20:07 +00:00
2063705d91
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
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llvm-svn: 100650
2010-04-07 18:20:02 +00:00
c1e7a6feac
FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9.
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llvm-svn: 100649
2010-04-07 18:19:56 +00:00
dad973334b
Proper cycle times for locks, since wbck latency can be larger than fwd latency.
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llvm-svn: 100648
2010-04-07 18:19:51 +00:00
4c1da0f82a
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
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llvm-svn: 100647
2010-04-07 18:19:46 +00:00
baeb210be7
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
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llvm-svn: 100646
2010-04-07 18:19:40 +00:00
15ccae2a46
Some bits of A9 scheduling: VFP
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llvm-svn: 100643
2010-04-07 18:19:18 +00:00
10fc6e9650
Separate const from non-const stuff during mergeing
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llvm-svn: 100642
2010-04-07 18:19:13 +00:00
0453de0133
Some initial version of global merger
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llvm-svn: 100641
2010-04-07 18:19:07 +00:00
5202269dc4
Expand SELECT and SELECT_CC for NEON vector types.
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Radar 7770501.
llvm-svn: 100568
2010-04-06 22:02:24 +00:00
6e39c4a097
don't use emitlabel in the arm asm printer yet, the order
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isn't well specified. ARM really needs to have its instprinter
finished at some point.
llvm-svn: 100439
2010-04-05 17:52:31 +00:00
6a0e89aefb
fix a couple problems I introduced handling symbols
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with spaces in them. Sym->getName() != OS << *Sym
llvm-svn: 100434
2010-04-05 16:32:14 +00:00
dacfd2c6d4
Get rid of traling whitespaces. No functionality change.
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llvm-svn: 100404
2010-04-05 04:51:50 +00:00
dba13e7922
The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
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uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
llvm-svn: 100403
2010-04-05 04:46:17 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
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When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
0b8adb0652
Temporarily remove to disable building of ARM disassembler.
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llvm-svn: 100380
2010-04-05 01:57:50 +00:00
Chris Lattner