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135 Commits

Author SHA1 Message Date
Michael Liao 73cffddb95 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
 2012-11-08 07:28:54 +00:00
Michael Liao f54249b55f Add register encoding support in X86 backend 
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
  retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.

llvm-svn: 165241
 2012-10-04 19:50:43 +00:00
Craig Topper 3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper a60c0f1163 Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 
llvm-svn: 163974
 2012-09-15 17:09:36 +00:00
Craig Topper f7755df776 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren. 
llvm-svn: 160110
 2012-07-12 06:52:41 +00:00
Manman Ren a09820414a X86: add GATHER intrinsics (AVX2) in LLVM 
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221
 2012-06-26 19:47:59 +00:00
Elena Demikhovsky 602f3a26d6 Added FMA3 Intel instructions. 
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.

llvm-svn: 157737
 2012-05-31 09:20:20 +00:00
Benjamin Kramer ef479ea854 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

llvm-svn: 157634
 2012-05-29 19:05:25 +00:00
Craig Topper 1964b6d39d Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended. 
llvm-svn: 157122
 2012-05-19 19:14:18 +00:00
Jim Grosbach c3b0427921 Allow MCCodeEmitter access to the target MCRegisterInfo. 
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
 2012-05-15 17:35:52 +00:00
Joerg Sonnenberger a29b5bd2a8 Put Is64BitMemOperand into !defined(NDEBUG) for now. 
llvm-svn: 153185
 2012-03-21 14:09:26 +00:00
Joerg Sonnenberger 5463e66768 Fix generation of the address size override prefix. Add assertions for 
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.

llvm-svn: 153166
 2012-03-21 05:48:07 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler. 
llvm-svn: 150899
 2012-02-19 01:39:49 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. 
llvm-svn: 150873
 2012-02-18 08:19:49 +00:00
Anton Korobeynikov c6b4017ce2 Add support for implicit TLS model used with MS VC runtime. 
Patch by Kai Nacke!

llvm-svn: 150307
 2012-02-11 17:26:53 +00:00
Craig Topper 4ed7278ff4 Convert assert(0) to llvm_unreachable in X86 Target directory. 
llvm-svn: 149809
 2012-02-05 05:38:58 +00:00
Jim Grosbach 8f28dbdde5 Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
Craig Topper cd93de93fa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Jan Sjödin 6dd2488383 XOP encoding bits and logic. 
llvm-svn: 146397
 2011-12-12 19:12:26 +00:00
Rafael Espindola c7f355b8e1 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
 2011-12-10 02:28:43 +00:00
Jan Sjödin d19760a40c Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding. 
llvm-svn: 146151
 2011-12-08 14:43:19 +00:00
Bruno Cardoso Lopes 0f9a1f5e6c This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
Craig Topper 980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper 27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Bruno Cardoso Lopes 60aa85b672 Tidy up a bit more, fix tab and remove trailing whitespaces 
llvm-svn: 140186
 2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes 05f3f4939a Tidy up code! 
llvm-svn: 140183
 2011-09-20 21:39:06 +00:00
Bruno Cardoso Lopes d126347f32 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Bruno Cardoso Lopes 22241acc29 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
 2011-07-27 23:22:03 +00:00
Jeffrey Yasskin 6381c0100b Explicitly cast narrowing conversions inside {}s that will become errors in 
C++0x.

llvm-svn: 136211
 2011-07-27 06:22:51 +00:00
Evan Cheng b25310095f More refactoring. 
llvm-svn: 135939
 2011-07-25 19:33:48 +00:00