7c10252943
[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.
...
llvm-svn: 225432
2015-01-08 07:41:30 +00:00
627df427eb
[Hexagon] Adding floating point classification and creation.
...
llvm-svn: 225374
2015-01-07 20:28:57 +00:00
290ece7d4c
[Hexagon] Adding encodings for v5 floating point instructions.
...
llvm-svn: 225372
2015-01-07 20:24:09 +00:00
777abcb1d7
[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
...
llvm-svn: 225371
2015-01-07 20:07:28 +00:00
507dd32703
[Hexagon] Adding compound jump encodings.
...
llvm-svn: 225291
2015-01-06 20:03:31 +00:00
68b2e050f0
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
...
llvm-svn: 225283
2015-01-06 19:03:20 +00:00
d9c605ddae
[Hexagon] Adding encoding information for absolute address loads.
...
llvm-svn: 225279
2015-01-06 18:38:26 +00:00
1445553474
[Hexagon] Adding dealloc_return encoding and absolute address stores.
...
llvm-svn: 225267
2015-01-06 16:15:15 +00:00
639445494f
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
...
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.
llvm-svn: 225256
2015-01-06 08:59:30 +00:00
dacf057bdc
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
...
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
28bb02a8c7
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
...
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
abdf2b37d8
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
...
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
3acfddd6b5
[Hexagon] Adding V4 logic-logic instructions and tests.
...
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
ff10c8c95c
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
...
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
5e079577e1
[Hexagon] Adding round reg/imm and bitsplit instructions.
...
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
4edc66b8de
[PowerPC] Add support for the CMPB instruction
...
Newer POWER cores, and the A2, support the cmpb instruction. This instruction
compares its operands, treating each of the 8 bytes in the GPRs separately,
returning a 'mask' result of 0 (for false) or -1 (for true) in each byte.
Code generation support is added, in the form of a PPCISelDAGToDAG
DAG-preprocessing routine, that recognizes patterns close to what the
instruction computes (either exactly, or related by a constant masking
operation), and generates the cmpb instruction (along with any necessary
constant masking operation). This can be expanded if use cases arise.
llvm-svn: 225106
2015-01-03 01:16:37 +00:00
ae8e1b3831
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.
...
llvm-svn: 225099
2015-01-03 00:00:20 +00:00
055845f5cb
[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.
...
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.
Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.
llvm-svn: 225075
2015-01-02 07:02:25 +00:00
a7a8c4c09e
[X86] Update disassembler tests for absolute move instructions to check the encodings. This provides testing for r225036. 64-bit mode is still broken.
...
llvm-svn: 225037
2014-12-31 07:24:23 +00:00
bc405294f0
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
...
llvm-svn: 225024
2014-12-31 00:08:34 +00:00
8971e055ae
[Hexagon] Adding double-logic on predicate instructions.
...
llvm-svn: 225018
2014-12-30 23:22:39 +00:00
65f3e12ed1
[Hexagon] Adding newvalue compare and jumps.
...
llvm-svn: 225015
2014-12-30 23:04:21 +00:00
0cba5f1b43
[Hexagon] Adding postincrement register newvalue stores.
...
llvm-svn: 225010
2014-12-30 22:34:08 +00:00
9014890819
[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
...
llvm-svn: 225009
2014-12-30 22:28:31 +00:00
820d5cb608
[Hexagon] Adding indexed store new-value variants.
...
llvm-svn: 225007
2014-12-30 22:00:26 +00:00
2bad4a7177
[Hexagon] Adding indexed store of immediates.
...
llvm-svn: 225006
2014-12-30 21:01:38 +00:00
94a498bf0e
[Hexagon] Adding indexed stores.
...
llvm-svn: 225005
2014-12-30 20:42:23 +00:00
9161d47476
[Hexagon] Adding reg-reg indexed load forms.
...
llvm-svn: 224997
2014-12-30 18:58:47 +00:00
377ac65340
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
...
llvm-svn: 224991
2014-12-30 17:39:24 +00:00
d7a56fd9ff
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
...
llvm-svn: 224989
2014-12-30 15:44:17 +00:00
aa1c51ee01
Testcases for r224939.
...
llvm-svn: 224976
2014-12-30 02:35:56 +00:00
651b72095b
[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
...
llvm-svn: 224957
2014-12-29 21:33:45 +00:00
bda31b42a0
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
...
llvm-svn: 224952
2014-12-29 20:44:51 +00:00
9a3cd3f58c
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
...
llvm-svn: 224951
2014-12-29 20:00:43 +00:00
3d34afb32d
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
...
llvm-svn: 224949
2014-12-29 19:42:14 +00:00
8233fb002d
[Hexagon] Adding auto-incrementing loads with and without byte reversal.
...
llvm-svn: 224871
2014-12-26 21:09:25 +00:00
0a721cd4e1
[Hexagon] Adding locked loads.
...
llvm-svn: 224870
2014-12-26 20:42:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
...
llvm-svn: 224869
2014-12-26 20:30:58 +00:00
c83cbbf6a1
[Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
...
llvm-svn: 224868
2014-12-26 19:31:46 +00:00
fe9612e09d
[Hexagon] Adding post-increment unsigned byte loads.
...
llvm-svn: 224867
2014-12-26 19:12:11 +00:00
96976a10a3
[Hexagon] Adding post-increment signed byte loads with tests.
...
llvm-svn: 224866
2014-12-26 18:57:13 +00:00
c4b12166f2
[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them.
...
llvm-svn: 224862
2014-12-26 18:20:05 +00:00
d5b39237a1
[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references.
...
llvm-svn: 224861
2014-12-26 18:19:44 +00:00
ee9eef2fd8
Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4.
...
llvm-svn: 224846
2014-12-26 06:36:28 +00:00
947cd70413
[Hexagon] Adding doubleword load.
...
llvm-svn: 224787
2014-12-23 20:44:59 +00:00
026e88d317
[Hexagon] Reapplying 224775 load words.
...
llvm-svn: 224786
2014-12-23 20:02:16 +00:00
ab6d1cce3e
[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
...
Differential Revision: http://reviews.llvm.org/D5204
llvm-svn: 224785
2014-12-23 19:55:34 +00:00
20be15718b
Reverting 224775 until mayLoad flag is addressed.
...
llvm-svn: 224783
2014-12-23 19:22:59 +00:00
122aeaafea
[Hexagon] Adding word loads.
...
llvm-svn: 224775
2014-12-23 18:06:56 +00:00
8e39cad934
[Hexagon] Adding signed halfword loads.
...
llvm-svn: 224774
2014-12-23 17:25:57 +00:00
Craig Topper