2fbeaf084f
Remove some unused variables and methods warned about by
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icc (#177 , partial). Patch by Erick Tryzelaar.
llvm-svn: 81106
2009-09-06 08:33:48 +00:00
1eaa90b901
Whitespace cleanup
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llvm-svn: 80978
2009-09-04 01:38:51 +00:00
d93c668f00
Calls clobber FPSCR.
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llvm-svn: 80956
2009-09-03 22:12:28 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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llvm-svn: 80904
2009-09-03 07:04:02 +00:00
f0da41c3e4
More missed vdup patterns
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llvm-svn: 80838
2009-09-02 21:21:28 +00:00
68c5f477fa
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
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llvm-svn: 80773
2009-09-02 08:44:58 +00:00
e4459e466f
reduce size of SmallString to something more reasonable
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llvm-svn: 80710
2009-09-01 18:55:08 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
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llvm-svn: 80707
2009-09-01 18:51:56 +00:00
c5fcbdc7ee
Use raw_ostream instead of sstream
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llvm-svn: 80704
2009-09-01 18:49:12 +00:00
5f582b7290
RRX reads CPSR.
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llvm-svn: 80699
2009-09-01 18:32:09 +00:00
da9817cddd
Generate code for vld{234}_lane intrinsics.
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llvm-svn: 80656
2009-09-01 04:26:28 +00:00
345a5ae6e4
Fix compiler warnings
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llvm-svn: 80650
2009-09-01 02:05:03 +00:00
20eac92d88
Clean up LSDA name generation and use for SJLJ exception handling. This
...
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
llvm-svn: 80649
2009-09-01 01:57:56 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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llvm-svn: 80615
2009-08-31 20:14:07 +00:00
3c62f5095a
Normalize makefile comments and sort cmake file lists.
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llvm-svn: 80584
2009-08-31 13:05:24 +00:00
3681144bd8
Add missed pattern
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llvm-svn: 80502
2009-08-30 19:06:39 +00:00
eab572a8ff
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
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Remove the assertion and generalize the code for ARM NEON stuff.
llvm-svn: 80498
2009-08-30 17:14:54 +00:00
ece642a54c
Do not assert on too wide splats we don't support.
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llvm-svn: 80409
2009-08-29 00:08:18 +00:00
cd41d07f29
Add missed extract_element pattern
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llvm-svn: 80408
2009-08-28 23:41:26 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
3033db2448
Fix -Asserts warning, round two.
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llvm-svn: 80354
2009-08-28 08:08:22 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
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llvm-svn: 80350
2009-08-28 06:59:37 +00:00
d46e3466e7
Fix -Asserts warning.
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llvm-svn: 80338
2009-08-28 05:47:56 +00:00
6da267de23
v4, v5 does not support sxtb / sxth.
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llvm-svn: 80322
2009-08-28 00:31:43 +00:00
ba53af58f0
Hopefully the final missing part :(
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scalar_to_vector is fully legal now
llvm-svn: 80251
2009-08-27 16:25:49 +00:00
076f105d86
Forgot about actual change :)
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llvm-svn: 80250
2009-08-27 16:10:17 +00:00
58ebae4acd
Transform float scalar_to_vector into subreg accesses.
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No idea whether this is profitable or not.
llvm-svn: 80245
2009-08-27 14:38:44 +00:00
209baa5c48
STRD and LDRD require ARMv5TE, not just ARMv5T.
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See http://llvm.org/PR4687 for more info and links.
llvm-svn: 80244
2009-08-27 14:14:21 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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llvm-svn: 80191
2009-08-27 01:23:50 +00:00
e0636a7aed
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
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The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
llvm-svn: 80117
2009-08-26 17:39:53 +00:00
0f756b27ae
Expand scalar_to_vector - we don't have any isel logic for it now
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llvm-svn: 80107
2009-08-26 16:26:09 +00:00
f1beef9f48
Remove some unused SDNode definitions.
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llvm-svn: 80015
2009-08-25 17:52:39 +00:00
9129376719
Expose the instruction contraint string as an argument to the NLdSt class.
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llvm-svn: 80011
2009-08-25 17:46:06 +00:00
6bbeda41b9
Make linkerprivate work for ARM and PPC. Testcase covers
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all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
llvm-svn: 79877
2009-08-24 01:03:42 +00:00
30ebdc4311
remove the last uses of Config/alloca.h
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llvm-svn: 79873
2009-08-23 22:57:38 +00:00
940fbb0e3c
Remove Streams.h from the targets.
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llvm-svn: 79853
2009-08-23 11:52:17 +00:00
af29ea6d57
eliminate the last DOUTs from the targets.
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llvm-svn: 79833
2009-08-23 06:49:22 +00:00
a6f074fb3a
remove various std::ostream version of printing methods from
...
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
llvm-svn: 79813
2009-08-23 03:41:05 +00:00
f7b571726a
Forgot to update some CMakeLists.
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llvm-svn: 79780
2009-08-22 22:20:11 +00:00
e9a75a6654
rename TAI -> MAI, being careful not to make MAILJMP instructions :)
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llvm-svn: 79777
2009-08-22 21:43:10 +00:00
054574666a
rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.
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llvm-svn: 79773
2009-08-22 21:03:30 +00:00
7b26fce23e
Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.
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llvm-svn: 79763
2009-08-22 20:48:53 +00:00
0939595711
Record variable debug info at ISel time directly.
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llvm-svn: 79742
2009-08-22 17:12:53 +00:00
682d8c1881
Make x86 test actually test x86 code generation. Fix the
...
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
2009-08-22 03:13:10 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a70623102e
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
...
now using shuffles instead of intrinsics.
llvm-svn: 79673
2009-08-21 20:54:19 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
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llvm-svn: 79625
2009-08-21 12:41:42 +00:00
9a232f46a8
Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table.
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llvm-svn: 79624
2009-08-21 12:41:24 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
...
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
e3046618de
Expand EXTRACT_SUBVECTOR
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llvm-svn: 79621
2009-08-21 12:40:35 +00:00
38f284f2ae
Provide vext.{16,32}
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llvm-svn: 79620
2009-08-21 12:40:21 +00:00
c32e99e3ed
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle
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llvm-svn: 79619
2009-08-21 12:40:07 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
...
vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
01de985ae6
Fix an obvious copy-n-paste bug.
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llvm-svn: 79535
2009-08-20 17:01:04 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
...
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
4b7dadb76e
eliminate AsmPrinter::SwitchToSection and just have clients
...
talk to the MCStreamer directly instead.
llvm-svn: 79405
2009-08-19 05:49:37 +00:00
36d747745e
Simplify RegScavenger::FindUnusedReg.
...
- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
llvm-svn: 79369
2009-08-18 21:14:54 +00:00
dd406177de
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
2c64130c43
Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.
...
llvm-svn: 79189
2009-08-16 11:56:42 +00:00
bae6b2cca3
Reapply r79127. It was fixed by d0k.
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llvm-svn: 79136
2009-08-15 21:21:19 +00:00
d3fade656f
Revert r79127. It was causing compilation errors.
...
llvm-svn: 79135
2009-08-15 21:14:01 +00:00
52d4e64711
Change allowsUnalignedMemoryAccesses to take type argument since some targets
...
support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
2009-08-15 19:23:44 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
75c9e535c6
Do not use frame register to reference fixed stack objects if the function is frameless.
...
llvm-svn: 79067
2009-08-15 02:05:35 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
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llvm-svn: 79039
2009-08-14 20:48:13 +00:00
a6b3ce203a
Allow targets to specify their choice of calling conventions per
...
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
llvm-svn: 79033
2009-08-14 20:10:52 +00:00
dc49a8d3f1
Add Thumb2 lsr hooks.
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llvm-svn: 79032
2009-08-14 20:09:37 +00:00
09c070f4ce
80 col violation.
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llvm-svn: 79026
2009-08-14 19:11:20 +00:00
9a58aff837
Indentation.
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llvm-svn: 79022
2009-08-14 19:01:37 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
6f34e278c7
Now that all the legal Neon shuffles (or at least the ones that have been
...
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
llvm-svn: 78995
2009-08-14 05:16:33 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
...
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
76fa6e6a8f
New entry.
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llvm-svn: 78968
2009-08-14 00:16:47 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
...
llvm-svn: 78948
2009-08-13 21:58:54 +00:00
86c065dd68
Revert 78892 and 78895, these break generating working executables on
...
x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
llvm-svn: 78919
2009-08-13 17:03:38 +00:00
eba70d85cf
Add missing defs of R2 and D1.
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llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
...
llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
...
llvm-svn: 78904
2009-08-13 15:11:43 +00:00
f59e9f4288
tPOP_RET now has predicate operands.
...
llvm-svn: 78898
2009-08-13 06:05:07 +00:00
3e4c012d54
Add a fixme message about canonicalizing floating-point vector types.
...
llvm-svn: 78897
2009-08-13 06:01:30 +00:00
ef6e602bf4
Revert r78852 for now. I want to do this differently, but I don't have time
...
to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
e5801bd220
It's ok to spill a tGPR register as long as it's still allocated a low register.
...
llvm-svn: 78893
2009-08-13 05:40:51 +00:00
eb68198145
fix a minor fixme. When building with SL and later tools, the ".eh" symbols
...
don't need to be exported from the .o files.
llvm-svn: 78892
2009-08-13 05:30:22 +00:00
607cd3b63a
Change MCSectionELF to represent a section semantically instead of
...
syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
llvm-svn: 78890
2009-08-13 05:07:35 +00:00
c6800b55e6
Add a comment to describe why vector shuffles are legalized to custom DAG nodes.
...
llvm-svn: 78884
2009-08-13 02:13:04 +00:00
fcd6361ad1
Use cast<> instead of dyn_cast<> in places where the type is known.
...
llvm-svn: 78881
2009-08-13 01:57:47 +00:00
ef3d457126
Various AsmWriter output cleanups. Use WriteAsOperand instead of
...
PrintUnmangledNameSafely.
llvm-svn: 78878
2009-08-13 01:36:44 +00:00
ff2db10211
Recognize Neon VDUP shuffles during legalization instead of selection.
...
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
ea3a402ae7
Recognize Neon VREV shuffles during legalization instead of selection.
...
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
1432ef864e
This void is implicit in C++.
...
llvm-svn: 78848
2009-08-12 22:10:57 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
aee7e49c50
PredCC is meant to be 2 bits wide, like PredCC1.
...
llvm-svn: 78829
2009-08-12 18:35:50 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
3cfc6463c9
Add catch block handling to SjLj exception handling.
...
llvm-svn: 78817
2009-08-12 17:38:44 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
...
llvm-svn: 78806
2009-08-12 15:21:13 +00:00
Duncan Sands