7366fa1aa6
(1) Added special register class containing (for now) %fsr.
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Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
llvm-svn: 6341
2003-05-27 00:05:23 +00:00
f22d1f5912
Fix a bug which occurred with empty basic blocks
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llvm-svn: 5982
2003-05-02 18:44:42 +00:00
176866caed
Fix problems with empty basic blocks
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llvm-svn: 5326
2003-01-16 18:06:43 +00:00
c52c791806
Arg, fix bugs in previous checkin...
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llvm-svn: 5322
2003-01-16 02:24:20 +00:00
910ee768d0
Add assertion
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llvm-svn: 5321
2003-01-16 02:22:08 +00:00
86ee825bce
* Insert prolog/epilog code before rewriting indexes
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* Fix calculation of frame offsets when there is an offset.
llvm-svn: 5318
2003-01-15 22:52:34 +00:00
b4d58d7f9e
Rename MachineInstrInfo -> TargetInstrInfo
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llvm-svn: 5272
2003-01-14 22:00:31 +00:00
8d2a07ab2f
Convert to MachineFunctionPass
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llvm-svn: 5218
2003-01-13 00:23:41 +00:00
ca4362fee7
Rename FunctionFrameInfo to MachineFrameInfo
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llvm-svn: 5200
2002-12-28 21:08:26 +00:00
871e591e34
Rename MachineFrameInfo to TargetFrameInfo.h
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llvm-svn: 5199
2002-12-28 21:00:25 +00:00
c8b36e6362
Initial checkin of Prolog/Epilog code inserter, which is an important part
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of the abstract frame representation
llvm-svn: 5198
2002-12-28 20:43:30 +00:00
Vikram S. Adve