llvm-project

Commit Graph

Author	SHA1	Message	Date
Sebastian Neubauer	4897effb14	[AMDGPU] Add TransVALU to gfx10 Instructions on the transcendental unit are executed in parallel to the normal VALU, so add this as an extra resource. This doesn't seem to have any effect, but it should be more correct. Differential Revision: https://reviews.llvm.org/D100123	2021-04-20 15:34:43 +02:00
Andrew Savonichev	292da93d59	[MCA] Disable RCU for InOrderIssueStage This is a follow-up for: D98604 [MCA] Ensure that writes occur in-order When instructions are aligned by the order of writes, they retire in-order naturally. There is no need for an RCU, so it is disabled. Differential Revision: https://reviews.llvm.org/D98628	2021-03-24 13:54:04 +03:00
Jay Foad	7340fd6886	[MCA] Support in-order CPUs with MicroOpBufferSize=1 Differential Revision: https://reviews.llvm.org/D98356	2021-03-11 10:12:54 +00:00

Author

SHA1

Message

Date

Sebastian Neubauer

4897effb14

[AMDGPU] Add TransVALU to gfx10

Instructions on the transcendental unit are executed in parallel to the
normal VALU, so add this as an extra resource.

This doesn't seem to have any effect, but it should be more correct.

Differential Revision: https://reviews.llvm.org/D100123

2021-04-20 15:34:43 +02:00

Andrew Savonichev

292da93d59

[MCA] Disable RCU for InOrderIssueStage

This is a follow-up for:
D98604 [MCA] Ensure that writes occur in-order

When instructions are aligned by the order of writes, they retire
in-order naturally. There is no need for an RCU, so it is disabled.

Differential Revision: https://reviews.llvm.org/D98628

2021-03-24 13:54:04 +03:00

Jay Foad

7340fd6886

[MCA] Support in-order CPUs with MicroOpBufferSize=1

Differential Revision: https://reviews.llvm.org/D98356

2021-03-11 10:12:54 +00:00

3 Commits