Commit Graph

2501 Commits

Author SHA1 Message Date
David Goodwin 8370485db9 Break anti-dependence breaking out into its own class.
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
Dan Gohman d632f89596 Make LSR's OptimizeShadowIV ignore induction variables with negative
strides for now, because it doesn't handle them correctly. This fixes a
miscompile of SingleSource/Benchmarks/Misc-C++/ray.

This problem was usually hidden because indvars transforms such induction
variables into negations of canonical induction variables.

llvm-svn: 85118
2009-10-26 15:32:57 +00:00
Evan Cheng b81cb2a9a8 - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091
2009-10-26 04:56:07 +00:00
Chris Lattner e38317f432 fix PR5295 where the .ll parser didn't reject a function after a global
or global after a function with conflicting names.  Update some testcases
that were accidentally depending on this behavior.

llvm-svn: 85081
2009-10-25 23:22:50 +00:00
Evan Cheng 69140ec4fa Add a couple of ARM cross-rc coalescing tests.
llvm-svn: 85051
2009-10-25 08:01:41 +00:00
Evan Cheng b9f3520660 Update tests.
llvm-svn: 85050
2009-10-25 07:53:48 +00:00
Dan Gohman 4ef112be62 APInt-ify the gep scaling code, so that it correctly handles the case where
the scale overflows pointer-sized arithmetic. This fixes PR5281.

llvm-svn: 84954
2009-10-23 17:57:43 +00:00
Evan Cheng 36f4bd0b62 Update tests for 84931.
llvm-svn: 84932
2009-10-23 05:58:34 +00:00
David Goodwin 02ad4cb32e Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
Bob Wilson 9d763cc3f8 Revert 84843. Evan, this was breaking some of the if-conversion tests.
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
Evan Cheng 3615b9bef3 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
Evan Cheng 0f55e9ce2e Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
Anton Korobeynikov f1ad2c618a Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
Yay for ASCII graphics!

llvm-svn: 84808
2009-10-22 00:16:00 +00:00
Dan Gohman ff97acd8f1 Revert the main portion of r31856. It was causing BranchFolding
to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.

This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.

llvm-svn: 84803
2009-10-22 00:03:58 +00:00
Jim Grosbach a93ca3c637 Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
2009-10-21 20:44:34 +00:00
Anton Korobeynikov 9e92857b38 Add DAG printing for RMW stuff debugging
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
Anton Korobeynikov ccfa3e31f7 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
Evan Cheng 786b15fe12 Match more patterns to movt.
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
Dan Gohman 682a2d154a Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
llvm-svn: 84727
2009-10-21 01:44:44 +00:00
Anton Korobeynikov 7cea91e171 Add reg-imm tests
llvm-svn: 84705
2009-10-21 00:11:44 +00:00
Anton Korobeynikov a6faf60831 Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)
transform.

llvm-svn: 84683
2009-10-20 21:37:45 +00:00
David Goodwin baf6dd26ea Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
llvm-svn: 84658
2009-10-20 19:54:44 +00:00
Dan Gohman 4a43e3068d Make TranslateX86CC return COND_INVALID instead of aborting when it
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640
2009-10-20 16:22:37 +00:00
Dan Gohman c0964a571b Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks are
tracked. Instead of trying to manually keep track of these locations
while doing complex modifications, just recompute them when they're needed.
This fixes a bug in which the TopMBB and BotMBB were not correctly updated,
leading to invalid transformations.

llvm-svn: 84598
2009-10-20 04:50:37 +00:00
Evan Cheng fa4bcaec7c If the physical register being spilled does not have an interval, spill its sub-registers instead.
llvm-svn: 84586
2009-10-20 01:31:09 +00:00
Jim Grosbach f5f263f1b4 Enable allocation of R3 in Thumb1
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
Chris Lattner 0ed889521b convert to filecheck syntax and make a lot more aggressive.
llvm-svn: 84517
2009-10-19 18:27:56 +00:00
Anton Korobeynikov 8383c3d7f3 Revert r84295, this unbreaks llvm-gcc bootstrap on x86-64/linux
llvm-svn: 84516
2009-10-19 18:21:09 +00:00
Chris Lattner 7ea0c35ba0 rename test
llvm-svn: 84515
2009-10-19 18:18:07 +00:00
Torok Edwin 033f01c922 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.

llvm-svn: 84485
2009-10-19 11:00:58 +00:00
Daniel Dunbar 1df7ea05c3 Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' aren't tests.
llvm-svn: 84460
2009-10-19 03:53:55 +00:00
Nate Begeman 18df82a20c Add support for matching shuffle patterns with palignr.
llvm-svn: 84459
2009-10-19 02:17:23 +00:00
Evan Cheng c436631a9c Turn on post-alloc scheduling for x86.
llvm-svn: 84431
2009-10-18 19:57:27 +00:00
Dan Gohman 0d3d9ee03e Enhance CodePlacementOpt's unconditional intra-loop branch elimination logic
to be more general and understand more varieties of loops.

Teach CodePlacementOpt to reorganize the basic blocks of a loop so that
they are contiguous. This also includes a fair amount of logic for preserving
fall-through edges while doing so. This fixes a BranchFolding-ism where blocks
which can't be made to use a fall-through edge and don't conveniently fit
anywhere nearby get tossed out to the end of the function.

llvm-svn: 84295
2009-10-17 00:32:43 +00:00
Mon P Wang 1a015acf69 Update tests to use FileCheck
llvm-svn: 84282
2009-10-16 22:09:05 +00:00
Mon P Wang 0185b1ea85 Add test case for r84279
llvm-svn: 84280
2009-10-16 22:07:19 +00:00
Dan Gohman 99429a00ff Move zext and sext casts fed by loads into the same block as the
load, to help SelectionDAG fold them into the loads, unless
conditions are unfavorable.

llvm-svn: 84271
2009-10-16 20:59:35 +00:00
Evan Cheng 03da4dba59 Enable post-alloc scheduling for all ARM variants except for Thumb1.
llvm-svn: 84249
2009-10-16 06:11:08 +00:00
Sandeep Patel 3f23601b00 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
Sanjiv Gupta a07cae65e3 Re-apply 84180 with the fixed test case.
llvm-svn: 84195
2009-10-15 19:26:25 +00:00
Jakob Stoklund Olesen 460ceae432 Move Blackfin intrinsics into the Target/Blackfin directory.
llvm-svn: 84194
2009-10-15 18:50:52 +00:00
Dan Gohman c9af381df8 Make CodePlacementOpt align loops, rather than loop headers. The
header is just the entry block to the loop, and it needn't be at
the top of the loop in the code layout.

Remove the code that suppressed loop alignment for outer loops,
so that outer loops are aligned.

llvm-svn: 84158
2009-10-15 00:36:22 +00:00
Evan Cheng 2f61e0946a When LiveVariables is adding implicit-def to model "partial dead", add the earlyclobber marker if the superreg def has it.
llvm-svn: 84153
2009-10-14 23:39:27 +00:00
Dan Gohman 03a7667349 Fix this test to account for a movl $0 being emitted as an xor now,
and convert it to FileCheck.

llvm-svn: 84065
2009-10-14 00:28:48 +00:00
Bob Wilson 3b51560ae4 Revise ARM inline assembly memory operands to require the memory address to
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
2009-10-13 20:50:28 +00:00
Sandeep Patel 423e42b371 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
Dan Gohman a698d7ac3c Don't forget to mark RAX as live-out of the function when arranging for
it to hold the address of an sret return value, for x86-64 ABI purposes.

Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.

llvm-svn: 83853
2009-10-12 16:36:12 +00:00
Benjamin Kramer 258c7fa33a Eliminate some redundant llvm-as calls.
llvm-svn: 83837
2009-10-12 09:31:55 +00:00
Anton Korobeynikov 4b38ce9f25 Add missed mem-mem move patterns
llvm-svn: 83812
2009-10-11 23:03:53 +00:00
Anton Korobeynikov 415c3dc501 Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
llvm-svn: 83811
2009-10-11 23:03:28 +00:00