llvm-project

Commit Graph

Author	SHA1	Message	Date
Simon Pilgrim	85b87179f4	[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs Split SSE2 and SSSE3 costs to correctly handle PSHUFB lowering - as was noted on D111938	2021-10-16 17:28:07 +01:00
Simon Pilgrim	6ec644e215	[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs These cases use the same codegen as AVX2 (pshuflw/pshufd) for the sub-128bit vector deinterleaving, and unpcklqdq for v2i64. It's going to take a while to add full interleaved cost coverage, but since these are the same for SSE2 -> AVX2 it should be an easy win. Fixes PR47437 Differential Revision: https://reviews.llvm.org/D111938	2021-10-16 16:21:45 +01:00
Simon Pilgrim	d5f5121ea6	[LV][X86] Add PR47437 test case	2021-10-16 13:40:54 +01:00

Author

SHA1

Message

Date

Simon Pilgrim

85b87179f4

[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs

Split SSE2 and SSSE3 costs to correctly handle PSHUFB lowering - as was noted on D111938

2021-10-16 17:28:07 +01:00

Simon Pilgrim

6ec644e215

[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs

These cases use the same codegen as AVX2 (pshuflw/pshufd) for the sub-128bit vector deinterleaving, and unpcklqdq for v2i64.

It's going to take a while to add full interleaved cost coverage, but since these are the same for SSE2 -> AVX2 it should be an easy win.

Fixes PR47437

Differential Revision: https://reviews.llvm.org/D111938

2021-10-16 16:21:45 +01:00

Simon Pilgrim

d5f5121ea6

[LV][X86] Add PR47437 test case

2021-10-16 13:40:54 +01:00

3 Commits