Commit Graph

569 Commits

Author SHA1 Message Date
Frederic Cambus bc01d8fbcf [compiler-rt] Remove mentions of AuroraUX in code comments and docs.
AuroraUX was an operating system project based on an OpenSolaris kernel
and an Ada userland.

There appear to be no public code or release available online anymore.
The project page on Wikipedia [1] was deleted in January 2012, and a news
item [2] from November 2012 has more details.

[1] https://en.wikipedia.org/w/index.php?title=Special:Log/delete&page=AuroraUX
[2] https://www.phoronix.com/scan.php?page=news_item&px=MTIyMTI
2022-03-21 22:05:58 +01:00
James Y Knight 4a6fab793f [compiler-rt] Expand comment about Exynos 9810 workaround. 2022-03-21 13:35:11 +00:00
Roman Lebedev c62746ac6e
[X86] Fix AMD Znver3 model checks
While `-march=` is correctly detected as `znver3` for the cpu,
apparently the model check is incorrect:
```
$ lscpu
Architecture:            x86_64
  CPU op-mode(s):        32-bit, 64-bit
  Address sizes:         48 bits physical, 48 bits virtual
  Byte Order:            Little Endian
CPU(s):                  32
  On-line CPU(s) list:   0-31
Vendor ID:               AuthenticAMD
  Model name:            AMD Ryzen 9 5950X 16-Core Processor
    CPU family:          25
    Model:               33
    Thread(s) per core:  2
    Core(s) per socket:  16
    Socket(s):           1
    Stepping:            0
    Frequency boost:     disabled
    CPU max MHz:         6017.8462
    CPU min MHz:         2200.0000
    BogoMIPS:            8050.07
    Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse
                         3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_p
                         state ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbn
                         oinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
Virtualization features:
  Virtualization:        AMD-V
Caches (sum of all):
  L1d:                   512 KiB (16 instances)
  L1i:                   512 KiB (16 instances)
  L2:                    8 MiB (16 instances)
  L3:                    64 MiB (2 instances)
NUMA:
  NUMA node(s):          1
  NUMA node0 CPU(s):     0-31
Vulnerabilities:
  Itlb multihit:         Not affected
  L1tf:                  Not affected
  Mds:                   Not affected
  Meltdown:              Not affected
  Spec store bypass:     Mitigation; Speculative Store Bypass disabled via prctl
  Spectre v1:            Mitigation; usercopy/swapgs barriers and __user pointer sanitization
  Spectre v2:            Mitigation; Retpolines, IBPB conditional, IBRS_FW, STIBP always-on, RSB filling
  Srbds:                 Not affected
  Tsx async abort:       Not affected
```

Model is 33 (0x21), while the code was expecting it to be `0x00 .. 0x1F`.
https://github.com/torvalds/linux/blob/v5.17-rc8/drivers/hwmon/k10temp.c#L432-L453 agrees.
I'm not sure if other ranges listed here should also be accepted.

I noticed this while implementing CPU model detection
for halide (https://github.com/halide/Halide/pull/6648)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121708
2022-03-15 20:28:02 +03:00
Khem Raj 5017de8ba4 [builtins] Do not force thumb mode directive in arm/sync-ops.h
.thumb_func was not switching mode until [1]
so it did not show up but now that .thumb_func (without argument) is
switching mode, its causing build failures on armv6 ( rpi0 ) even when
build is explicitly asking for this file to be built with -marm (ARM
mode), therefore use DEFINE_COMPILERRT_FUNCTION macro to add function
header which considers arch and mode from compiler cmdline to decide if
the function is built using thumb mode or arm mode.

[1] https://reviews.llvm.org/D101975

Note that it also needs https://reviews.llvm.org/D99282

Reviewed By: peter.smith, MaskRay

Differential Revision: https://reviews.llvm.org/D104183
2022-03-11 16:25:49 -08:00
Khem Raj a11d1cc41c [builtins] Use mcr for dmb instruction on armv6
At present compiler-rt cross compiles for armv6 ( -march=armv6 ) but includes
dmb instructions which are only available in armv7+ this causes SIGILL on
clang+compiler-rt compiled components on rpi0w platforms.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D99282
2022-03-10 19:30:00 -08:00
Kai Luo eb3730cf89 [AIX][cmake][NFC] Customize name of output atomic library
Let `archive-aix-libatomic` accept additional argument to customize name of output atomic library.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D120534
2022-02-28 02:31:56 +00:00
Eli Friedman 0389f2edf7 Revert "[compiler-rt] Implement ARM atomic operations for architectures without SMP support"
This reverts commit 910a642c0a.

There are serious correctness issues with the current approach: __sync_*
routines which are not actually atomic should not be enabled by default.

I'll continue discussion on the review.
2022-02-17 02:17:27 -08:00
Eli Friedman d20e01bb06 Revert "[NFC][compiler-rt] Format file lib/builtins/arm/sync-ops.h"
This reverts commit f165c23bf3.

Part of revert sequence for 910a642c0a.
2022-02-17 02:16:25 -08:00
Pavel Kosov f165c23bf3 [NFC][compiler-rt] Format file lib/builtins/arm/sync-ops.h 2022-02-17 10:21:22 +03:00
Pavel Kosov 910a642c0a [compiler-rt] Implement ARM atomic operations for architectures without SMP support
ARMv5 and older architectures don’t  support SMP and do not have atomic instructions. Still they’re in use in IoT world, where one has to stick to libgcc.

Reviewed By: mstorsjo

Differential Revision: https://reviews.llvm.org/D116088
2022-02-17 10:11:25 +03:00
Tim Northover 4b120c8d63 Compiler-rt: build fp_mode.c for macho_embedded variants too.
It provides some functions needed by add/sub.
2022-02-16 13:37:24 +00:00
Anatoly Trosinenko 4bcd2588a9 [compiler-rt][builtins] Use c[tl]zsi macro instead of __builtin_c[tl]z
`__builtin_c[tl]z` accepts `unsigned int` argument that is not always the
same as uint32_t. For example, `unsigned int` is uint16_t on MSP430.

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D86547
2022-01-30 23:04:07 +03:00
Anatoly Trosinenko 9595f00510 [compiler-rt][builtins] Use explicitly-sized integer types for LibCalls
Use s[iu]_int instead of `(unsigned) int` and d[ui]_int instead of
`(unsigned) long long` for LibCall arguments.

Note: the `*vfp` LibCall versions were NOT touched.

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D86546
2022-01-30 21:10:54 +03:00
Alexandre Ganea ae4c643bcd [compiler-rt] Silence warnings when building with MSVC
Differential Revision: https://reviews.llvm.org/D116872
2022-01-11 10:36:57 -05:00
jinge90 6fab274275 Control-flow Enforcement Technology (CET), published by Intel, introduces
indirect branch tracking(IBT) feature aiming to ensure the target address
of an indirect jump/call is not tampered.
When IBT is enabled, each function or target of any indirect jump/call will start
with an 'endbr32/64' instruction otherwise the program will crash during execution.
To build an application with CET enabled. we need to ensure:

  1. build the source code with "-fcf-protection=full"
  2. all the libraries linked with .o files must be CET enabled too

This patch aims to enable CET for compiler-rt builtins library, we add an option
"COMPILER_RT_ENABLE_CET" whose default value is OFF to enable CET for compiler-rt
in building time and when this option is "ON", "-fcf-protection=full" is added to
BUILTINS_CFLAG and the "endbr32/64" will be placed in the beginning of each assembly
function. We also enabled CET for crtbegin, crtend object files in this patch.

Reviewed by: MaskRay, compnerd, manojgupta, efriedma
Differential Revision: https://reviews.llvm.org/D109811

Signed-off-by: jinge90 <ge.jin@intel.com>
2022-01-10 11:01:11 +08:00
Qiu Chaofan c2cc70e4f5 [NFC] Fix endif comments to match with include guard 2022-01-07 15:52:59 +08:00
Petr Hosek 96e36048fd [CMake] Move the AIX archiver settings to a module
This allows their reuse across projects. The name of the module
is intentionally generic because we would like to move more platform
checks there.

Differential Revision: https://reviews.llvm.org/D115276
2022-01-05 11:46:30 -08:00
John Ericson 949bbd0a68 [CMake] Use `LLVM_COMMON_CMAKE_UTILS` in runtimes just for clarity
In D116472 we created conditionally defined variables for the tools to
unbreak the legacy build where they are in `llvm/tools`.

The runtimes are not tools, so that flexibility doesn't matter. Still,
it might be nice to define (unconditionally) and use the variable for
the runtimes simply to make the code a bit clearer and document what is
going on.

Also, consistently put project dirs at the beginning, not end of `CMAKE_MODULE_PATH`. This ensures they will properly shadow similarly named stuff that happens to be later on the path.

Reviewed By: mstorsjo, #libunwind, #libc, #libc_abi, ldionne

Differential Revision: https://reviews.llvm.org/D116477
2022-01-03 20:55:44 +00:00
Stephen Hines cce4a7258b [compiler-rt][AArch64] Add a workaround for Exynos 9810
Big.LITTLE Heterogeneous architectures, as described by ARM [1],
require that the instruction set architecture of the big and little
cores be compatible. However, the Samsung Exynos 9810 is known to
have different ISAs in its core.
According to [2], some cores are ARMv8.2 and others are ARMv8.0.

Since LSE is for ARMv8.1 and later, it should be disabled
for this broken CPU.

[1] https://developer.arm.com/documentation/den0024/a/big-LITTLE-Technology
[2] https://github.com/golang/go/issues/28431

Patch by: Byoungchan Lee (byoungchan.lee@gmx.com)
Reviewed By: srhines

Differential Revision: https://reviews.llvm.org/D114523
2021-12-14 19:51:46 -08:00
Patrick Oppenlander 06f1d63cb1 [compiler-rt][CMake] Support powerpcspe build
Reviewed By: jhibbits, MaskRay

Differential Revision: https://reviews.llvm.org/D98836
2021-11-26 13:29:06 -08:00
Dimitry Andric 7dbbb5d3a4 compiler-rt: Use FreeBSD's elf_aux_info to detect AArch64 HW features
Using the out-of-line LSE atomics helpers for AArch64 on FreeBSD also
requires adding support for initializing __aarch64_have_lse_atomics
correctly. On Linux this is done with getauxval(3), on FreeBSD with
elf_aux_info(3), which has a slightly different interface.

Differential Revision: https://reviews.llvm.org/D109330
2021-11-20 12:12:03 +01:00
Kai Luo 6ea2431d3f [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall
Add `__c11_atomic_fetch_nand` builtin to language extensions and support `__atomic_fetch_nand` libcall in compiler-rt.

Reviewed By: theraven

Differential Revision: https://reviews.llvm.org/D112400
2021-10-28 02:18:43 +00:00
Petr Hosek 22acda48ff [CMake] Cache the compiler-rt library search results
There's a lot of duplicated calls to find various compiler-rt libraries
from build of runtime libraries like libunwind, libc++, libc++abi and
compiler-rt. The compiler-rt helper module already implemented caching
for results avoid repeated Clang invocations.

This change moves the compiler-rt implementation into a shared location
and reuses it from other runtimes to reduce duplication and speed up
the build.

Differential Revision: https://reviews.llvm.org/D88458
2021-10-27 17:53:03 -07:00
Petr Hosek ba4920e98e Revert "[CMake] Cache the compiler-rt library search results"
This reverts commit 0eed292fba, there
are compiler-rt build failures that appear to have been introduced
by this change.
2021-10-21 10:32:01 -07:00
Petr Hosek 0eed292fba [CMake] Cache the compiler-rt library search results
There's a lot of duplicated calls to find various compiler-rt libraries
from build of runtime libraries like libunwind, libc++, libc++abi and
compiler-rt. The compiler-rt helper module already implemented caching
for results avoid repeated Clang invocations.

This change moves the compiler-rt implementation into a shared location
and reuses it from other runtimes to reduce duplication and speed up
the build.

Differential Revision: https://reviews.llvm.org/D88458
2021-10-18 14:44:07 -07:00
Jeremie Courreges-Anglas 3db9590605 [compiler-rt] Implement __clear_cache() on OpenBSD/riscv64 2021-09-17 15:42:05 -04:00
Jessica Clarke b8d83e83be [RISCV][compiler-rt] Fix an incorrect comment for RV64 __riscv_restore_12
This was presumably copied from the RV32 implementation and not updated
like the rest.
2021-09-15 15:25:59 +01:00
Jessica Clarke bbca392a7f [RISCV][compiler-rt] Move RV64 __riscv_restore_1/0 directives next to labels
This looks like it was copied from the RV32 version and not properly
updated. This has no functional effect but is not good style.
2021-09-15 14:42:22 +01:00
Jessica Clarke 3c885190af [RISCV][compiler-rt] Add missing __riscv_save_1/0 labels for RV64
These got missed in D91717.
2021-09-15 14:42:16 +01:00
Kazuaki Ishizaki a1e7e401d2 [compiler-rt] NFC: Fix trivial typo
Reviewed By: xgupta

Differential Revision: https://reviews.llvm.org/D77457
2021-09-04 14:12:58 +05:30
Martin Storsjö e6407356ba [builtins] Move Windows/ARM frontends for fix/float functions into the individual source files
This avoids pulling in all of them if only one of them is needed
(if builtins are built without -ffunction-sections), and matches how
the similar aliases for AEABI are set up.

Differential Revision: https://reviews.llvm.org/D107815
2021-08-20 09:13:32 +03:00
Freddy Ye d268c20070 [X86] Support auto-detect for tigerlake and alderlake
Differential Revision: https://reviews.llvm.org/D107245
2021-08-02 11:01:01 +08:00
Shoaib Meenai b8f04a670f [builtins] Try to ensure single copy of emulated TLS state
Multiple copies of emulated TLS state means inconsistent results when
accessing the same thread-local variable from different shared objects
(https://github.com/android/ndk/issues/1551). Making `__emutls_get_address`
be a weak default visibility symbol should make the dynamic linker
ensure only a single copy gets used at runtime. This is best-effort, but
the more robust approach of putting emulated TLS into its own shared
object would (a) be a much bigger change, and (b) shared objects are
pretty heavyweight, and adding a new one to a space-constrained
environment isn't an easy sell. Given the expected rarity of direct
accesses to emulated TLS variables across different shared objects, the
best-effort approach should suffice.

Reviewed By: danalbert, rprichard

Differential Revision: https://reviews.llvm.org/D107127
2021-07-30 14:52:38 -07:00
Raul Tambre b31080c596 [compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources
On Apple platforms the builtins may be built for both arm64 and arm64e.
With Makefile generators separate targets are built using Make sub-invocations.
This causes a race when creating the symlink which may sometimes fail.

Work around this by using a custom target that the builtin targets depend on.
This causes any sub-invocations to depend on the symlinks having been created before.

Mailing list thread: https://lists.llvm.org/pipermail/llvm-dev/2021-July/151822.html

Reviewed By: thakis, steven_wu

Differential Revision: https://reviews.llvm.org/D106305
2021-07-26 21:42:27 +03:00
Kristof Beyls 6f0e74cd58 Avoid unnecessary AArch64 DSB in __clear_cache in some situations.
The dsb after instruction cache invalidation only needs to be executed
if any instruction cache invalidation did happen.
Without this change, if the CTR_EL0.DIC bit indicates that instruction
cache invalidation is not needed, __clear_cache would execute two dsb
instructions in a row; with the second one being unnecessary.

Differential Revision: https://reviews.llvm.org/D104371
2021-06-17 07:45:06 +01:00
Alex Richardson 13f0b85212 Fix Windows builders after 244601f472
Apparently __builtin_abort() is not supported when targetting Windows.
This should fix the following builder errors:
clang_rt.builtins-x86_64.lib(int_util.c.obj) : error LNK2019: unresolved
external symbol __builtin_abort referenced in function __compilerrt_abort_impl
2021-06-15 09:47:29 +01:00
Alex Richardson 244601f472 [builtins] Allow compiling the builtins without libc headers
When compiled with -ffreestanding, we should not assume that headers
declaring functions such as abort() are available. While the compiler may
still emit calls to those functions [1], we should not require the headers
to build compiler-rt since that can result in a cyclic dependency graph:
The compiler-rt functions might be required to build libc.so, but the libc
headers such as stdlib.h might only be available once libc has been built.

[1] From https://gcc.gnu.org/onlinedocs/gcc/Standards.html:
GCC requires the freestanding environment provide memcpy, memmove,
memset and memcmp. Finally, if __builtin_trap is used, and the target
does not implement the trap pattern, then GCC emits a call to abort.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D103876
2021-06-15 09:08:59 +01:00
Kai Luo 6393164cf2 [AIX][compiler-rt] Fix cmake build of libatomic for cmake-3.16+
cmake-3.16+ for AIX changes the default behavior of building a `SHARED` library which breaks AIX's build of libatomic, i.e., cmake-3.16+ builds `SHARED` as an archive of dynamic libraries. To fix it, we have to build `libatomic.so.1` as `MODULE` which keeps `libatomic.so.1` as an normal dynamic library.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103786
2021-06-12 00:12:29 +00:00
Stephen Hines 6455418d3d [compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier (dsb) to __clear_cache
https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance
covers how to properly clear caches on AArch64, and the builtin
implementation was missing a `dsb ish` after clearing the icache for the
selected range.

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D104094
2021-06-11 02:13:48 -07:00
Evgeny Leviant 7879fa6884 [compiler-rt] Fix compilation when multiple architectures can be targeted
When toolchain can supports all of arm, armhf and armv6m architectures compiler-rt
libraries won't compile because architecture specific flags are appended to single
BUILTIN_CFLAGS variable.

Differential revision: https://reviews.llvm.org/D103363
2021-06-01 15:26:51 +03:00
Martin Storsjö 9f57675e52 [compiler-rt] [builtins] Provide a SEH specific __gcc_personality_seh0
This matches how __gxx_personality_seh0 is hooked up in libcxxabi.

Differential Revision: https://reviews.llvm.org/D102530
2021-05-18 23:52:33 +03:00
Kai Luo d56729b4a4 [AIX][compiler-rt] Build and install standalone libatomic
On AIX, we have to ship `libatomic.a` for compatibility. First, a new `clang_rt.atomic` is added. Second, use added cmake modules for AIX, we are able to build a compatible libatomic.a for AIX. The second step can't be perfectly implemented with cmake now since AIX's archive approach is kinda unique, i.e., archiving shared libraries into a static archive file.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D102155
2021-05-16 05:04:08 +00:00
Alex Richardson 777ca513c8 [builtins] Fix ABI-incompatibility with GCC for floating-point compare
While implementing support for the float128 routines on x86_64, I noticed
that __builtin_isinf() was returning true for 128-bit floating point
values that are not infinite when compiling with GCC and using the
compiler-rt implementation of the soft-float comparison functions.
After stepping through the assembly, I discovered that this was caused by
GCC assuming a sign-extended 64-bit -1 result, but our implementation
returns an enum (which then has zeroes in the upper bits) and therefore
causes the comparison with -1 to fail.

Fix this by using a CMP_RESULT typedef and add a static_assert that it
matches the GCC soft-float comparison return type when compiling with GCC
(GCC has a __libgcc_cmp_return__ mode that can be used for this purpose).

Also move the 3 copies of the same code to a shared .inc file.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D98205
2021-04-28 12:19:19 +01:00
David Carlier 0df0d6acea [Sanitizers] DragonFlyBSD adding support for builtins
Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D89653
2021-04-17 11:10:35 +01:00
Ties Stuij 3b9dc59dbf [arm][compiler-rt] add armv8m.main and arv8.1m.main targets
These changes were enough to compile compiler-rt builtins for armv8m.main and
armv8.1m.main.

Differential Revision: https://reviews.llvm.org/D99600
2021-04-14 16:41:03 +01:00
Freddy Ye b28ec3fd18 [compiler-rt][X86] fix build fail after "[X86] Support -march=rocketlake"
This copy error will cause a failed builder on sanitizer-x86_64-linux
2021-04-13 14:33:12 +08:00
Freddy Ye 3fc1fe8db8 [X86] Support -march=rocketlake
Reviewed By: skan, craig.topper, MaskRay

Differential Revision: https://reviews.llvm.org/D100085
2021-04-13 09:48:13 +08:00
Daniel Kiss a46effbd2a [compiler-rt][aarch64] Add PAC-RET/BTI support to HWASAN.
Support for -mbranch-protection.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D100143
2021-04-12 17:02:45 +02:00
Alex Richardson ed0bf875a9 [builtins] Avoid enum name conflicts with fenv.h
After a follow-up change (D98332) this header can be included the same time
as fenv.h when running the tests. To avoid enum members conflicting with
the macros/enums defined in the host fenv.h, prefix them with CRT_.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D98333
2021-04-09 18:48:49 +01:00
Daniel Rodríguez Troitiño 813e7249b8 [builtins] Build for arm64_32 for watchOS (Darwin)
Trying to build the builtins code fails because `arm64_32_SOURCES` is
missing. Setting it to the same list used for `aarch64_SOURCES` solves
that problem and allow the builtins to compile for that architecture.

Additionally, arm64_32 is added as a possible architecture for watchos
platforms.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D99690
2021-04-01 17:16:18 -07:00