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Author SHA1 Message Date
Arthur Eubanks e6ead19b77 Revert "Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 2, fixed assertion crash." 
This reverts commit 27bd8f9492.

Causes crashes, see comments in D121973
 2022-03-23 10:57:45 -07:00
Vasileios Porpodas 27bd8f9492 Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 2, fixed assertion crash. 
Original review: https://reviews.llvm.org/D121354

This reverts commit f7d7d2a08d.
 2022-03-22 16:41:55 -07:00
Arthur Eubanks f7d7d2a08d Revert "Recommit "[SLP] Fix lookahead operand reordering for splat loads."" 
This reverts commit 79613185d3.

Causes crashes, see comments in https://reviews.llvm.org/D121973.
 2022-03-22 13:33:49 -07:00
Vasileios Porpodas 79613185d3 Recommit "[SLP] Fix lookahead operand reordering for splat loads." 
Original review: https://reviews.llvm.org/D121354

The original commit 9136145eb0 broke the build on several targets.

Differential Revision: https://reviews.llvm.org/D121973
 2022-03-21 15:57:32 -07:00
Philip Reames ee7324b898 Rename mayBeMemoryDependent to mayHaveNonDefUseDependency [nfc] 2022-03-21 10:01:40 -07:00
Shengchen Kan 37b378386e [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments 2022-03-16 20:25:42 +08:00
serge-sans-paille ed98c1b376 Cleanup includes: DebugInfo & CodeGen 
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332
 2022-03-12 17:26:40 +01:00
Krzysztof Parzyszek 108910c667 [Hexagon] Handle v2f16 in build_vector in isel 2022-03-07 11:54:24 -08:00
Benjamin Kramer 924eac4942 [Hexagon] Move single-use global tables into their only user and turn them into StringSwitch 
Delete the unused globals. NFCI.
 2022-03-06 19:23:09 +01:00
Krzysztof Parzyszek 2cd13e8b00 [Hexagon] Recognize "access size" for dcfetch 
Dcfetch doesn't really have an access size, but the immediate
offset is scaled as for an 8-byte access, so treat it as such.
 2022-03-02 12:57:51 -08:00
Jameson Nash c4b1a63a1b mark getTargetTransformInfo and getTargetIRAnalysis as const 
Seems like this can be const, since Passes shouldn't modify it.

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D120518
 2022-02-25 14:30:44 -05:00
Simon Pilgrim 7104f0c4ab [Hexagon] aligned load/store patterns - use cast<> instead of dyn_cast<> to avoid dereference of nullptr 
The pointer is always referenced inside isAlignedMemNode, so assert the cast is correct instead of returning nullptr
 2022-02-18 10:36:40 +00:00
Roman Lebedev 371fcb720e
[SimplifyCFG][PhaseOrdering] Defer lowering switch into an integer range comparison and branch until after at least the IPSCCP 
That transformation is lossy, as discussed in
https://github.com/llvm/llvm-project/issues/53853
and https://github.com/rust-lang/rust/issues/85133#issuecomment-904185574

This is an alternative to D119839,
which would add a limited IPSCCP into SimplifyCFG.

Unlike lowering switch to lookup, we still want this transformation
to happen relatively early, but after giving a chance for the things
like CVP to do their thing. It seems like deferring it just until
the IPSCCP is enough for the tests at hand, but perhaps we need to
be more aggressive and disable it until CVP.

Fixes https://github.com/llvm/llvm-project/issues/53853
Refs. https://github.com/rust-lang/rust/issues/85133

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D119854
 2022-02-17 12:13:55 +03:00
Shao-Ce SUN 2aed07e96c [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter` 
Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846
 2022-02-16 13:10:09 +08:00
Krzysztof Parzyszek 02e7479e6b [Hexagon] Add patterns for select(i1, Q, Q) 2022-02-11 09:45:20 -08:00
serge-sans-paille ef736a1c39 Cleanup LLVMMC headers 
There's a few relevant forward declarations in there that may require downstream
adding explicit includes:

llvm/MC/MCContext.h no longer includes llvm/BinaryFormat/ELF.h, llvm/MC/MCSubtargetInfo.h, llvm/MC/MCTargetOptions.h
llvm/MC/MCObjectStreamer.h no longer include llvm/MC/MCAssembler.h
llvm/MC/MCAssembler.h no longer includes llvm/MC/MCFixup.h, llvm/MC/MCFragment.h

Counting preprocessed lines required to rebuild llvm-project on my setup:
before: 1052436830
after:  1049293745

Which is significant and backs up the change in addition to the usual benefits of
decreasing coupling between headers and compilation units.

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D119244
 2022-02-09 11:09:17 +01:00
Krzysztof Parzyszek 0792161c00 [Hexagon] Fix operation actions for v128f16 
There were more cases of operations that should have been "Custom" for
v128f16, but ended up "Legal" (e.g. load and store).
 2022-02-08 15:28:37 -08:00
Krzysztof Parzyszek 7403c02f06 [Hexagon] Fix crash with shuffle_vector of v128f16 2022-02-08 13:05:22 -08:00
Kazu Hirata 3a3cb929ab [llvm] Use = default (NFC) 2022-02-06 22:18:35 -08:00
Krzysztof Parzyszek c935f6e048 [Hexagon] Punt on registers without reaching defs in addr mode opt 
This fixes https://github.com/llvm/llvm-project/issues/52636.
 2022-02-01 09:52:59 -08:00
Benjamin Kramer f15014ff54 Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17" 
This reverts commit ef82063207.

- It conflicts with the existing llvm::size in STLExtras, which will now
  never be called.
- Calling it without llvm:: breaks C++17 compat
 2022-01-26 16:55:53 +01:00
serge-sans-paille ef82063207 Rename llvm::array_lengthof into llvm::size to match std::size from C++17 
As a conquence move llvm::array_lengthof from STLExtras.h to
STLForwardCompat.h (which is included by STLExtras.h so no build
breakage expected).
 2022-01-26 16:17:45 +01:00
Nikita Popov aa97bc116d [NFC] Remove uses of PointerType::getElementType() 
Instead use either Type::getPointerElementType() or
Type::getNonOpaquePointerElementType().

This is part of D117885, in preparation for deprecating the API.
 2022-01-25 09:44:52 +01:00
Jim Lin f533011252 [Hexagon] Use llvm::Register instead of unsigned in HexagonConstExtenders.cpp. NFC. 
Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D117851
 2022-01-24 16:06:25 +08:00
Jim Lin d6b0734837 [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
Pranav Bhandarkar bde1032588 [Hexagon] Fix optimize address mode pass only handle BaseImmOffset mode 
This is a fix for a crash in the HexagonOptAddrMode pass that was looking
for the third operand (offset) in the following instruction that does not,
in fact, have a third operand:

  $r1 = L2_loadw_locked $r1

Additionally, this patch also adds an addrMode value to vgather pseudos
in the Hexagon backend.

Differential Revision: https://reviews.llvm.org/D117133
 2022-01-14 15:45:23 -08:00
Kazu Hirata f44473ec4e [llvm] Remove redundant member initialization (NFC) 
Identified with readability-redundant-member-init.
 2022-01-08 11:56:44 -08:00
Vitaly Buka 5c46c1c23a Initialize output parameter 
Or code like this have UB passing uninitialized CmpValue:

```
  int64_t CmpMask, CmpValue;
  if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue))
    return false;
  if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
```

Detected by msan with:
-Xclang -enable-noundef-analysis -mllvm -msan-eager-checks=1

Differential Revision: https://reviews.llvm.org/D116831
 2022-01-07 15:21:22 -08:00
Sumanth Gundapaneni ec2945d031 [Hexagon] Reconize M2_mnaci in HexagonBitTracker 2022-01-07 14:48:29 -08:00
Krzysztof Parzyszek 07ecb98798 [Hexagon] Use map from HexagonDepArch instead of local one, NFC 
Co-authored-by: Brian Cain <bcain@quicinc.com>
 2022-01-07 13:02:57 -08:00
Krzysztof Parzyszek d9ee9a1419 [Hexagon] Extract condition into function, NFC 
Co-authored-by: Brian Cain <bcain@quicinc.com>
 2022-01-07 12:35:12 -08:00
Krzysztof Parzyszek dfbe74be63 [Hexagon] Fix release build break after 5476585673 2022-01-07 12:21:02 -08:00
Michael Lambert 028444c2b3 [Hexagon] Duplex error: wrong branch hint 2022-01-07 12:04:01 -08:00
colinl 4096ef3ed7 [Hexagon] Consider direction hint forming dealloc_return duplex 2022-01-07 12:04:00 -08:00
colinl 5476585673 [Hexagon] Improve check for subinstruction registers 2022-01-07 11:33:14 -08:00
Yuanxiang Ye 137642f433 [Hexagon] Reject accumulating on vd.tmp 
Added hvx accum checker function and test cases.
 2022-01-07 11:13:19 -08:00
Brian Cain 1f71e46f2a [Hexagon] Apply tiny core packet size slots limit 2022-01-07 10:33:12 -08:00
colinl a247360173 [Hexagon] Simplify AX instruction detection 2022-01-07 10:33:12 -08:00
Brian Cain 9af53d2f0c [Hexagon] s/Fatal/ReportErrors/ 
Rename argument from 'Fatal' => 'ReportErrors'.  HexagonShuffler refers to
this arg as 'ReportErrors' and calling it 'Fatal' in HexagonMCShuffler is
misleading and inconsistent.
 2022-01-07 08:27:34 -08:00
Brian Cain a58a062fba [Hexagon] Show slot resources for errors 
For a scalar packet resource error, emit details about the slots
available for each instruction in the packet.
 2022-01-07 08:27:33 -08:00
Krzysztof Parzyszek 88397739a3 [Hexagon] Misc shuffling fixes 
Co-authored-by: Brian Cain <bcain@quicinc.com>
 2022-01-07 08:27:33 -08:00
Kazu Hirata f3a344d212 [Target] Remove redundant member initialization (NFC) 
Identified with readability-redundant-member-init.
 2022-01-06 22:01:44 -08:00
Colin LeMahieu e37b6a67f8 [Hexagon] Some compound opportunities missed in presence of branches 
The lld testcase change from ddf1fb1f should take care of the build
breakage from before.
 2022-01-06 14:16:23 -08:00
Brian Cain ddf1fb1f13 [Hexagon] Save results from partial compound 
Previously compounding was all-or-nothing.  Now, the
compounding attempts will iterate and yield the most
compounds that still result in a valid packet.
 2022-01-06 14:08:33 -08:00
Nico Weber 6c255ac969 Revert "[Hexagon] Some compound opportunities missed in presence of branches" 
This reverts commit afdc6a0b8e.
Breaks check-lld, see e.g.:
https://lab.llvm.org/buildbot/#/builders/123/builds/8100/steps/8/logs/stdio
 2022-01-06 15:32:14 -05:00
Colin LeMahieu afdc6a0b8e [Hexagon] Some compound opportunities missed in presence of branches 2022-01-06 09:25:56 -08:00
Brian Cain b17f036a99 [Hexagon] Consider HVX reg aliases for .cur warning 2022-01-06 08:59:08 -08:00
Ikhlas Ajbar 2819e5de42 [Hexagon] Handle instruction selection for select(I1,Q,Q) 
Lower select(I1,Q,Q) by converting vector predicate Q to vector register V,
doing select(I1,V,V), and then converting the resulting V back to Q. Also,
try to avoid creating such situations in the first place.
 2022-01-05 14:50:12 -08:00
Ikhlas Ajbar 3892baaa71 [Hexagon] Replace isImmValidForOpcode() with isExtendable flag 2022-01-05 13:19:02 -08:00
Krzysztof Parzyszek f6309db719 [Hexagon] Handle L2_loadb[sz]w[24]_io in HII::isValidOffset 2022-01-05 13:19:02 -08:00