Commit Graph

4 Commits

Author SHA1 Message Date
Amir Ayupov 2c4e38fa6f [X86] Emit REX prefix immediately before the opcode
Fix prefix emission order to emit REX immediately before the opcode (SDM vol2,
2.1, Figure 2-1). According to SDM vol2 2.2.1, "Other placements are ignored".

This fix has a side effect of outputting segment override prefix in a different
order than previously (benign).

Follow-up to https://reviews.llvm.org/D120592

Reviewed By: skan, craig.topper

Differential Revision: https://reviews.llvm.org/D120871
2022-03-16 08:30:31 -07:00
Amir Ayupov 1d3719820f [X86] Preserve redundant Address-Size override prefix
Print and emit redundant Address-Size override prefix if it's set on the
instruction.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D120592
2022-03-16 08:30:29 -07:00
Craig Topper a0ebac52df [X86] Properly encode a 32-bit address with an index register and no base register in 16-bit mode.
In 16-bit mode we can encode a 32-bit address using 0x67 prefix.
We were failing to do this when the index register was a 32-bit
register, the base register was not present, and the displacement
fit in 16-bits.

Fixes PR46866.
2020-07-27 21:11:42 -07:00
Nirav Dave 6477ce2697 Add support for Code16GCC
[X86] The .code16gcc directive parses X86 assembly input in 32-bit mode and
outputs in 16-bit mode. Teach parser to switch modes appropriately.

Reviewers: dwmw2, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20109

llvm-svn: 282430
2016-09-26 19:33:36 +00:00