26177d2c24
Update CMake build.
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llvm-svn: 110429
2010-08-06 04:05:21 +00:00
7de9d52c13
Add the Optimize Compares pass (disabled by default).
...
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
llvm-svn: 110423
2010-08-06 01:32:48 +00:00
8a18aee421
While emitting DBG_VALUE for registers spilled at the end of a block do not use location of MBB->end(). If a block does not have terminator then incoming iterator points to end().
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llvm-svn: 110411
2010-08-06 00:26:18 +00:00
bda59bd247
Revert r110396 to fix buildbots.
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llvm-svn: 110410
2010-08-06 00:23:35 +00:00
01a81b01bc
Be more aggressive about removing joined physreg copies.
...
When a joined COPY changes subreg liveness, we keep it around as a KILL,
otherwise it is safe to delete.
llvm-svn: 110403
2010-08-05 23:51:28 +00:00
b4ef4a961d
Don't verify LiveVariables if LiveIntervals is available.
...
LiveVariables becomes horribly wrong while the coalescer is running, but the
analysis is not zapped until after the coalescer pass has run. This causes tons
of false reports when calling verify form the coalescer.
llvm-svn: 110402
2010-08-05 23:51:26 +00:00
755aceb5d0
Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
...
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
2010-08-05 23:42:04 +00:00
e7709ebb64
Add basic verification of LiveIntervals.
...
We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.
Stuff we don't check yet:
- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?
llvm-svn: 110386
2010-08-05 22:32:21 +00:00
4583355a78
Remove double-def checking from MachineVerifier, so a register does not have to
...
be killed before being redefined.
These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.
llvm-svn: 110362
2010-08-05 18:59:59 +00:00
d9572619e2
Avoid using a live std::multimap iterator while editing the map. It looks like
...
we sometimes compare singular iterators, reported by ENABLE_EXPENSIVE_CHECKS.
This fixes PR7825.
llvm-svn: 110355
2010-08-05 18:12:19 +00:00
ca1cb13646
The lower invoke pass needs to have unreachable code elimination run after it
...
because it could create such things. This fixes a MingW buildbot test failure.
llvm-svn: 110279
2010-08-04 23:36:02 +00:00
7fd4905f08
Coalesce stack slot accesses that arise when spilling both sides of a COPY.
...
This helps avoid silly code:
%R0<def = LOAD <fi#5>
STORE <fi#5>, %R0<kill>
llvm-svn: 110266
2010-08-04 22:35:11 +00:00
dc96e28d70
Checkpoint SplitKit progress.
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We are now at a point where we can split around simple single-entry, single-exit
loops, although still with some bugs.
llvm-svn: 110257
2010-08-04 22:08:39 +00:00
6c378ac473
Use location entry only of the location described by DBG_VALUE is valid.
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llvm-svn: 110255
2010-08-04 22:07:27 +00:00
b87f3e5a7d
The EH prepare passes really want to be the last passes run before code-gen.
...
llvm-svn: 110248
2010-08-04 21:44:13 +00:00
6d21f61b3f
Fix typo in comment.
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llvm-svn: 110244
2010-08-04 20:32:36 +00:00
2392287306
Change this llvm_unreachable to report_fatal_error, since it can
...
be triggered by valid, if dubious, IR.
llvm-svn: 110240
2010-08-04 18:51:09 +00:00
d71bc1ae4e
While spilling live registers at the end of block check whether they are used by DBG_VALUE machine instructions or not. If a spilled register is used by DBG_VALUE machine instruction then insert a new DBG_VALUE machine instruction to encode variable's new location on stack.
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llvm-svn: 110235
2010-08-04 18:42:02 +00:00
0e60e67efb
If a variable is spilled by code generator then use DW_OP_fbreg to describe its location on stack.
...
llvm-svn: 110234
2010-08-04 18:40:52 +00:00
5cae103392
Eliminate unnecessary empty string literals.
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llvm-svn: 110183
2010-08-04 01:39:08 +00:00
0c18757c9d
Oops. Don't normalize spill weights twice.
...
When the normalizeSpillWeights function was introduced, I forgot to remove this
normalization.
This change could affect register allocation. Hopefully for the better.
llvm-svn: 110119
2010-08-03 17:21:16 +00:00
44dc60ba13
Early exit and reduce indentation. No functionality change.
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llvm-svn: 110069
2010-08-02 22:06:08 +00:00
d070128de5
Free DbgScope created for dead functions.
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llvm-svn: 110045
2010-08-02 17:32:15 +00:00
40b31ad3ee
Prefix `next' iterator operation with `llvm::'.
...
Fixes potential ambiguity problems on VS 2010.
Patch by nobled!
llvm-svn: 110029
2010-08-02 06:00:15 +00:00
460ad41d6d
PR7586: Make sure we don't claim that unknown bits are actually known in the
...
ISD::AND case of TargetLowering::SimplifyDemandedBits.
llvm-svn: 110019
2010-08-02 04:42:25 +00:00
d9900542a6
Reference the personalities. Don't copy them into a new vector.
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llvm-svn: 109966
2010-08-01 01:34:21 +00:00
ffe64c06ef
Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly
...
check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.
llvm-svn: 109854
2010-07-30 06:44:31 +00:00
a3e0ddb564
Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ownership of the TargetAsmBackend and the MCCodeEmitter.
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llvm-svn: 109767
2010-07-29 17:48:06 +00:00
329d4741a5
Comment typo.
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llvm-svn: 109765
2010-07-29 17:45:24 +00:00
36cf119049
Fix a bug in the -regalloc=fast handling of exotic two-address instruction with
...
multiple defs, like t2LDRSB_POST.
The first def could accidentally steal the physreg that the second, tied def was
required to be allocated to.
Now, the tied use-def is treated more like an early clobber, and the physreg is
reserved before allocating the other defs.
This would never be a problem when the tied def was the only def which is the
usual case.
This fixes MallocBench/gs for thumb2 -O0.
llvm-svn: 109715
2010-07-29 00:52:19 +00:00
0ff2c110ad
Print out the regclass of any virtual registers used by a machine instruction.
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llvm-svn: 109608
2010-07-28 18:35:46 +00:00
84a74779a1
It is FE's responsibility to emit proper directory name.
...
llvm-svn: 109538
2010-07-27 20:51:15 +00:00
7383cf06ba
Grammar
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llvm-svn: 109525
2010-07-27 18:36:27 +00:00
317b969ac5
Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
...
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.
llvm-svn: 109519
2010-07-27 18:02:18 +00:00
2ff0e64bc3
80 column
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llvm-svn: 109513
2010-07-27 17:38:47 +00:00
7639967e6c
fix typo
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llvm-svn: 109511
2010-07-27 17:14:29 +00:00
0ff1ef650b
It's better to have the arrays, which would trigger the creation of stack
...
protectors, to be near the stack protectors on the stack. Accomplish this by
tagging the stack object with a predicate that indicates that it would trigger
this. In the prolog-epilog inserter, assign these objects to the stack after the
stack protector but before the other objects.
llvm-svn: 109481
2010-07-27 01:55:19 +00:00
c698417e52
Add SplitEditor to SplitKit. This class will be used to edit live intervals and
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rewrite instructions for live range splitting.
Still work in progress.
llvm-svn: 109469
2010-07-26 23:44:11 +00:00
c2af77f510
Fix a use-after-free.
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llvm-svn: 109468
2010-07-26 23:40:24 +00:00
fa60b0ee51
Using llvm.eh.catch.all.value instead of .llvm.eh.catch.all.value.
...
llvm-svn: 109462
2010-07-26 22:36:52 +00:00
e6d6c5dd11
The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.
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llvm-svn: 109449
2010-07-26 21:49:07 +00:00
2810bacafb
Handle Values with no value in getCopyFromRegs.
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llvm-svn: 109415
2010-07-26 18:15:41 +00:00
f9da3c3b88
A block dominates itself, by definition.
...
llvm-svn: 109402
2010-07-26 17:38:15 +00:00
136a6f0dbb
Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parameter)
...
may be used uninitialized in the callers of HighRegPressure.
llvm-svn: 109393
2010-07-26 07:54:17 +00:00
2e3f20b9aa
Factored out a bit of common code to mark VNInfos for deletion.
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llvm-svn: 109388
2010-07-26 01:49:41 +00:00
8ae3ecad2b
Add comments.
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llvm-svn: 109383
2010-07-25 18:59:43 +00:00
280ce9984e
Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts on
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those. Radar 8231572.
llvm-svn: 109367
2010-07-25 05:34:27 +00:00
3c8eb80d93
Add hook to insert late LLVM=>LLVM passes just before isel
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llvm-svn: 109354
2010-07-24 20:48:54 +00:00
56c006561c
Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors
...
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K
won't cause a compile time performance regression.
llvm-svn: 109330
2010-07-24 06:01:53 +00:00
498877d055
Use current working directory when Dirname is empty. This only happens when absolute source file path is used on compiler command line.
...
llvm-svn: 109302
2010-07-24 00:53:22 +00:00
37b740c4bf
Add an ILP scheduler. This is a register pressure aware scheduler that's
...
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
llvm-svn: 109300
2010-07-24 00:39:05 +00:00
ba4b1909ce
Remove too-strict assertion. We may want the vreg copy of the physical register
...
to be of a different register class. For example, in Thumb1 if the live-in is
a high register, we want the vreg to be a low register. rdar://8224931
llvm-svn: 109291
2010-07-23 23:48:02 +00:00
28499f76c9
Revert r109262.
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llvm-svn: 109285
2010-07-23 23:04:41 +00:00
df907f4594
- Allow target to specify when is register pressure "too high". In most cases,
...
it's too late to start backing off aggressive latency scheduling when most
of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
For ARM, this is almost always a win on # of instructions. It's runtime
neutral for most of the tests. But for some kernels with high register
pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
54 and sped up by 20%.
llvm-svn: 109279
2010-07-23 22:39:59 +00:00
55e244698a
Use the proper type for shift counts. This fixes a bootstrap error.
...
llvm-svn: 109265
2010-07-23 21:08:12 +00:00
3032354bbe
IF directory name is empty then try to extract one using absolute file name.
...
llvm-svn: 109262
2010-07-23 20:36:13 +00:00
0818684a70
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
...
are not demanded. This often allows the anyext to be folded away.
llvm-svn: 109242
2010-07-23 18:03:30 +00:00
2e00e3b12d
Make SDNode::dump() print a newline at the end.
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llvm-svn: 109234
2010-07-23 16:37:47 +00:00
faf5c76114
80-col.
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llvm-svn: 109205
2010-07-23 01:05:59 +00:00
8f3adc9057
remove the JIT "NeedsExactSize" feature and supporting logic.
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llvm-svn: 109167
2010-07-22 21:17:55 +00:00
59f9970ba5
keep in 80 cols
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llvm-svn: 109122
2010-07-22 17:18:03 +00:00
dde79d8f1a
mass elimination of reliance on automatic iterator dereferencing
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llvm-svn: 109103
2010-07-22 13:36:47 +00:00
3e44ea1917
undo 80 column trespassing I caused
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llvm-svn: 109092
2010-07-22 10:37:47 +00:00
bf32e54bac
Re-apply r109079 with fix.
...
llvm-svn: 109083
2010-07-22 06:24:48 +00:00
6c55cccf87
Revert r109079, which broke a lot of CodeGen tests.
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llvm-svn: 109082
2010-07-22 06:01:28 +00:00
d85e3c5a86
Initial modifications to MCAssembler and TargetMachine for the MCJIT.
...
Patch by Olivier Meurant!
llvm-svn: 109080
2010-07-22 05:58:53 +00:00
bd81bff672
Initialize RegLimit only when register pressure is being tracked.
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llvm-svn: 109079
2010-07-22 05:18:41 +00:00
285903853f
More register pressure aware scheduling work.
...
llvm-svn: 109064
2010-07-21 23:53:58 +00:00
965a73a28c
For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
...
rdar://8202967
llvm-svn: 109057
2010-07-21 23:03:52 +00:00
a57b97e7e7
Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
...
llvm-svn: 109045
2010-07-21 22:09:45 +00:00
a8683bb033
80 column and trailing whitespace cleanup
...
llvm-svn: 109037
2010-07-21 21:21:52 +00:00
093cb79d4b
Disallow null as a named metadata operand.
...
Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.
One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).
llvm-svn: 109028
2010-07-21 18:54:18 +00:00
bdafcc633d
Changed OStream templates to functions on raw_ostream, removed the unused "renderWarnings" function.
...
llvm-svn: 109003
2010-07-21 09:02:06 +00:00
a77f3d3b37
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
...
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
0fef9dda8e
Change the createSpiller interface to take a MachineFunctionPass argument.
...
The spillers can pluck the analyses they need from the pass reference.
Switch some never-null pointers to references.
llvm-svn: 108969
2010-07-20 23:50:15 +00:00
ed4075cc3b
Implement loop splitting analysis.
...
Determine which loop exit blocks need a 'pre-exit' block inserted.
Recognize when this would be impossible.
llvm-svn: 108941
2010-07-20 21:46:58 +00:00
6e5ec6263e
Fix test for switch statements and increase
...
threshold a bit per experimentation.
llvm-svn: 108935
2010-07-20 21:29:12 +00:00
ff095507e3
Appease the colonials.
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llvm-svn: 108845
2010-07-20 16:12:37 +00:00
36d12c679d
Beginning SplitKit - utility classes for live range splitting.
...
This is a work in progress. So far we have some basic loop analysis to help
determine where it is useful to split a live range around a loop.
The actual loop splitting code from Splitter.cpp is also going to move in here.
llvm-svn: 108842
2010-07-20 15:41:07 +00:00
31dfb75b52
Updated css classes for the pressure table legend.
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llvm-svn: 108839
2010-07-20 14:35:55 +00:00
2ff2193a80
Oops - I tables render poorly in Chrome without this explicit height specification.
...
llvm-svn: 108824
2010-07-20 10:29:46 +00:00
a475ab7f02
Use run-length encoding to represent identical adjacent cells in the pressure
...
and interval table. Reduces output HTML file sizes by ~80% in my test cases.
Also fix access of private member type by << operator.
llvm-svn: 108823
2010-07-20 10:18:54 +00:00
716b184108
Added support for turning HTML indentation on and off (indentation off by default).
...
Reduces output file size ~20% on my test cases.
llvm-svn: 108822
2010-07-20 09:13:29 +00:00
a93fe2de3c
Switched to rendering after allocation (but before rewriting) in PBQP.
...
Updated renderer to use allocation information from VirtRegMap (if
available) to render spilled intervals differently.
llvm-svn: 108815
2010-07-20 07:41:44 +00:00
08645f1991
Don't hoist things out of a large switch inside a
...
loop, for the reasons in the comments. This is a
major win on 253.perlbmk on ARM Darwin. I expect it
to be a good heuristic in general, but it's possible
some things will regress; I'll be watching.
7940152
2010-07-20 00:50:13 +00:00
61475c5c3c
Correct line info for declarations/definitions. Radar 8063111.
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llvm-svn: 108784
2010-07-19 23:56:30 +00:00
d61b735d25
Fix memory leak reported by valgrind.
...
Do not visit operands of old instruction. Visit all operands of new instruction.
llvm-svn: 108767
2010-07-19 23:25:39 +00:00
b5e918dc05
After a custom inserter, in a block which has constant instructions,
...
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.
llvm-svn: 108765
2010-07-19 22:48:56 +00:00
10f99a3490
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
...
llvm-svn: 108761
2010-07-19 22:15:08 +00:00
7a135510e3
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
...
This property will be used by the register pressure tracking instruction scheduler.
llvm-svn: 108735
2010-07-19 18:47:01 +00:00
a58a7e7f9e
Spillers may alter MachineLoopInfo when breaking critical edges, so make it
...
non-const.
llvm-svn: 108734
2010-07-19 18:41:20 +00:00
18efced1a2
Fix PR 7662.
...
Do not try to insert local variable info to a DIE used for function declaration.
llvm-svn: 108731
2010-07-19 17:53:55 +00:00
58c283ee85
Update CMake build.
...
llvm-svn: 108700
2010-07-19 15:37:03 +00:00
6624efb711
Render MachineFunctions to HTML pages, with options to render register
...
pressure estimates and liveness alongside.
Still experimental.
llvm-svn: 108698
2010-07-19 15:22:28 +00:00
9c271e2835
Remove r108639 now that it is handled by InstCombine instead.
...
llvm-svn: 108688
2010-07-19 08:10:24 +00:00
419197cc4d
Target: Give the TargetAsmParser access to the TargetMachine.
...
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
llvm-svn: 108664
2010-07-19 00:33:49 +00:00
7f5bf5ae2a
MC: Move several clients to using AsmParser constructor function.
...
llvm-svn: 108645
2010-07-18 18:31:33 +00:00
8ff89f5c02
Fix struct/class mismatch
...
llvm-svn: 108642
2010-07-18 11:47:56 +00:00
f7f9c8a2f7
Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
...
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.
This fixed <rdar://problem/8197504>.
llvm-svn: 108639
2010-07-18 08:47:54 +00:00
1392b8eb79
Added -pbqp-pre-coalescing flag to PBQP. If enabled this will cause PBQP to require
...
LoopSplitter be run prior to register allocation.
Entirely for testing purposes at the moment.
llvm-svn: 108634
2010-07-18 00:57:59 +00:00
Ted Kremenek