337e8db712
Add support for the x86 instructions "pusha" and "popa".
...
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
d24c66b4a3
Do not do tail calls to external symbols. If the
...
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
llvm-svn: 106662
2010-06-23 18:52:34 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
6f71039fa4
The generic DAG combiner can now fold atomic fences when needed, so switch
...
to using that.
llvm-svn: 106633
2010-06-23 16:25:07 +00:00
a8ea498171
When using libcall expansions for the atomic intrinsics, the explicit
...
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
llvm-svn: 106631
2010-06-23 16:08:49 +00:00
3d6e2c6335
Update uses, defs, and comments for darwin tls patterns.
...
llvm-svn: 106621
2010-06-23 08:01:49 +00:00
ef5a4383ad
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
...
Conflicts:
lib/CodeGen/MachineSink.cpp
llvm-svn: 106614
2010-06-23 00:48:25 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
535aa8ea91
Reapply support for AVX unpack and interleave instructions, with
...
testcases this time.
llvm-svn: 106593
2010-06-22 23:02:38 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
...
llvm-svn: 106588
2010-06-22 22:38:56 +00:00
8ce69cd95a
Fix the formatting of the switch statement and add a missing break.
...
llvm-svn: 106586
2010-06-22 22:16:17 +00:00
c5d712232d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
...
Radar 8031193.
llvm-svn: 106582
2010-06-22 22:04:24 +00:00
6c275bc5a2
fix typo
...
llvm-svn: 106574
2010-06-22 20:52:02 +00:00
3af915f84b
Reorganize logical and arithmetic SSE 1 & 2 instructions
...
llvm-svn: 106557
2010-06-22 18:17:40 +00:00
b91af24d3e
Reorganize SSE instructions, making easier to see oportunities for refactoring
...
llvm-svn: 106556
2010-06-22 18:09:32 +00:00
d2d1ae105d
Use pre-increment instead of post-increment when the result is not used.
...
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
37bb617f8a
Tail merging pass shall not break up IT blocks. rdar://8115404
...
llvm-svn: 106517
2010-06-22 01:18:16 +00:00
60bb7c42a7
make sure to initialize indent_level
...
llvm-svn: 106513
2010-06-22 00:40:26 +00:00
64960f55fe
add some support for blockaddress. This isn't really enough to be useful,
...
but it will cover uses of blockaddress that are actually in a function.
llvm-svn: 106502
2010-06-21 23:19:36 +00:00
bb45b964f8
eliminate a mutable global variable, use raw_ostream::indent instead of
...
rolling our own.
llvm-svn: 106501
2010-06-21 23:14:47 +00:00
a0b8c90870
un-indent a huge amount of code out of an anonymous namespace.
...
llvm-svn: 106500
2010-06-21 23:12:56 +00:00
b7dadb0e95
revert r106482
...
llvm-svn: 106499
2010-06-21 22:59:03 +00:00
510d9a3404
change parameter name to avoid confusion with global definition
...
llvm-svn: 106486
2010-06-21 21:28:07 +00:00
72df24037e
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
...
Radar 8104310.
llvm-svn: 106484
2010-06-21 21:27:34 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
374b2195f6
Add unpack and interleave AVX instructions, encoding tests cooming soon
...
llvm-svn: 106482
2010-06-21 21:21:48 +00:00
1fb4de8ec5
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
...
llvm-svn: 106481
2010-06-21 21:21:14 +00:00
6dd51a2bb6
Remove isTwoAddress from SystemZ.
...
llvm-svn: 106467
2010-06-21 20:25:57 +00:00
d7a7356be6
Remove isTwoAddress from Sparc.
...
llvm-svn: 106466
2010-06-21 20:22:35 +00:00
c7927f2013
Remove isTwoAddress from Mips.
...
llvm-svn: 106465
2010-06-21 20:19:21 +00:00
fb008dfa05
Remove isTwoAddress from Blackfin.
...
llvm-svn: 106457
2010-06-21 20:13:37 +00:00
fa1b54d26e
Remove isTwoAddress from MSP430.
...
llvm-svn: 106455
2010-06-21 20:07:30 +00:00
0ca648d758
Make 80-column.
...
llvm-svn: 106448
2010-06-21 18:56:55 +00:00
98392f69e3
Remove isTwoAddress from PIC16.
...
llvm-svn: 106447
2010-06-21 18:55:01 +00:00
2401271217
Remove isTwoAddress from XCore.
...
llvm-svn: 106446
2010-06-21 18:51:38 +00:00
e159407231
Remove isTwoAddress from Alpha.
...
llvm-svn: 106445
2010-06-21 18:48:55 +00:00
29a894dd64
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
...
llvm-svn: 106437
2010-06-21 18:36:04 +00:00
20de4258f8
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
...
llvm-svn: 106436
2010-06-21 18:22:54 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
...
handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
bf572c7cea
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
...
Based on a patch by Patrick Marlier!
llvm-svn: 106433
2010-06-21 18:21:27 +00:00
97c8a6a928
early exit for dbg_value instructions
...
llvm-svn: 106430
2010-06-21 17:49:23 +00:00
74b5e3e0ae
remove some dead variables reported by clang++
...
llvm-svn: 106428
2010-06-21 17:20:18 +00:00
0ab5a02579
Mark the SPU 'lr' instruction to never have side effects.
...
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
2010-06-21 15:08:16 +00:00
d7f50c118a
Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
...
llvm-svn: 106419
2010-06-21 14:42:19 +00:00
1cae86f704
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
...
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
llvm-svn: 106413
2010-06-21 13:31:32 +00:00
6f58190f6f
Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
...
used to choke llc with the attached test.
llvm-svn: 106411
2010-06-21 10:17:36 +00:00
c596baa56d
wip
...
llvm-svn: 106408
2010-06-21 02:17:34 +00:00
dcc7b6dcb6
Fix warning in no-asserts build.
...
llvm-svn: 106405
2010-06-20 20:27:42 +00:00
884a8fe5fa
Fix a crash caused by dereference of MBB.end(). rdar://8110842
...
llvm-svn: 106399
2010-06-20 00:54:38 +00:00
6d12973143
Remove a fixme comment that is no longer relevant.
...
llvm-svn: 106382
2010-06-19 05:32:41 +00:00
0ae08935f6
Fix error message to match function name.
...
llvm-svn: 106381
2010-06-19 05:32:09 +00:00
b86a3abcc7
Refactoring of regular logical packed instructions to prepare for AVX ones.
...
llvm-svn: 106375
2010-06-19 04:09:22 +00:00
8737b7d73d
Refactor aliased packed logical instructions, also add
...
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
llvm-svn: 106374
2010-06-19 02:44:01 +00:00
7079bf815d
Ignore dbg_value's.
...
llvm-svn: 106373
2010-06-19 02:36:21 +00:00
a588049ce9
Move new sse 1 & 2 generic classes to a more appropriate place
...
llvm-svn: 106372
2010-06-19 01:32:46 +00:00
2787efd961
Remove unnecessary arguments
...
llvm-svn: 106371
2010-06-19 01:22:34 +00:00
00ada89f95
Add AVX packed intrinsics for MIN, MAX
...
llvm-svn: 106370
2010-06-19 01:17:05 +00:00
f3c01f3ef6
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
...
llvm-svn: 106368
2010-06-19 01:01:32 +00:00
42105b2976
Finish ripping isTwoAddress out of X86. Some mindless formatting
...
and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
llvm-svn: 106367
2010-06-19 00:37:40 +00:00
1e205f6b1c
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
...
llvm-svn: 106366
2010-06-19 00:37:31 +00:00
c60cecd88b
rip out dead code.
...
llvm-svn: 106365
2010-06-19 00:34:14 +00:00
e808a78ac1
fix rdar://7873482 by teaching the instruction encoder to emit
...
segment prefixes. Daniel wrote most of this patch.
llvm-svn: 106364
2010-06-19 00:34:00 +00:00
e5fcd333da
Indentation and remove dead code.
...
llvm-svn: 106362
2010-06-19 00:11:54 +00:00
1888f11887
Clean up: remove now unnecessary Constraints
...
llvm-svn: 106361
2010-06-19 00:09:27 +00:00
5fc43eb186
Silence compiler warnings.
...
llvm-svn: 106360
2010-06-19 00:02:06 +00:00
502c4fe61c
more refactoring! yay! big win over the intrinsics
...
llvm-svn: 106359
2010-06-19 00:00:22 +00:00
6bdbdb5544
Remove isTwoAddress from here too.
...
llvm-svn: 106358
2010-06-18 23:56:07 +00:00
66d2d57d9b
Fix typo, SSE1 should be used by XS, not SSE2
...
llvm-svn: 106357
2010-06-18 23:53:27 +00:00
3577c1b811
Remove isTwoAddress from 64-bit files.
...
llvm-svn: 106356
2010-06-18 23:51:21 +00:00
119824ed4d
Move ARM if-conversion before post-ra scheduling.
...
llvm-svn: 106355
2010-06-18 23:32:07 +00:00
8693650422
Teach regular and fast isel to set dead flags on unused implicit defs
...
on calls and similar instructions.
llvm-svn: 106353
2010-06-18 23:28:01 +00:00
2bfad417a1
Apply some refactor to packed instructions
...
llvm-svn: 106349
2010-06-18 23:13:35 +00:00
4f0781c9b3
Update cmake list.
...
llvm-svn: 106348
2010-06-18 23:12:10 +00:00
285935939d
Thumb2 hazard recognizer.
...
llvm-svn: 106347
2010-06-18 23:11:35 +00:00
2d51c7c592
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
2010-06-18 23:09:54 +00:00
a57c2885cf
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
...
llvm-svn: 106342
2010-06-18 23:03:10 +00:00
6860bb7796
Enable Expand handling of atomics for subtargets that can't do them inline.
...
llvm-svn: 106336
2010-06-18 22:35:32 +00:00
871439abd2
Use the new 'defm' class inheritance in SSE
...
llvm-svn: 106327
2010-06-18 22:10:11 +00:00
a92e41a50a
Rewrite chained if's as switches and replace assertions with llvm_unreachable
...
(as suggested in radar 8104405).
llvm-svn: 106318
2010-06-18 21:32:42 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
...
llvm-svn: 106314
2010-06-18 21:07:47 +00:00
22a212f97c
When using ADDri to get the address of a stack object, 255 is a conservative
...
limit on the offset that can be materialized without using the register
scavenger.
llvm-svn: 106312
2010-06-18 20:59:25 +00:00
a46d607545
Make this comment less specific.
...
llvm-svn: 106311
2010-06-18 20:45:41 +00:00
af4903d6ee
Fix X86FastISel's address-mode folding to stay within the
...
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.
llvm-svn: 106310
2010-06-18 20:44:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
...
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
c1570dda5c
Enable tail calls on ARM by default, with some
...
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
llvm-svn: 106299
2010-06-18 19:00:18 +00:00
882bb2984e
Start TargetRegisterClass indices at 0 instead of 1, so that
...
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
llvm-svn: 106296
2010-06-18 18:13:55 +00:00
3ac52b3e43
Last round of changes for ARM tail calls.
...
Not turning them on yet.
llvm-svn: 106295
2010-06-18 18:13:11 +00:00
b9f91667e1
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
...
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
llvm-svn: 106289
2010-06-18 16:49:33 +00:00
92c11acdb8
Change UpdateNodeOperands' operand and return value from SDValue to
...
SDNode *, since it doesn't care about the ResNo value.
llvm-svn: 106282
2010-06-18 15:30:29 +00:00
c3479f5342
Delete unused variables.
...
llvm-svn: 106280
2010-06-18 14:32:32 +00:00
f1d8304fe3
Eliminate unnecessary uses of getZExtValue().
...
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
35b6f9a929
isValueValidForType can be a static member function.
...
llvm-svn: 106278
2010-06-18 14:01:07 +00:00
67d25f91c5
Some assorted isTwoAddress -> Constraints cleanup.
...
llvm-svn: 106273
2010-06-18 02:41:19 +00:00
99ba4dac59
Don't maintain a set of deleted nodes; instead, use a HandleSDNode
...
to track a node over CSE events. This fixes PR7368.
llvm-svn: 106266
2010-06-18 01:24:29 +00:00
2323168705
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
...
llvm-svn: 106264
2010-06-18 01:12:56 +00:00
b92156d5e4
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
...
which is faster, simpler, and less surprising.
llvm-svn: 106263
2010-06-18 01:05:21 +00:00
6b98f7129f
Use new tablegen resources in SSE tablegen code. This will
...
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
llvm-svn: 106251
2010-06-17 23:05:30 +00:00
0125b6410a
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
...
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
2010-06-17 22:43:56 +00:00
5712c77c89
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
...
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
llvm-svn: 106204
2010-06-17 02:02:03 +00:00
6e758c97fd
simplify code a bit and add a more explanatory assert for cases that
...
previously would result in 'cannot yet select' errors.
llvm-svn: 106199
2010-06-17 01:37:00 +00:00
29b58afdf1
Hack to let the move lowering handle dynamic-no-pic absolute moves of
...
TLVP:
movl _a@TLVP, %eax
Daniel: Please review if you get a chance.
llvm-svn: 106194
2010-06-17 00:51:48 +00:00
e3864cc15e
format and 80-column cleanup
...
llvm-svn: 106173
2010-06-16 23:45:49 +00:00
2334144e6e
Don't attempt preserving conservative kill flags. We were doing it wrong.
...
This is before LiveVariables anyway, where these kill flags are recalculated.
llvm-svn: 106157
2010-06-16 22:11:08 +00:00
01ac8f9fc0
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
...
now, so there's no need to disable them.
llvm-svn: 106155
2010-06-16 21:34:01 +00:00
41476410c9
TODO--
...
llvm-svn: 106102
2010-06-16 15:47:00 +00:00
f128bdcb55
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
...
llvm-svn: 106091
2010-06-16 07:35:02 +00:00
8c0cf0994d
Create a more targeted fix for not sinking instructions into a range where it
...
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.
llvm-svn: 106066
2010-06-15 23:46:31 +00:00
6c4d63e1a5
For 32-bit non-pic tlv mach-o addressing we don't need a pic base or
...
a relative address.
llvm-svn: 106064
2010-06-15 23:08:42 +00:00
438c35b5d1
Add file missing from previous commit.
...
llvm-svn: 106058
2010-06-15 22:24:08 +00:00
44f9dfc9cf
Next round of tail call changes. Register used in a tail
...
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
llvm-svn: 106053
2010-06-15 22:08:33 +00:00
89456b2612
Reapply 105986 with fix for bug pointed out by Jakob:
...
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info. I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.
llvm-svn: 106049
2010-06-15 21:36:43 +00:00
874c92bd47
fix fastisel to handle GS and FS relative pointers. Patch by
...
Nelson Elhage!
llvm-svn: 106031
2010-06-15 19:08:40 +00:00
f3f7a770b7
Add basic support for NEON modified immediates besides VMOV.
...
llvm-svn: 106030
2010-06-15 19:05:35 +00:00
0904134252
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
...
llvm-svn: 105994
2010-06-15 14:50:42 +00:00
1478142485
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
...
llvm-svn: 105990
2010-06-15 05:51:27 +00:00
3f253d2353
Revert 105986; looks like I'd better try bootstrapping.
...
llvm-svn: 105988
2010-06-15 04:55:06 +00:00
c338ef2b65
The form of BuildMI used for TAILJMPr was changing the register
...
containing the target address, an input, into an output. I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.
llvm-svn: 105986
2010-06-15 03:13:49 +00:00
f14e08b01b
Make sure to skip dbg_value instructions when finding an insertion point for
...
the combined load/store instruction. rdar://7797940
llvm-svn: 105982
2010-06-15 00:41:09 +00:00
5b2b504038
Rename functions referring to VMOV immediates to refer to NEON "modified
...
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
llvm-svn: 105969
2010-06-14 22:19:57 +00:00
faa7bdccbf
fix a nasty bug where we were not treating available_externally
...
symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
llvm-svn: 105954
2010-06-14 20:11:56 +00:00
58c09b2859
fix a -Wbool-conversions warning from clang.
...
llvm-svn: 105943
2010-06-14 18:28:57 +00:00
ba1f1fcae5
Add back some possible optimizations for va_arg, with wording that makes it
...
more clear what exactly is missing.
llvm-svn: 105934
2010-06-14 07:03:30 +00:00
e302f833e1
Merge getStoreRegOpcode and getLoadRegOpcode.
...
llvm-svn: 105900
2010-06-12 20:13:29 +00:00
e17e4aea2a
Add README entry; based on testcase from Bill Hart.
...
llvm-svn: 105878
2010-06-12 05:54:27 +00:00
ada854f8b6
make the avx intrinsics 3 address
...
llvm-svn: 105876
2010-06-12 03:12:14 +00:00
f203703467
Add some basic fp intrinsics for AVX
...
llvm-svn: 105873
2010-06-12 02:38:32 +00:00
a714ea0f7d
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
...
llvm-svn: 105870
2010-06-12 01:53:48 +00:00
b06f54b852
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
...
Handle OpSize TSFlag for AVX
llvm-svn: 105869
2010-06-12 01:23:26 +00:00
8947c32493
Add some comments about REX fields
...
llvm-svn: 105860
2010-06-12 00:03:52 +00:00
fd5458d4bd
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
...
Introduce the VEX_X field
llvm-svn: 105859
2010-06-11 23:50:47 +00:00
f07d33d8f1
Add a missing bitcast. This code used to only handle conversions between
...
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
llvm-svn: 105845
2010-06-11 22:45:25 +00:00
6eae520de9
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
llvm-svn: 105836
2010-06-11 21:34:50 +00:00
2901371c32
Delete code that's not safe.
...
llvm-svn: 105774
2010-06-10 02:08:20 +00:00
5fa0158ecd
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
...
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
llvm-svn: 105758
2010-06-09 22:21:24 +00:00
a0746bd50a
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
...
llvm-svn: 105745
2010-06-09 19:26:01 +00:00
5e0862f7f5
Fix SPU to cope with vector insertelement to an undef position.
...
We default to inserting to lane 0.
llvm-svn: 105722
2010-06-09 09:58:17 +00:00
056113a211
Handle loading from/storing to undef pointers on SPU by inserting a
...
random load/store, rather than crashing llc.
llvm-svn: 105710
2010-06-09 08:29:41 +00:00
83c64ee8de
Typo.
...
llvm-svn: 105677
2010-06-09 03:49:12 +00:00
ab44d1281a
A few new x86-64 specific README entries.
...
llvm-svn: 105674
2010-06-09 02:43:17 +00:00
47cd593023
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
...
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
llvm-svn: 105669
2010-06-09 01:46:50 +00:00
0de0f3fc02
Incremental improvement to the handling of the x86 "Jump if rCX Zero"
...
instruction. Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode. Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.
llvm-svn: 105661
2010-06-08 23:48:44 +00:00
6ab55c5683
Split out these asserts so it's more apparent why we're not assembling
...
that rip-relative address when executing in 32-bit mode.
llvm-svn: 105656
2010-06-08 22:57:33 +00:00
8fe3cc8055
fix copy/paste/modify think-o
...
llvm-svn: 105653
2010-06-08 22:53:32 +00:00
c2f87b7bb2
Reapply r105521, this time appending "LLU" to 64 bit
...
immediates to avoid breaking the build.
llvm-svn: 105652
2010-06-08 22:51:23 +00:00
89d103a8ce
Ensure that mov and not lea are used to stick the address into
...
the register. While we're at it, make sure it's in the right one.
llvm-svn: 105645
2010-06-08 22:04:25 +00:00
57c6fd452e
fix typo
...
llvm-svn: 105634
2010-06-08 20:06:55 +00:00
6c40caf729
Flag SPU's function call sequence together.
...
Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html
llvm-svn: 105601
2010-06-08 07:55:16 +00:00
0271c5928e
Fix up a comment.
...
llvm-svn: 105591
2010-06-08 00:42:08 +00:00
846bd7992c
Further changes for Neon vector shuffles:
...
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
llvm-svn: 105586
2010-06-07 23:53:38 +00:00
723d242a95
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
...
rdar://7797940
llvm-svn: 105557
2010-06-07 21:48:47 +00:00
a3bba3371a
Create new accessors to get arguments for call/invoke instructions. It breaks
...
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.
llvm-svn: 105539
2010-06-07 19:05:06 +00:00
e4f45cc88f
This bug is also present in MSVC10. Requested by Elrood on IRC.
...
llvm-svn: 105527
2010-06-05 12:40:43 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
...
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
...
yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
81ef35b3ca
Improvements to tail call code. No functional effect
...
unless using -arm-tail-calls.
llvm-svn: 105515
2010-06-05 00:51:39 +00:00
df1a7f83bf
Fix some liveout handling related to tail calls, see comments.
...
I don't think this ever resulted in problems on x86, but it
would on ARM.
llvm-svn: 105509
2010-06-05 00:30:45 +00:00
d1b9311afa
More thoroughly disable tails calls by default.
...
8060143, although this doesn't fix the real problem with tail call.
llvm-svn: 105472
2010-06-04 18:04:24 +00:00
3548803f62
Another fix to prevent debug info from affecting codegen. rdar://7797940
...
llvm-svn: 105470
2010-06-04 17:57:34 +00:00
4e5e6a8973
more dbg_value adjustments so debug info doesn't affect codegen
...
llvm-svn: 105454
2010-06-04 01:23:30 +00:00
1bcdf32d22
fix typo
...
llvm-svn: 105441
2010-06-04 00:15:00 +00:00
d8a9a04739
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
...
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
llvm-svn: 105439
2010-06-04 00:04:02 +00:00
b30b81edb6
Teach the ARM load-store optimizer to deal with dbg_value instructions.
...
llvm-svn: 105427
2010-06-03 22:41:15 +00:00
d679ff7330
Early implementation of tail call for ARM.
...
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
b0e1a458ce
Add first pass at darwin tls compiler support.
...
llvm-svn: 105381
2010-06-03 04:07:48 +00:00
ceb13f2af3
Remove some already-fixed README entries.
...
llvm-svn: 105377
2010-06-03 01:47:31 +00:00
a59b7a72b9
Remove README entry which no longer compiles to something sane.
...
llvm-svn: 105376
2010-06-03 01:16:51 +00:00
1f41303260
Remove a fixed item, update a couple partially-fixed items.
...
llvm-svn: 105375
2010-06-03 01:01:48 +00:00
a8ad97743d
Slightly change the meaning of the reMaterialize target hook when the original
...
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
llvm-svn: 105358
2010-06-02 22:47:25 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
f2dffcef82
Remove the TargetRegisterClass member from CalleeSavedInfo
...
llvm-svn: 105344
2010-06-02 20:02:30 +00:00
6e3d5af945
Fix comment so it doesn't include comments which are irrelevant to the x86
...
backend. Add a FIXME noting what can be fixed here.
llvm-svn: 105342
2010-06-02 19:35:46 +00:00
a690618c58
Use comments to document non-obvious code rather than
...
mailing list archives.
llvm-svn: 105341
2010-06-02 19:13:40 +00:00
2d35a9e810
Rename canCombinedSubRegIndex method to something more grammatically correct
...
and tidy up the comment describing it.
llvm-svn: 105339
2010-06-02 18:54:47 +00:00
94801a47f8
Replace ARM's getCalleeSavedRegClasses with a simpler solution
...
llvm-svn: 105335
2010-06-02 17:54:50 +00:00
7881a64a50
Remove unused function.
...
llvm-svn: 105325
2010-06-02 15:44:20 +00:00
ef2b6ce00a
cleanup
...
llvm-svn: 105322
2010-06-02 13:53:17 +00:00
c08ecba597
Remove uses of getCalleeSavedRegClasses from outside the
...
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
llvm-svn: 105321
2010-06-02 12:39:06 +00:00
526e6d045f
Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
...
x86 backend currently doesn't know how to handle them.
This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either. We do get a better error message, though.
llvm-svn: 105305
2010-06-02 00:27:18 +00:00
6382c9c681
Remove outdated README entries.
...
llvm-svn: 105303
2010-06-02 00:10:36 +00:00
47a0724425
Fix the allocation of shadow space for the Win64 calling convention
...
in X86FastISel. Patch by Jan Sjodin.
llvm-svn: 105290
2010-06-01 21:09:47 +00:00
d44677ba69
Refactor some SSE 2 unpack instructions
...
llvm-svn: 105276
2010-06-01 17:02:50 +00:00
8916358f97
Fix handling of 'load' nodes.
...
llvm-svn: 105269
2010-06-01 13:34:47 +00:00
a09d95412e
Some A9 load/store cleanups
...
llvm-svn: 105109
2010-05-29 19:25:39 +00:00
2a21aef8f2
Some rough approximations for load/stores on A9
...
llvm-svn: 105108
2010-05-29 19:25:34 +00:00
d4c7cceb70
NEON/VFP stuff can be issued only via Pipe1 on A9
...
llvm-svn: 105107
2010-05-29 19:25:29 +00:00
94d7fd88fd
Add some integer instruction itineraries for A9
...
llvm-svn: 105106
2010-05-29 19:25:17 +00:00
27c4933e02
Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
...
llvm-svn: 105092
2010-05-29 01:35:22 +00:00
e02996ca8f
Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
...
were overspecified when inheriting sub-subregisters, for instance:
R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.
This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.
llvm-svn: 105063
2010-05-28 23:48:29 +00:00
bf91499f1a
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
...
llvm-svn: 105060
2010-05-28 23:25:23 +00:00
e8be73f3e7
Fix comment typos.
...
llvm-svn: 105059
2010-05-28 23:24:28 +00:00
1f79289806
More SSE 1 & 2 merge, this time with logical instructions
...
llvm-svn: 105014
2010-05-28 22:47:03 +00:00
4c71e08ed8
MC/X86: Add alias for movzx.
...
llvm-svn: 105005
2010-05-28 21:20:21 +00:00
b29228905f
MC/X86: Add alias for fwait.
...
llvm-svn: 105001
2010-05-28 20:59:10 +00:00
76413597a9
Fix the use of x86 control and debug registers so that the assertion failure in
...
getX86RegNum() does not happen. Patch by Shantonu Sen!
llvm-svn: 104994
2010-05-28 19:01:27 +00:00
b342e09b5e
correct retattr
...
llvm-svn: 104980
2010-05-28 18:03:48 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
...
llvm-svn: 104974
2010-05-28 17:51:20 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
...
llvm-svn: 104967
2010-05-28 17:37:40 +00:00
b6112e8706
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
...
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
llvm-svn: 104907
2010-05-28 00:27:15 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c2ebe0334a
Use report_fatal_error, not llvm_unreachable.
...
llvm-svn: 104899
2010-05-27 23:45:31 +00:00
c9f532dddc
back out 104862/104869. Can reuse stacksave after all. Very cool.
...
llvm-svn: 104897
2010-05-27 23:11:57 +00:00
3d3ee87d4e
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
...
llvm-svn: 104891
2010-05-27 22:08:38 +00:00
9738f64bd9
MC/X86: Add aliases for Jcc variants.
...
llvm-svn: 104890
2010-05-27 21:33:19 +00:00
40e62dfdc0
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
...
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
llvm-svn: 104883
2010-05-27 20:23:42 +00:00
9e43c07bc5
Mark some math lib intrinsic nodes Legal on SSE4.1.
...
No functional effect as these nodes are not generated yet.
llvm-svn: 104879
2010-05-27 20:12:41 +00:00
dc53f1cb5c
FastISel doesn't yet handle callee-pop functions.
...
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
2010-05-27 18:43:40 +00:00
5cde219fb1
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
...
to update the jmpbuf in the presence of VLAs.
llvm-svn: 104862
2010-05-27 18:23:48 +00:00
54b07ad2cd
Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring
...
common code between SSE versions.
llvm-svn: 104860
2010-05-27 18:17:40 +00:00
c0b69020cd
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
...
to be matched.
llvm-svn: 104757
2010-05-26 22:21:28 +00:00
4f6da9e3a8
Give SubRegIndex names to all ARM subregisters. This will be required by
...
TableGen shortly.
llvm-svn: 104754
2010-05-26 22:15:03 +00:00
b33dfbcba4
MC: Add TargetMachine support for setting the value of MCRelaxAll with
...
-filetype=obj.
llvm-svn: 104747
2010-05-26 21:48:55 +00:00
d1d7ed63ff
Add StringRef::compare_numeric and use it to sort TableGen register records.
...
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
llvm-svn: 104745
2010-05-26 21:47:28 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
...
ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
70e34983e8
Fix the x86 move to/from segment register instructions.
...
llvm-svn: 104731
2010-05-26 20:10:45 +00:00
7c8bd0fc98
MC: Change RelaxInstruction to only take the input and output instructions.
...
llvm-svn: 104713
2010-05-26 18:15:06 +00:00
338674a323
Fix a typo in a comment that Gabor noticed.
...
llvm-svn: 104711
2010-05-26 18:03:53 +00:00
a19838e107
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
...
before encoding.
llvm-svn: 104707
2010-05-26 17:45:29 +00:00
7de379467e
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
2010-05-26 17:27:12 +00:00
b34440a6a8
MC: Eliminate MCAsmFixup, replace with MCFixup.
...
llvm-svn: 104699
2010-05-26 15:18:56 +00:00
353a91ff76
MC: Use accessors for access to MCAsmFixup.
...
llvm-svn: 104697
2010-05-26 15:18:31 +00:00
3627af5da4
MC: Change MCInst::dump_pretty to not include a trailing newline.
...
llvm-svn: 104696
2010-05-26 15:18:13 +00:00
730a977e02
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
...
llvm-svn: 104691
2010-05-26 08:10:02 +00:00
c4376b9b1b
Coding style change (Adding 1 missing space.)
...
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
0568ca0ddc
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
llvm-svn: 104667
2010-05-26 03:21:39 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
50eec620f4
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
...
This reverts commit 104654.
llvm-svn: 104660
2010-05-26 01:21:14 +00:00
0b0274524c
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
2010-05-26 00:28:19 +00:00
b6e0bc9457
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
llvm-svn: 104653
2010-05-26 00:25:05 +00:00
e22abfa823
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
llvm-svn: 104652
2010-05-26 00:02:28 +00:00
66c939a2ca
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
...
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
492d4f409a
Changed the encoding of X86 floating point stack operations where both operands
...
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
2010-05-25 20:52:34 +00:00
3311eb50d7
Separate unrelated cases that once shared a numeric value
...
llvm-svn: 104629
2010-05-25 19:49:40 +00:00
1ad0d5e25b
Print symbolic SubRegIndex names on machine operands.
...
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
673e7e0f37
Remove NumberHack entirely.
...
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
2010-05-25 19:49:33 +00:00
0e767d7364
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
...
llvm-svn: 104626
2010-05-25 19:49:32 +00:00
4a5b2c597b
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
...
llvm-svn: 104622
2010-05-25 18:40:53 +00:00
c798965e63
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
llvm-svn: 104621
2010-05-25 18:16:58 +00:00
f6562d35ac
Make sure aeskeygenassist uses an unsigned immediate field.
...
Fixes rdar://8017638
llvm-svn: 104617
2010-05-25 17:33:22 +00:00
3b59e0601e
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
...
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
llvm-svn: 104615
2010-05-25 17:21:04 +00:00
36caaf1c59
Use enums instead of literals for SystemZ subregisters
...
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
396c8802b2
Use enums instead of literals for X86 subregisters.
...
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
llvm-svn: 104611
2010-05-25 17:04:16 +00:00
a6714e8a43
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
2da5aa1b60
Add support to MOVimm32 using movt/movw for ARM JIT
...
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
26fdebcae9
Clean up indentation.
...
llvm-svn: 104580
2010-05-25 03:36:52 +00:00
70affbd988
Use enums instead of literals in the ARM backend.
...
llvm-svn: 104573
2010-05-25 00:15:15 +00:00
fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
...
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
1181a19318
Lose the dummies
...
llvm-svn: 104564
2010-05-24 21:47:01 +00:00
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
...
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
79b6a0f140
Fix an mmx movd encoding.
...
llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
...
llvm-svn: 104549
2010-05-24 20:32:23 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
...
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
...
never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
8a57aeca2a
Use SubRegIndex in SystemZ.
...
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
5d56769fb6
SubRegIndex'ize Mips
...
llvm-svn: 104514
2010-05-24 17:42:58 +00:00
fd6f16fab9
SubRegIndex'ize MSP430
...
llvm-svn: 104513
2010-05-24 17:42:55 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
9340ea59e1
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
...
llvm-svn: 104455
2010-05-23 05:42:31 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
...
llvm-svn: 104435
2010-05-22 06:37:33 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
...
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
...
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
4dc833c607
add a note
...
llvm-svn: 104404
2010-05-21 23:16:21 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
...
llvm-svn: 104394
2010-05-21 23:01:38 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
...
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
2b78565842
Previous commit message should refer to 104308.
...
llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
...
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
...
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
...
llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
...
llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
...
llvm-svn: 104326
2010-05-21 17:49:07 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
...
isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
...
differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
...
llvm-svn: 104307
2010-05-21 00:43:17 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
...
llvm-svn: 104293
2010-05-20 23:26:43 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
...
llvm-svn: 104275
2010-05-20 20:36:29 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
...
llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
5954994bba
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
...
This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
098a47931c
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
d7d6638e3e
The PPC MFCR instruction implicitly uses all 8 of the CR
...
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
...
instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
5238275478
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
1e19eab963
Define the x86 pause instruction.
...
llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
...
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
...
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
52e37becf6
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
...
llvm-svn: 104122
2010-05-19 17:20:58 +00:00
d2f78e755f
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
llvm-svn: 104120
2010-05-19 15:26:43 +00:00
b243dfb085
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
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CALL64pcrel32, for the same reason.
llvm-svn: 104116
2010-05-19 08:07:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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llvm-svn: 104115
2010-05-19 07:28:01 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
...
llvm-svn: 104114
2010-05-19 07:26:50 +00:00
4f6c7c6d94
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
...
llvm-svn: 104112
2010-05-19 06:20:44 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
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llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
...
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
f8bf663873
Teach mode load folding and unfolding code about CMP32ri8 and friends.
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llvm-svn: 104068
2010-05-18 21:54:15 +00:00
4ed63f8687
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
...
specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
887dd1cd31
When converting a test to a cmp to fold a load, use the cmp that has an
...
8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
9f46539e07
make mcinstlower remove all but the first operand to CALL64pcrel32.
...
The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
...
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
a4820fcc78
MC/X86: Implement custom lowering to make sure we match things like
...
X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
llvm-svn: 104030
2010-05-18 17:22:24 +00:00
93d8844699
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
...
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
llvm-svn: 103995
2010-05-17 23:29:23 +00:00
02d3368831
- Set the "HasCalls" flag after instruction selection is finished.
...
- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00
cd04ed3533
vmov of immediates are trivially re-materializable.
...
llvm-svn: 103982
2010-05-17 21:54:50 +00:00
ce5e1bb326
MC: Add dyn_cast support to MCSection.
...
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.
llvm-svn: 103980
2010-05-17 21:54:26 +00:00
bf79238599
Add some section and constant support for darwin TLS.
...
llvm-svn: 103974
2010-05-17 21:02:07 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
3d98b996ff
Turn on -neon-reg-sequence by default.
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Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
2010-05-17 19:51:20 +00:00
5a2809cbd8
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
...
llvm-svn: 103917
2010-05-17 01:11:46 +00:00
2ef974ee0e
Revert 103911; it broke a test that expects bitconvert
...
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
llvm-svn: 103914
2010-05-16 20:19:04 +00:00
fc1492d71b
Make x86-64 64-bit bitconvert work when SSE is not available.
...
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
llvm-svn: 103911
2010-05-16 18:22:38 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
8f35fabbc1
Add support for thiscall calling convention.
...
Patch by Charles Davis and Steven Watanabe!
llvm-svn: 103902
2010-05-16 09:08:45 +00:00
4c719c4515
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
...
llvm-svn: 103901
2010-05-16 08:54:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
...
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
...
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
1bf28a128b
Some cheap DAG combine goodness for multiplication with a particular constant.
...
This can be extended later on to handle more "complex" constants.
llvm-svn: 103881
2010-05-15 18:16:59 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
...
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
3d214cdfaf
v4i64 and v8i64 are only synthesizable when NEON is available.
...
llvm-svn: 103855
2010-05-15 02:20:21 +00:00
4cad68eb34
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
...
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
2010-05-15 02:18:07 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
...
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
8c2d062ea6
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
...
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-14 23:21:14 +00:00
cb78e5558b
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
...
llvm-svn: 103833
2010-05-14 22:54:52 +00:00
0160e55893
SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
...
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)
llvm-svn: 103829
2010-05-14 22:17:42 +00:00
062a97f0f6
BR is a barrier.
...
llvm-svn: 103826
2010-05-14 22:00:27 +00:00
1713d95874
Several tail call tests apparently rely upon this being "adjusts stack" instead
...
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.
llvm-svn: 103824
2010-05-14 21:58:35 +00:00
e9ac7ad68c
This should happen if there are no calls, not if it just doesn't adjust the
...
stack.
llvm-svn: 103813
2010-05-14 21:38:44 +00:00
db4bc54c4f
Revert r103804. The comment is correct.
...
llvm-svn: 103808
2010-05-14 21:28:24 +00:00
7bf4bae5dc
Fix comment.
...
llvm-svn: 103804
2010-05-14 21:17:29 +00:00
95f6ebcb37
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
...
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
llvm-svn: 103802
2010-05-14 21:14:32 +00:00
35dd005d22
Lowering of atomic instructions can result in operands being
...
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.
llvm-svn: 103799
2010-05-14 21:01:44 +00:00
7bc111f5a9
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
...
argument, like "int $4", to not get an Assertion error.
llvm-svn: 103791
2010-05-14 19:16:02 +00:00
cfa7d02d6e
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
...
llvm-svn: 103790
2010-05-14 18:54:59 +00:00
30e3db2ba3
Set isTerminator on TRAP instructions.
...
llvm-svn: 103778
2010-05-14 16:46:02 +00:00
c56ca22616
Don't use isBarrier for the PowerPC sync instruction. isBarrier is for
...
control barriers, not memory ordering barriers.
llvm-svn: 103777
2010-05-14 16:42:16 +00:00
02d9947e60
Add mayLoad and mayStore flags to instructions which missed them.
...
llvm-svn: 103776
2010-05-14 16:34:55 +00:00
cd67c21407
Added a QQQQ register file to model 4-consecutive Q registers.
...
llvm-svn: 103760
2010-05-14 02:13:41 +00:00
ca21cc8b13
Fix comments.
...
llvm-svn: 103749
2010-05-14 00:21:45 +00:00
2ca1bd119e
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
...
llvm-svn: 103731
2010-05-13 20:02:08 +00:00
208dc08c2b
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
...
Do not use those for Thumb1 functions.
llvm-svn: 103730
2010-05-13 19:58:24 +00:00
82135e5a2f
CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936.
...
Patch by Dimitry Andric!
llvm-svn: 103727
2010-05-13 19:34:06 +00:00
449df9698f
Properly set thread-local flag on globals during cpp emission
...
llvm-svn: 103702
2010-05-13 07:41:57 +00:00
a58dc0ffdb
Fix -Asserts warning.
...
llvm-svn: 103694
2010-05-13 03:19:36 +00:00
9de7cfe3f4
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
...
llvm-svn: 103692
2010-05-13 01:12:06 +00:00
2f736c9577
Expand VMOVQQ into a pair of VMOVQ.
...
llvm-svn: 103684
2010-05-13 00:17:02 +00:00
79efd71962
Mark some pattern-less instructions as neverHasSideEffects.
...
llvm-svn: 103683
2010-05-13 00:16:46 +00:00
9efef006cf
reapply r103668 with a fix. Never make "minor syntax changes"
...
after testing before committing.
llvm-svn: 103681
2010-05-13 00:02:47 +00:00
e354235512
revert r103668 for now, it is apparently breaking things.
...
llvm-svn: 103677
2010-05-12 23:40:59 +00:00
a6df4650fd
moffset forms of moves are x86-32 only, make the parser
...
lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
llvm-svn: 103668
2010-05-12 23:13:36 +00:00
7c1f56f29a
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
...
llvm-svn: 103667
2010-05-12 23:13:12 +00:00
e132b0a92c
fix the encoding of the obscure "moffset" forms of moves, i386
...
part first. rdar://7947184
llvm-svn: 103660
2010-05-12 22:48:24 +00:00
5aa20d6c26
Remove a dead fixme.
...
llvm-svn: 103642
2010-05-12 20:20:22 +00:00
b69c7b76f1
Add support for movi32 of global values to the new (MC) asm printer.
...
llvm-svn: 103576
2010-05-12 05:16:34 +00:00
a2ff4fc96a
vst instructions are modeled as this:
...
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
llvm-svn: 103540
2010-05-12 01:42:50 +00:00
059379a9d7
MC/X86: Extend suffix matching hack to match 'q' suffix.
...
llvm-svn: 103535
2010-05-12 00:54:20 +00:00
ba2f4c3884
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
...
be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
llvm-svn: 103532
2010-05-12 00:38:17 +00:00
1a1b51ff59
Add initial kill flag support to FastISel.
...
llvm-svn: 103529
2010-05-11 23:54:07 +00:00
44e865f487
Avoid breaking vstd when reg_sequence is not used.
...
llvm-svn: 103513
2010-05-11 21:07:36 +00:00
508f661fbe
Simplify this logic of creating a default Features object.
...
llvm-svn: 103507
2010-05-11 20:46:04 +00:00
6c5e4355bb
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
...
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
llvm-svn: 103495
2010-05-11 20:16:09 +00:00
4cfccb801c
Remove the "WantsWholeFile" concept, as it's no longer needed. CBE
...
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.
llvm-svn: 103492
2010-05-11 19:57:55 +00:00
bb919dfb6b
Implement a bunch more TargetSelectionDAGInfo infrastructure.
...
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
llvm-svn: 103481
2010-05-11 17:31:57 +00:00
4df9d9ce11
Remove the TargetLowering::getSubtarget() virtual function, which
...
was unused. TargetMachine::getSubtarget() is used instead.
llvm-svn: 103474
2010-05-11 16:21:03 +00:00
9dd3ef8d01
Make SPU backend not assert on jump tables.
...
llvm-svn: 103466
2010-05-11 11:00:02 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
...
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
ea31737fef
Don't create a StringRef with a NULL value.
...
llvm-svn: 103455
2010-05-11 01:33:39 +00:00
e276c18385
Model some vst3 and vst4 with reg_sequence.
...
llvm-svn: 103453
2010-05-11 01:19:40 +00:00
a12c1ff25a
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
...
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
llvm-svn: 103451
2010-05-11 00:30:02 +00:00
630063aa0d
Model some vld3 instructions with REG_SEQUENCE.
...
llvm-svn: 103437
2010-05-10 21:26:24 +00:00
c2ae5f546f
Model vld2 / vst2 with reg_sequence.
...
llvm-svn: 103411
2010-05-10 17:34:18 +00:00
92ea401d8f
Fix encoding of 'sf' and 'sfh' instructions.
...
llvm-svn: 103399
2010-05-10 08:13:49 +00:00
b19c598843
updated handling dllexport in X86AsmPrinter
...
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform
llvm-svn: 103377
2010-05-09 08:40:06 +00:00
2760216c89
made COFF target dllexport logic apply to all subtargets
...
llvm-svn: 103373
2010-05-09 05:52:28 +00:00
72afa956db
break coff symbol definition stuff out into proper MCStreamer callbacks,
...
patch by Nathan Jeffords!
llvm-svn: 103346
2010-05-08 19:54:22 +00:00
2a41cad900
Clean up the conditional for handling of sign_extend_inreg based on
...
whether the extract instructions are available.
rdar://7956878
llvm-svn: 103277
2010-05-07 18:34:55 +00:00
4423abd734
Use overloaded operators instead of DIDescriptor::getNode()
...
llvm-svn: 103276
2010-05-07 18:19:32 +00:00
b3c5c4611c
Testing svn access with a note added to documentation.
...
llvm-svn: 103271
2010-05-07 18:06:28 +00:00
87cffa9498
switch MCSectionCOFF from a syntactic to semantic representation,
...
patch by Peter Housel!
llvm-svn: 103267
2010-05-07 17:17:41 +00:00
86eb22976f
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
...
llvm-svn: 103235
2010-05-07 02:04:02 +00:00
04d47e8efa
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
...
llvm-svn: 103234
2010-05-07 01:54:08 +00:00
90c600d6d2
When rematerializing, use the debug location of the original
...
instruction, rather than a location near where the new instruction
is being inserted.
llvm-svn: 103232
2010-05-07 01:28:10 +00:00
ddc93c7e04
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
...
llvm-svn: 103218
2010-05-07 00:24:52 +00:00
21aa523c28
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
...
- This fixes "leal 0, %eax", for example.
llvm-svn: 103205
2010-05-06 22:39:14 +00:00
348dc9b15a
fix rdar://7947167 - llvm-mc doesn't match movsq
...
llvm-svn: 103199
2010-05-06 21:48:14 +00:00
e7e1cf9fbd
Eliminated the classification of control registers into %ecr_
...
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
llvm-svn: 103196
2010-05-06 20:59:00 +00:00
358b29c855
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
...
we don't currently support relaxing them.
llvm-svn: 103195
2010-05-06 20:34:01 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
...
doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
...
llvm-svn: 103193
2010-05-06 19:06:44 +00:00
f765e1f34a
Add a missing break statement to fix unintentional fall-through
...
(replacing the previous patch for the same issue).
llvm-svn: 103183
2010-05-06 16:05:26 +00:00
5e3cccb1e4
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
...
llvm-svn: 103181
2010-05-06 15:32:49 +00:00
94231eec1f
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
...
llvm-svn: 103179
2010-05-06 14:57:47 +00:00
31cdcd46d6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
...
llvm-svn: 103172
2010-05-06 06:36:08 +00:00
77c71811f5
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
...
llvm-svn: 103163
2010-05-06 05:08:57 +00:00
9feb1bb117
Revert r103156 since it was breaking the build bots.
...
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
llvm-svn: 103159
2010-05-06 02:29:06 +00:00
8fd7b510d6
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
...
llvm-svn: 103157
2010-05-06 01:54:03 +00:00
8f99a1c6b4
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
...
llvm-svn: 103156
2010-05-06 01:52:03 +00:00
9d768f4445
Cosmetic changes.
...
llvm-svn: 103155
2010-05-06 01:34:11 +00:00
718ff448df
storeRegToStackSlot has forgotten about QPR_8 register class.
...
llvm-svn: 103154
2010-05-06 01:32:54 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
4cd930f417
Fixed a sign-extension bug in the X86 disassembler
...
that was causing PC-relative branch targets to be
evaluated incorrectly. Also added support for
checking operand values to the llvm-mc tester.
llvm-svn: 103128
2010-05-05 22:47:27 +00:00
61908f6b6c
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
...
llvm-svn: 103124
2010-05-05 22:15:40 +00:00
f62cd20b62
No-ops emitted for scheduling don't correspond with anything in the
...
user's source, so don't arbitrarily assign them a debug location.
llvm-svn: 103121
2010-05-05 20:58:01 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
d85631e700
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
...
llvm-svn: 103104
2010-05-05 18:28:36 +00:00
5ab29366b5
Trim include.
...
llvm-svn: 103103
2010-05-05 18:27:57 +00:00
4e7e4e6b60
Revert 102941, we're going to do this via attr and can just
...
hack the code to turn it off when debugging.
llvm-svn: 103083
2010-05-05 07:35:59 +00:00
a00830df31
Update comment.
...
llvm-svn: 103057
2010-05-04 22:13:03 +00:00
8e6b40a881
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
...
llvm-svn: 103047
2010-05-04 20:39:49 +00:00
a3a7b0099c
Do not pre-allocate for registers which form a REG_SEQUENCE.
...
llvm-svn: 103041
2010-05-04 20:38:12 +00:00
0185047b3f
"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
...
Patch by Kalle Raiskila!
llvm-svn: 103021
2010-05-04 17:58:46 +00:00
c3e0bafc6d
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
...
instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
llvm-svn: 103015
2010-05-04 17:31:02 +00:00
9b816a1bb3
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
...
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
llvm-svn: 103012
2010-05-04 16:12:42 +00:00
4c0f838637
fix operand indexes when outputting InvokeInsts
...
llvm-svn: 103003
2010-05-04 09:23:54 +00:00
8f0037097f
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
...
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
llvm-svn: 102991
2010-05-04 00:42:46 +00:00
30e637c9bc
rdar://7937137 - dbg values not being handled in thumb1 version of
...
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
llvm-svn: 102980
2010-05-04 00:11:37 +00:00
81bfca7bde
Implement builtin_return_address(x) and builtin_frame_address(x)
...
on PPC for x!=0. 7624113.
llvm-svn: 102972
2010-05-03 22:59:34 +00:00
6f2f8d0798
Changed llvm-mc to use the same suffixes with floating point compare
...
instructions as the Mac OS X darwin assembler. Some of which like 'fcoml'
assembled to different opcodes. While some of the suffixes were just different.
llvm-svn: 102958
2010-05-03 21:31:40 +00:00
e3a1726034
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
...
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
llvm-svn: 102952
2010-05-03 21:03:31 +00:00
1a51d4cec9
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
...
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
llvm-svn: 102951
2010-05-03 20:45:05 +00:00
937a5b75f9
Add an option, defaulting to off, to disable the sse domain crossing opts.
...
llvm-svn: 102941
2010-05-03 19:54:02 +00:00
73c8145505
Add a README entry.
...
llvm-svn: 102906
2010-05-03 14:31:00 +00:00
211427bda9
Remove the -enable-sjlj-eh option, which doesn't do anything.
...
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.
llvm-svn: 102865
2010-05-02 15:36:26 +00:00
2094488d81
fix some inconsistent line endings, patch by Jakub Staszak!
...
llvm-svn: 102852
2010-05-01 17:36:49 +00:00
319d71f44f
Do folding for indirect branches, where possible
...
llvm-svn: 102836
2010-05-01 12:28:21 +00:00
ebbdfef2fc
Implement indirect branches on MSP430
...
llvm-svn: 102835
2010-05-01 12:04:32 +00:00
6fbff44893
Long branch target oparands are not pc-rel.
...
This should fix PR6603.
llvm-svn: 102834
2010-05-01 12:04:22 +00:00
25c1653700
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
...
changes before doing phi lowering for switches.
llvm-svn: 102809
2010-05-01 00:01:06 +00:00
0cb06d64e8
Fix a typo.
...
llvm-svn: 102799
2010-04-30 22:38:11 +00:00
2e2cc87081
Make this code less confusing. Instead of reassigning BB, just operate
...
on the original variables, so it's easier to see what is being done
to which blocks.
llvm-svn: 102759
2010-04-30 20:14:26 +00:00
57bb73c80b
Remove the -disable-16bit command-line option, which is now obsolete.
...
llvm-svn: 102730
2010-04-30 18:30:26 +00:00
5117a555e0
Another sibcall bug. If caller and callee calling conventions differ, then it's only safe to do a tail call if the results are returned in the same way.
...
llvm-svn: 102683
2010-04-30 01:12:32 +00:00
0fd54fbbcf
Don't leave Base.FrameIndex uninitialized, so that it doesn't
...
print randomly in debug output.
llvm-svn: 102668
2010-04-29 23:30:41 +00:00
6feac8a39b
Make naked functions work on PPC.
...
llvm-svn: 102657
2010-04-29 19:32:19 +00:00
080e4fb2f0
Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g.
...
##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0
llvm-svn: 102655
2010-04-29 18:52:10 +00:00
38dfa5cf20
Load folding tail call should not use ebp / rbp after it's popped. PEI
...
should use esp / rsp to reference frame instead.
llvm-svn: 102596
2010-04-29 05:08:22 +00:00
b0a0a26df1
Add support for assemblers that don't support periods in a name
...
llvm-svn: 102594
2010-04-29 04:00:56 +00:00
250e917e9d
Frame index can be negative.
...
llvm-svn: 102577
2010-04-29 01:13:30 +00:00
4822841b82
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
...
Operand size override prefix to be part of their records.
llvm-svn: 102556
2010-04-28 23:20:40 +00:00
04cbcca319
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
...
rdar://7895451
llvm-svn: 102526
2010-04-28 20:33:09 +00:00
96fad31694
Teach X86FloatingPoint that a register can be killed multiple times by the same
...
instruction.
This instruction would crash the pass:
INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>
Now it doesn't.
llvm-svn: 102509
2010-04-28 18:28:37 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
...
llvm-svn: 102493
2010-04-28 08:30:49 +00:00
d21f564543
Unbreak the build. Only form shld / shrd after legalization.
...
llvm-svn: 102488
2010-04-28 02:25:18 +00:00
50c9431203
Emit debug info for byval parameters.
...
llvm-svn: 102486
2010-04-28 01:39:28 +00:00
347e3b8f15
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
...
llvm-svn: 102485
2010-04-28 01:18:01 +00:00
a3facc5cb5
further simplify EmitAlignment by eliminating the
...
ForcedAlignBits argument, tweaking the single client of it.
llvm-svn: 102484
2010-04-28 01:08:40 +00:00
c0458f1a40
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
...
llvm-svn: 102477
2010-04-28 00:35:10 +00:00
12f6855f85
Use MachineOperand::is* predicates.
...
llvm-svn: 102472
2010-04-27 22:24:37 +00:00
9e3a4ef089
Fix obvious typos.
...
llvm-svn: 102467
2010-04-27 21:46:03 +00:00
3b928af28f
SRA promotion is also not free.
...
llvm-svn: 102456
2010-04-27 19:48:31 +00:00
6a5e706e3c
on darwin empty functions need to codegen into something of non-zero length,
...
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
llvm-svn: 102400
2010-04-26 23:37:21 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
...
Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
91358585d7
Handle target-specific form of DBG_VALUE in AsmPrinter.
...
llvm-svn: 102373
2010-04-26 20:07:31 +00:00
bc41cfa78f
Add PPC AsmPrinter handling for target-specific form of
...
DBG_VALUE, and a cautionary comment.
llvm-svn: 102371
2010-04-26 20:05:01 +00:00
6e45f1d1ff
Promoting 16-bit cmp / test aren't free. Don't do it.
...
llvm-svn: 102366
2010-04-26 19:06:11 +00:00
1ff9d1b63e
Remove a redundant comment.
...
llvm-svn: 102326
2010-04-26 08:16:57 +00:00
f19bd4ebba
Add PPC specific emitFrameIndexDebugValue.
...
llvm-svn: 102325
2010-04-26 07:39:36 +00:00
bcb99ecc18
Add ARM specific emitFrameIndexDebugValue.
...
llvm-svn: 102324
2010-04-26 07:39:25 +00:00
ed69b382ea
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
...
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
llvm-svn: 102323
2010-04-26 07:38:55 +00:00
582565e991
Stop abusing EmitInstrWithCustomInserter for target-dependent
...
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
llvm-svn: 102320
2010-04-25 21:33:54 +00:00
a02d0e7d6b
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
...
llvm-svn: 102237
2010-04-24 04:44:57 +00:00
e1931fa676
Change TargetData's algorithm for computing defualt vector type
...
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.
llvm-svn: 102206
2010-04-23 19:41:15 +00:00
24b63f1597
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
...
llvm-svn: 102199
2010-04-23 19:03:32 +00:00
0367559786
Fix X86ISD::CMP i16 to i32 promotion.
...
llvm-svn: 102192
2010-04-23 18:21:16 +00:00
825cb299cd
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
...
extraction. This fixes PR5998.
llvm-svn: 102144
2010-04-22 23:24:18 +00:00
c594eab10f
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
...
and into SelectionDAGBuilder and FastISel.
llvm-svn: 102123
2010-04-22 20:46:50 +00:00
f1223bdec0
- It's not safe to promote rotates (at least not trivially).
...
- Some code refactoring.
llvm-svn: 102111
2010-04-22 20:19:46 +00:00
d85afee134
Modified some assert() msg strings; no other functionality change.
...
llvm-svn: 102008
2010-04-21 18:37:48 +00:00
4158a0ff6b
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
...
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
llvm-svn: 101984
2010-04-21 03:18:23 +00:00
9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
...
llvm-svn: 101979
2010-04-21 01:47:12 +00:00
873310f635
Trim include.
...
llvm-svn: 101978
2010-04-21 01:39:06 +00:00
57c732b032
Add more const qualifiers on TargetMachine and friends.
...
llvm-svn: 101977
2010-04-21 01:34:56 +00:00
dd56c40591
Thumb instructions which have reglist operands at the end and predicate operands
...
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
llvm-svn: 101974
2010-04-21 01:01:19 +00:00
11740305f9
Handle a displacement location in 64-bit as an RIP-relative displacement. It
...
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:
target triple = "x86_64-apple-darwin"
define double @func(double %a) {
%tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1]
ret double %tmp1
}
define i32 @main() nounwind {
%1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
ret i32 0
}
llvm-svn: 101965
2010-04-21 00:34:04 +00:00
84776786a7
teach the x86 address matching stuff to handle
...
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
llvm-svn: 101958
2010-04-20 23:18:40 +00:00
0522b90cdb
Because of the EMMS problem, right now we have to support
...
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
llvm-svn: 101951
2010-04-20 22:34:09 +00:00
8bcc00b43e
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
...
instead of just asserting.
llvm-svn: 101942
2010-04-20 21:29:28 +00:00
7be315c414
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
...
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
2010-04-20 17:28:50 +00:00
38c1a1a247
teach cellspu how to return i8 and i16 from calls,
...
patch by Kalle Raiskila!
llvm-svn: 101875
2010-04-20 05:36:09 +00:00
4025306a91
disable optimizations in this directory for MSVC9. This avoids
...
an optimizer infinite loop on the file, PR6866.
llvm-svn: 101854
2010-04-20 01:11:32 +00:00
2161e9f03b
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
...
d==15 is considered illegal. Return false instead of assert().
llvm-svn: 101852
2010-04-20 01:01:57 +00:00
64831c6a4c
Remove the palignr intrinsics now that we lower them to vector shuffles,
...
shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
llvm-svn: 101851
2010-04-20 00:59:54 +00:00
f3dd8b9487
More IT instruction error-handling improvements from fuzzing.
...
llvm-svn: 101839
2010-04-20 00:15:41 +00:00
e62b680965
Better error handling of invalid IT mask '0000', instead of just asserting.
...
llvm-svn: 101827
2010-04-19 23:02:58 +00:00
5ccd0b3686
Delete an unnecessary reference to SelectionDAGISel::BB.
...
llvm-svn: 101824
2010-04-19 22:48:45 +00:00
777346e749
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
...
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
llvm-svn: 101817
2010-04-19 21:19:52 +00:00
e19aa5cc52
More progress on promoting i16 operations to i32 for x86. Work in progress.
...
llvm-svn: 101808
2010-04-19 19:29:22 +00:00
25df2a75bd
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
...
instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
2010-04-19 17:16:40 +00:00
cbe3e1a3df
ARM disassembler did not react to recent changes to the NEON instruction table.
...
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
llvm-svn: 101784
2010-04-19 16:20:34 +00:00
7b056bfed0
Add missed part of prev. commit
...
llvm-svn: 101755
2010-04-18 20:41:42 +00:00
7d62e33291
Make processor FUs unique for given itinerary. This extends the limit of 32
...
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
llvm-svn: 101754
2010-04-18 20:31:01 +00:00
0a8d91a816
fix PR6332, allowing an index of zero into a zero sized array
...
even if the element of the array has no size.
llvm-svn: 101662
2010-04-17 19:02:33 +00:00
b927073f2e
teach the x86 asm parser how to handle segment prefixes
...
in memory operands. rdar://7874844
llvm-svn: 101661
2010-04-17 18:56:34 +00:00
1f0f2142cc
Fix -Wcast-qual warnings.
...
llvm-svn: 101655
2010-04-17 17:42:52 +00:00
05f34394d9
remove a dead variable, PR6856
...
llvm-svn: 101648
2010-04-17 17:28:00 +00:00
53d4a08d2b
Add const qualifiers to TargetLoweringObjectFile usage.
...
llvm-svn: 101640
2010-04-17 16:44:48 +00:00
88f7f6aeda
Use const_cast instead of a C-style cast to cast away const.
...
llvm-svn: 101639
2010-04-17 16:43:55 +00:00
8422e57baa
Delete now-unnecessary const_casts.
...
llvm-svn: 101637
2010-04-17 15:32:28 +00:00
20e094c711
Use cast instead of dyn_cast when assuming success.
...
llvm-svn: 101636
2010-04-17 15:31:16 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
31ae586c74
Move per-function state out of TargetLowering subclasses and into
...
MachineFunctionInfo subclasses.
llvm-svn: 101634
2010-04-17 14:41:14 +00:00
ca0a53ac52
Name these stub files consistently with the SPU and PPC targets' conventions.
...
Also rename the classes appropriately. The CMake build already used these
names.
llvm-svn: 101631
2010-04-17 08:50:29 +00:00
7f5088e6de
a bunch of ssse3 instructions are misencoded to think they have an
...
i8 field when they really do not. This fixes rdar://7840289
llvm-svn: 101629
2010-04-17 07:38:24 +00:00
f1bd5fcdb4
More work to allow dag combiner to promote 16-bit ops to 32-bit.
...
llvm-svn: 101621
2010-04-17 06:13:15 +00:00
59b70eacad
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
...
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
llvm-svn: 101615
2010-04-17 05:30:19 +00:00
cfc921cd2a
add a note
...
llvm-svn: 101581
2010-04-16 23:52:30 +00:00
7258dcd77f
Revert 101465, it broke internal OpenGL testing.
...
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
llvm-svn: 101579
2010-04-16 23:37:20 +00:00
c275414575
Cast to (uint64_t) instead of relying on the "ul" suffix.
...
llvm-svn: 101573
2010-04-16 23:30:28 +00:00
9becdddc49
Add skeleton target-specific SelectionDAGInfo files.
...
llvm-svn: 101564
2010-04-16 23:04:22 +00:00
ed9bee150b
Fixed logic error. Should check Builder for validity before calling SetSession
...
on it.
llvm-svn: 101563
2010-04-16 23:02:25 +00:00
b90b6f1a35
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
...
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
llvm-svn: 101557
2010-04-16 22:40:20 +00:00
d4758fc393
add a missing break back, patch by Nico Schmidt!
...
llvm-svn: 101538
2010-04-16 21:15:15 +00:00
148c69a3f6
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
...
llvm-svn: 101531
2010-04-16 20:11:05 +00:00
2b7aba10c2
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
...
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
llvm-svn: 101529
2010-04-16 19:57:21 +00:00
807e1748fc
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
...
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
llvm-svn: 101527
2010-04-16 19:33:23 +00:00
88599a42bb
Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are
...
considered legal instructions.
Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.
llvm-svn: 101524
2010-04-16 19:10:52 +00:00
f375520f7b
reapply r101434
...
with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101465
2010-04-16 15:33:14 +00:00
af56facacd
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
...
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
llvm-svn: 101448
2010-04-16 06:14:10 +00:00
3da64f7672
Use getAL() rather than a major constant.
...
llvm-svn: 101446
2010-04-16 05:46:06 +00:00
403e9694f9
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
...
llvm-svn: 101434
2010-04-16 01:16:20 +00:00
acbc06c2a3
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
...
am2offset. Modified the instruction table entry and added a new test case.
llvm-svn: 101415
2010-04-15 23:12:47 +00:00
f7f97b4bbd
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
...
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
33ae80bff7
reapply r101364, which has been backed out in r101368
...
with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101397
2010-04-15 20:51:13 +00:00
1ba1428577
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
...
llvm is generating poor code for dynamic alloca, I'll fix that later.
llvm-svn: 101383
2010-04-15 18:42:28 +00:00
4230e35879
DEBUG() print out "Unknown format" msg.
...
llvm-svn: 101382
2010-04-15 18:13:51 +00:00
48a189280e
ReuseFrameIndexVals is used in multiple files, so it can't be static.
...
llvm-svn: 101379
2010-04-15 17:34:58 +00:00
2085719a98
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
...
can't be static.
llvm-svn: 101377
2010-04-15 17:20:57 +00:00
b29cda9b3c
Fix a bunch of namespace polution.
...
llvm-svn: 101376
2010-04-15 17:08:50 +00:00
9fd00c7d25
back out r101364, as it trips the linux nightlybot on some clang C++ tests
...
llvm-svn: 101368
2010-04-15 12:46:56 +00:00
aafd209632
rotate CallInst operands, i.e. move callee to the back
...
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101364
2010-04-15 10:49:53 +00:00
4041ab6e00
Implement rdar://7860110 (also in target/readme.txt) narrowing
...
a load/or/and/store sequence into a narrower store when it is
safe. Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.
This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll
into:
movl %eax, 36(%rdi)
instead of:
movl $4294967295, %eax ## imm = 0xFFFFFFFF
andq 32(%rdi), %rax
shlq $32, %rcx
addq %rax, %rcx
movq %rcx, 32(%rdi)
and each of the testcases into a single store. Each of them used
to compile into craziness like this:
_test4:
movl $65535, %eax ## imm = 0xFFFF
andl (%rdi), %eax
shll $16, %esi
addl %eax, %esi
movl %esi, (%rdi)
ret
llvm-svn: 101343
2010-04-15 04:48:01 +00:00
913c998703
Add more const qualifiers for LLVM IR pointers in CodeGen.
...
llvm-svn: 101342
2010-04-15 04:33:49 +00:00
47bccf7f28
Fix build.
...
llvm-svn: 101335
2010-04-15 03:11:28 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
eabc9623da
Allow lowering for palignr instructions for mmx sized vectors. Add
...
patterns to handle the lowering.
llvm-svn: 101331
2010-04-15 01:40:20 +00:00
0175ec1263
Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
...
llvm-svn: 101329
2010-04-15 01:20:56 +00:00
82c50b11fa
Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
...
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).
llvm-svn: 101306
2010-04-14 22:37:17 +00:00
32bb362655
Add -arm-long-calls option to force calls to be indirect. This makes the
...
kernel linker happier when dealing with kexts.
Radar 7805069
llvm-svn: 101303
2010-04-14 22:28:31 +00:00
9aaaf4d5fa
For t2BFI disassembly, apply the same error checking as in r101205.
...
Change the error msg to read "Encoding error: msb < lsb".
llvm-svn: 101293
2010-04-14 22:04:45 +00:00
7637827064
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
...
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
llvm-svn: 101290
2010-04-14 21:03:13 +00:00
c05b887c84
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
...
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
llvm-svn: 101282
2010-04-14 20:45:23 +00:00
c87b74d913
Delete unneeeded arguments.
...
llvm-svn: 101276
2010-04-14 20:17:22 +00:00
7deb447781
Factor out EH landing pad code into a separate function, and constify
...
a bunch of stuff to support it.
llvm-svn: 101273
2010-04-14 19:53:31 +00:00
48bbf4910e
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
...
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.
llvm-svn: 101205
2010-04-14 02:05:29 +00:00
82c3cadad6
Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalid
...
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.
llvm-svn: 101201
2010-04-14 01:17:37 +00:00
9078f954bf
Unbreak CMake build by improving the EnhancedDisassembly makefile a
...
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
llvm-svn: 101188
2010-04-13 22:47:43 +00:00
699bdf7adf
Handle a v2f64 formal parameter that is split between registers and memory
...
such that the entire second half is in memory. Radar 7855014.
llvm-svn: 101181
2010-04-13 22:03:22 +00:00
814e69b171
Fixed a nasty layering violation in the edis source
...
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
llvm-svn: 101179
2010-04-13 21:21:57 +00:00
44d7d183fa
Changed getSOImmValRotate()'s hunt retry logic to ignore the low order 6 bits,
...
instead of 7, because we are only looking for even rotate amount.
llvm-svn: 101172
2010-04-13 20:35:16 +00:00
4ca4bc6f95
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.
...
llvm-svn: 101162
2010-04-13 18:50:27 +00:00
d67f66dc0c
Temporarily revert r101075, it's causing invalid iterator assertions
...
in a nightly tester.
llvm-svn: 101158
2010-04-13 18:37:58 +00:00
9d2d053e11
Eliminate MachineBasicBlock::const_livein_iterator and make
...
MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.
llvm-svn: 101147
2010-04-13 16:57:55 +00:00
a1cf9fef70
Use MachineBasicBlock::isLiveIn.
...
llvm-svn: 101144
2010-04-13 16:53:51 +00:00
af7674cbd4
Replace r101053 with a fix for getSOImmValRotate() so that it will correctly
...
recognize all the valid rotated immediates. This fixes the disassembler
issue and will also help codegen for some unusual constant values.
llvm-svn: 101114
2010-04-13 02:11:48 +00:00
5b212a31a2
add llvm codegen support for -ffunction-sections and -fdata-sections,
...
patch by Sylvere Teissier!
llvm-svn: 101106
2010-04-13 00:36:43 +00:00
d0d8e3343a
Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756
...
llvm-svn: 101085
2010-04-12 23:07:17 +00:00
b02bbe416f
Micro-optimization:
...
If we have this situation:
jCC L1
jmp L2
L1:
...
L2:
...
We can get a small performance boost by emitting this instead:
jnCC L2
L1:
...
L2:
...
This testcase shows an example of this:
float func(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
llvm-svn: 101075
2010-04-12 22:19:57 +00:00
fc93503c59
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
...
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
llvm-svn: 101053
2010-04-12 18:46:53 +00:00
4568ed7893
Implement support for varargs functions without any fixed
...
parameters in the CBE by implicitly adding a fixed argument.
This allows eliminating a work-around from DAE. Patch by
Sylvere Teissier!
llvm-svn: 100944
2010-04-10 19:12:44 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
1ef9826ff8
"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.
...
this patch disables .lcomm in favour of '.local .comm'
Patch by Kalle Raisklia!
llvm-svn: 100875
2010-04-09 18:27:03 +00:00
80c345927e
delete a forwarding function.
...
llvm-svn: 100815
2010-04-08 21:34:17 +00:00
5418dd5fda
move elf section uniquing to MCContext. Along the way
...
merge XCore's section into MCSectionELF
llvm-svn: 100812
2010-04-08 21:26:26 +00:00
433d40695b
remove the TargetLoweringObjectFileMachO::getMachoSection
...
api and update clients to use MCContext instead.
llvm-svn: 100808
2010-04-08 20:40:11 +00:00
c6a6d39289
use abstract interface in two more places
...
llvm-svn: 100762
2010-04-08 13:50:42 +00:00
1c73242012
fix compile
...
llvm-svn: 100760
2010-04-08 13:08:11 +00:00
11e7b32e4e
use abstract interface
...
llvm-svn: 100758
2010-04-08 12:52:19 +00:00
a6769269f3
Use twines to simplify calls to report_fatal_error. For code size and readability.
...
llvm-svn: 100756
2010-04-08 10:44:28 +00:00
ebe47c872f
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
...
llvm-svn: 100751
2010-04-08 07:37:57 +00:00
c0f63cf7a9
mpsadbw is not commutative.
...
Fixes PR3440.
llvm-svn: 100736
2010-04-08 00:52:02 +00:00
03549ee5af
Added support for ARM disassembly to edis.
...
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
llvm-svn: 100735
2010-04-08 00:48:21 +00:00
4b1b4205ed
Update CMake build.
...
llvm-svn: 100714
2010-04-07 23:05:23 +00:00
2104b8d36e
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
5109d3e55d
add newlines at end of files.
...
llvm-svn: 100706
2010-04-07 22:54:55 +00:00
85ce9f4f30
Missed this one line for the previous checkin to fix build warnings.
...
llvm-svn: 100697
2010-04-07 22:21:03 +00:00
8b04b550df
Fixed warnings pointed out by clang.
...
llvm-svn: 100696
2010-04-07 22:03:27 +00:00
80f8c3d533
Fixed warnings pointed out by clang.
...
Next to work on is ARMDisassemblerCore.cpp.
llvm-svn: 100695
2010-04-07 21:52:48 +00:00
1efe661b46
Fixed a bug where the disassembler would allow an immediate
...
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
llvm-svn: 100694
2010-04-07 21:42:19 +00:00
3f253e2cb1
Fixed 3 warnings pointed out by clang.
...
llvm-svn: 100693
2010-04-07 21:23:48 +00:00
4e2f8722c4
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
...
ARMDecoderEmitter.cpp, with FIXME comment.
llvm-svn: 100690
2010-04-07 20:53:12 +00:00
643a55708f
Added an AsmLexer for the ARM target, which uses
...
a simple mapping of register names to IDs to
identify register tokens.
llvm-svn: 100685
2010-04-07 20:29:34 +00:00
60b289709e
Educate GetInstrSizeInBytes implementations that
...
DBG_VALUE does not generate code.
llvm-svn: 100681
2010-04-07 19:51:44 +00:00
6e01726eae
Remove late ARM codegen optimization pass committed by accident.
...
It is not ready for public yet.
llvm-svn: 100673
2010-04-07 18:23:27 +00:00
090323aee5
Split A8/A9 itins - they already were too big.
...
llvm-svn: 100672
2010-04-07 18:22:11 +00:00
32457d6c5e
Add some crude itin approximation for VFP load / stores on A9
...
llvm-svn: 100671
2010-04-07 18:22:03 +00:00
d351104f19
Add some crude approximation for neon load/store instructions
...
llvm-svn: 100670
2010-04-07 18:21:58 +00:00
4acfad7c1b
Add some A8-based approximation for instructions with unknown cycle times
...
llvm-svn: 100669
2010-04-07 18:21:52 +00:00
Nico Weber