250e917e9d
Frame index can be negative.
...
llvm-svn: 102577
2010-04-29 01:13:30 +00:00
4822841b82
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
...
Operand size override prefix to be part of their records.
llvm-svn: 102556
2010-04-28 23:20:40 +00:00
04cbcca319
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
...
rdar://7895451
llvm-svn: 102526
2010-04-28 20:33:09 +00:00
96fad31694
Teach X86FloatingPoint that a register can be killed multiple times by the same
...
instruction.
This instruction would crash the pass:
INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>
Now it doesn't.
llvm-svn: 102509
2010-04-28 18:28:37 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
...
llvm-svn: 102493
2010-04-28 08:30:49 +00:00
d21f564543
Unbreak the build. Only form shld / shrd after legalization.
...
llvm-svn: 102488
2010-04-28 02:25:18 +00:00
50c9431203
Emit debug info for byval parameters.
...
llvm-svn: 102486
2010-04-28 01:39:28 +00:00
347e3b8f15
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
...
llvm-svn: 102485
2010-04-28 01:18:01 +00:00
a3facc5cb5
further simplify EmitAlignment by eliminating the
...
ForcedAlignBits argument, tweaking the single client of it.
llvm-svn: 102484
2010-04-28 01:08:40 +00:00
c0458f1a40
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
...
llvm-svn: 102477
2010-04-28 00:35:10 +00:00
12f6855f85
Use MachineOperand::is* predicates.
...
llvm-svn: 102472
2010-04-27 22:24:37 +00:00
9e3a4ef089
Fix obvious typos.
...
llvm-svn: 102467
2010-04-27 21:46:03 +00:00
3b928af28f
SRA promotion is also not free.
...
llvm-svn: 102456
2010-04-27 19:48:31 +00:00
6a5e706e3c
on darwin empty functions need to codegen into something of non-zero length,
...
otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
llvm-svn: 102400
2010-04-26 23:37:21 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
...
Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
91358585d7
Handle target-specific form of DBG_VALUE in AsmPrinter.
...
llvm-svn: 102373
2010-04-26 20:07:31 +00:00
bc41cfa78f
Add PPC AsmPrinter handling for target-specific form of
...
DBG_VALUE, and a cautionary comment.
llvm-svn: 102371
2010-04-26 20:05:01 +00:00
6e45f1d1ff
Promoting 16-bit cmp / test aren't free. Don't do it.
...
llvm-svn: 102366
2010-04-26 19:06:11 +00:00
1ff9d1b63e
Remove a redundant comment.
...
llvm-svn: 102326
2010-04-26 08:16:57 +00:00
f19bd4ebba
Add PPC specific emitFrameIndexDebugValue.
...
llvm-svn: 102325
2010-04-26 07:39:36 +00:00
bcb99ecc18
Add ARM specific emitFrameIndexDebugValue.
...
llvm-svn: 102324
2010-04-26 07:39:25 +00:00
ed69b382ea
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
...
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
llvm-svn: 102323
2010-04-26 07:38:55 +00:00
582565e991
Stop abusing EmitInstrWithCustomInserter for target-dependent
...
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
llvm-svn: 102320
2010-04-25 21:33:54 +00:00
a02d0e7d6b
Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity.
...
llvm-svn: 102237
2010-04-24 04:44:57 +00:00
e1931fa676
Change TargetData's algorithm for computing defualt vector type
...
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.
llvm-svn: 102206
2010-04-23 19:41:15 +00:00
24b63f1597
Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029.
...
llvm-svn: 102199
2010-04-23 19:03:32 +00:00
0367559786
Fix X86ISD::CMP i16 to i32 promotion.
...
llvm-svn: 102192
2010-04-23 18:21:16 +00:00
825cb299cd
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
...
extraction. This fixes PR5998.
llvm-svn: 102144
2010-04-22 23:24:18 +00:00
c594eab10f
Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
...
and into SelectionDAGBuilder and FastISel.
llvm-svn: 102123
2010-04-22 20:46:50 +00:00
f1223bdec0
- It's not safe to promote rotates (at least not trivially).
...
- Some code refactoring.
llvm-svn: 102111
2010-04-22 20:19:46 +00:00
d85afee134
Modified some assert() msg strings; no other functionality change.
...
llvm-svn: 102008
2010-04-21 18:37:48 +00:00
4158a0ff6b
Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
...
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181
llvm-svn: 101984
2010-04-21 03:18:23 +00:00
9c8cd8c061
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
...
llvm-svn: 101979
2010-04-21 01:47:12 +00:00
873310f635
Trim include.
...
llvm-svn: 101978
2010-04-21 01:39:06 +00:00
57c732b032
Add more const qualifiers on TargetMachine and friends.
...
llvm-svn: 101977
2010-04-21 01:34:56 +00:00
dd56c40591
Thumb instructions which have reglist operands at the end and predicate operands
...
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
llvm-svn: 101974
2010-04-21 01:01:19 +00:00
11740305f9
Handle a displacement location in 64-bit as an RIP-relative displacement. It
...
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:
target triple = "x86_64-apple-darwin"
define double @func(double %a) {
%tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1]
ret double %tmp1
}
define i32 @main() nounwind {
%1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
ret i32 0
}
llvm-svn: 101965
2010-04-21 00:34:04 +00:00
84776786a7
teach the x86 address matching stuff to handle
...
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.
This finishes off PR1135. Before we compiled the block to:
to:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
leaq 2(%rdx), %r9
movl %esi, (%rdi,%r9,4)
leaq 1(%rdx), %r9
movl %esi, (%rdi,%r9,4)
addq $3, %rdx
movl %esi, (%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
Now we produce:
LBB0_3: ## %bb
cmpb $4, %dl
sete %dl
addb %dl, %cl
movb %cl, %dl
shlb $2, %dl
addb %r8b, %dl
shlb $2, %dl
movzbl %dl, %edx
movl %esi, (%rdi,%rdx,4)
movl %esi, 8(%rdi,%rdx,4)
movl %esi, 4(%rdi,%rdx,4)
movl %esi, 12(%rdi,%rdx,4)
incb %r8b
decb %al
movb %r8b, %dl
jne LBB0_1
llvm-svn: 101958
2010-04-20 23:18:40 +00:00
0522b90cdb
Because of the EMMS problem, right now we have to support
...
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
llvm-svn: 101951
2010-04-20 22:34:09 +00:00
8bcc00b43e
Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),
...
instead of just asserting.
llvm-svn: 101942
2010-04-20 21:29:28 +00:00
7be315c414
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
...
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
2010-04-20 17:28:50 +00:00
38c1a1a247
teach cellspu how to return i8 and i16 from calls,
...
patch by Kalle Raiskila!
llvm-svn: 101875
2010-04-20 05:36:09 +00:00
4025306a91
disable optimizations in this directory for MSVC9. This avoids
...
an optimizer infinite loop on the file, PR6866.
llvm-svn: 101854
2010-04-20 01:11:32 +00:00
2161e9f03b
Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where
...
d==15 is considered illegal. Return false instead of assert().
llvm-svn: 101852
2010-04-20 01:01:57 +00:00
64831c6a4c
Remove the palignr intrinsics now that we lower them to vector shuffles,
...
shifts and null vectors. Autoupgrade these to what we'd lower them to.
Add a testcase to exercise this.
llvm-svn: 101851
2010-04-20 00:59:54 +00:00
f3dd8b9487
More IT instruction error-handling improvements from fuzzing.
...
llvm-svn: 101839
2010-04-20 00:15:41 +00:00
e62b680965
Better error handling of invalid IT mask '0000', instead of just asserting.
...
llvm-svn: 101827
2010-04-19 23:02:58 +00:00
5ccd0b3686
Delete an unnecessary reference to SelectionDAGISel::BB.
...
llvm-svn: 101824
2010-04-19 22:48:45 +00:00
777346e749
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
...
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
llvm-svn: 101817
2010-04-19 21:19:52 +00:00
e19aa5cc52
More progress on promoting i16 operations to i32 for x86. Work in progress.
...
llvm-svn: 101808
2010-04-19 19:29:22 +00:00
25df2a75bd
Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand
...
instructions should have Rd (Inst{11-8}) != 0b1111.
Ref: A6.3 32-bit Thumb instruction encoding
A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
2010-04-19 17:16:40 +00:00
cbe3e1a3df
ARM disassembler did not react to recent changes to the NEON instruction table.
...
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
llvm-svn: 101784
2010-04-19 16:20:34 +00:00
7b056bfed0
Add missed part of prev. commit
...
llvm-svn: 101755
2010-04-18 20:41:42 +00:00
7d62e33291
Make processor FUs unique for given itinerary. This extends the limit of 32
...
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
llvm-svn: 101754
2010-04-18 20:31:01 +00:00
0a8d91a816
fix PR6332, allowing an index of zero into a zero sized array
...
even if the element of the array has no size.
llvm-svn: 101662
2010-04-17 19:02:33 +00:00
b927073f2e
teach the x86 asm parser how to handle segment prefixes
...
in memory operands. rdar://7874844
llvm-svn: 101661
2010-04-17 18:56:34 +00:00
1f0f2142cc
Fix -Wcast-qual warnings.
...
llvm-svn: 101655
2010-04-17 17:42:52 +00:00
05f34394d9
remove a dead variable, PR6856
...
llvm-svn: 101648
2010-04-17 17:28:00 +00:00
53d4a08d2b
Add const qualifiers to TargetLoweringObjectFile usage.
...
llvm-svn: 101640
2010-04-17 16:44:48 +00:00
88f7f6aeda
Use const_cast instead of a C-style cast to cast away const.
...
llvm-svn: 101639
2010-04-17 16:43:55 +00:00
8422e57baa
Delete now-unnecessary const_casts.
...
llvm-svn: 101637
2010-04-17 15:32:28 +00:00
20e094c711
Use cast instead of dyn_cast when assuming success.
...
llvm-svn: 101636
2010-04-17 15:31:16 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
...
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
31ae586c74
Move per-function state out of TargetLowering subclasses and into
...
MachineFunctionInfo subclasses.
llvm-svn: 101634
2010-04-17 14:41:14 +00:00
ca0a53ac52
Name these stub files consistently with the SPU and PPC targets' conventions.
...
Also rename the classes appropriately. The CMake build already used these
names.
llvm-svn: 101631
2010-04-17 08:50:29 +00:00
7f5088e6de
a bunch of ssse3 instructions are misencoded to think they have an
...
i8 field when they really do not. This fixes rdar://7840289
llvm-svn: 101629
2010-04-17 07:38:24 +00:00
f1bd5fcdb4
More work to allow dag combiner to promote 16-bit ops to 32-bit.
...
llvm-svn: 101621
2010-04-17 06:13:15 +00:00
59b70eacad
Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this
...
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.
llvm-svn: 101615
2010-04-17 05:30:19 +00:00
cfc921cd2a
add a note
...
llvm-svn: 101581
2010-04-16 23:52:30 +00:00
7258dcd77f
Revert 101465, it broke internal OpenGL testing.
...
Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.
llvm-svn: 101579
2010-04-16 23:37:20 +00:00
c275414575
Cast to (uint64_t) instead of relying on the "ul" suffix.
...
llvm-svn: 101573
2010-04-16 23:30:28 +00:00
9becdddc49
Add skeleton target-specific SelectionDAGInfo files.
...
llvm-svn: 101564
2010-04-16 23:04:22 +00:00
ed9bee150b
Fixed logic error. Should check Builder for validity before calling SetSession
...
on it.
llvm-svn: 101563
2010-04-16 23:02:25 +00:00
b90b6f1a35
Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a
...
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.
Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().
llvm-svn: 101557
2010-04-16 22:40:20 +00:00
d4758fc393
add a missing break back, patch by Nico Schmidt!
...
llvm-svn: 101538
2010-04-16 21:15:15 +00:00
148c69a3f6
Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.
...
llvm-svn: 101531
2010-04-16 20:11:05 +00:00
2b7aba10c2
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(),
...
this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.
llvm-svn: 101529
2010-04-16 19:57:21 +00:00
807e1748fc
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed
...
to the UAL syntax of LDCL<c>, instead.
Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().
llvm-svn: 101527
2010-04-16 19:33:23 +00:00
88599a42bb
Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" are
...
considered legal instructions.
Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.
llvm-svn: 101524
2010-04-16 19:10:52 +00:00
f375520f7b
reapply r101434
...
with a fix for self-hosting
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101465
2010-04-16 15:33:14 +00:00
af56facacd
Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
...
x86 support is off by default. It can be enabled with -promote-16bit.
Work in progress.
llvm-svn: 101448
2010-04-16 06:14:10 +00:00
3da64f7672
Use getAL() rather than a major constant.
...
llvm-svn: 101446
2010-04-16 05:46:06 +00:00
403e9694f9
back out r101423 and r101397, they break llvm-gcc self-host on darwin10
...
llvm-svn: 101434
2010-04-16 01:16:20 +00:00
acbc06c2a3
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not
...
am2offset. Modified the instruction table entry and added a new test case.
llvm-svn: 101415
2010-04-15 23:12:47 +00:00
f7f97b4bbd
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
...
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
33ae80bff7
reapply r101364, which has been backed out in r101368
...
with a fix
rotate CallInst operands, i.e. move callee to the back
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101397
2010-04-15 20:51:13 +00:00
1ba1428577
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
...
llvm is generating poor code for dynamic alloca, I'll fix that later.
llvm-svn: 101383
2010-04-15 18:42:28 +00:00
4230e35879
DEBUG() print out "Unknown format" msg.
...
llvm-svn: 101382
2010-04-15 18:13:51 +00:00
48a189280e
ReuseFrameIndexVals is used in multiple files, so it can't be static.
...
llvm-svn: 101379
2010-04-15 17:34:58 +00:00
2085719a98
EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
...
can't be static.
llvm-svn: 101377
2010-04-15 17:20:57 +00:00
b29cda9b3c
Fix a bunch of namespace polution.
...
llvm-svn: 101376
2010-04-15 17:08:50 +00:00
9fd00c7d25
back out r101364, as it trips the linux nightlybot on some clang C++ tests
...
llvm-svn: 101368
2010-04-15 12:46:56 +00:00
aafd209632
rotate CallInst operands, i.e. move callee to the back
...
of the operand array
the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary
llvm-svn: 101364
2010-04-15 10:49:53 +00:00
4041ab6e00
Implement rdar://7860110 (also in target/readme.txt) narrowing
...
a load/or/and/store sequence into a narrower store when it is
safe. Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.
This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll
into:
movl %eax, 36(%rdi)
instead of:
movl $4294967295, %eax ## imm = 0xFFFFFFFF
andq 32(%rdi), %rax
shlq $32, %rcx
addq %rax, %rcx
movq %rcx, 32(%rdi)
and each of the testcases into a single store. Each of them used
to compile into craziness like this:
_test4:
movl $65535, %eax ## imm = 0xFFFF
andl (%rdi), %eax
shll $16, %esi
addl %eax, %esi
movl %esi, (%rdi)
ret
llvm-svn: 101343
2010-04-15 04:48:01 +00:00
913c998703
Add more const qualifiers for LLVM IR pointers in CodeGen.
...
llvm-svn: 101342
2010-04-15 04:33:49 +00:00
47bccf7f28
Fix build.
...
llvm-svn: 101335
2010-04-15 03:11:28 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
...
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
eabc9623da
Allow lowering for palignr instructions for mmx sized vectors. Add
...
patterns to handle the lowering.
llvm-svn: 101331
2010-04-15 01:40:20 +00:00
0175ec1263
Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.
...
llvm-svn: 101329
2010-04-15 01:20:56 +00:00
82c50b11fa
Fixed another assert exposed by fuzzing. Now, the DisassembleVFPLdStMulFrm()
...
function checks whether we have a valid submode for VLDM/VSTM (must be either
"ia" or "db") before calling ARM_AM::getAM5Opc(AMSubMode, unsigned char).
llvm-svn: 101306
2010-04-14 22:37:17 +00:00
32bb362655
Add -arm-long-calls option to force calls to be indirect. This makes the
...
kernel linker happier when dealing with kexts.
Radar 7805069
llvm-svn: 101303
2010-04-14 22:28:31 +00:00
9aaaf4d5fa
For t2BFI disassembly, apply the same error checking as in r101205.
...
Change the error msg to read "Encoding error: msb < lsb".
llvm-svn: 101293
2010-04-14 22:04:45 +00:00
7637827064
Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
...
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.
Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.
llvm-svn: 101290
2010-04-14 21:03:13 +00:00
c05b887c84
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
...
does not have a legal type. The legalizer does not know how to handle those
nodes. Radar 7854640.
llvm-svn: 101282
2010-04-14 20:45:23 +00:00
c87b74d913
Delete unneeeded arguments.
...
llvm-svn: 101276
2010-04-14 20:17:22 +00:00
7deb447781
Factor out EH landing pad code into a separate function, and constify
...
a bunch of stuff to support it.
llvm-svn: 101273
2010-04-14 19:53:31 +00:00
48bbf4910e
Fixed another assert exposed by fuzzing. Now, when an encoding error occurs
...
involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.
llvm-svn: 101205
2010-04-14 02:05:29 +00:00
82c3cadad6
Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalid
...
instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.
llvm-svn: 101201
2010-04-14 01:17:37 +00:00
9078f954bf
Unbreak CMake build by improving the EnhancedDisassembly makefile a
...
bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.
llvm-svn: 101188
2010-04-13 22:47:43 +00:00
699bdf7adf
Handle a v2f64 formal parameter that is split between registers and memory
...
such that the entire second half is in memory. Radar 7855014.
llvm-svn: 101181
2010-04-13 22:03:22 +00:00
814e69b171
Fixed a nasty layering violation in the edis source
...
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
llvm-svn: 101179
2010-04-13 21:21:57 +00:00
44d7d183fa
Changed getSOImmValRotate()'s hunt retry logic to ignore the low order 6 bits,
...
instead of 7, because we are only looking for even rotate amount.
llvm-svn: 101172
2010-04-13 20:35:16 +00:00
4ca4bc6f95
Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.
...
llvm-svn: 101162
2010-04-13 18:50:27 +00:00
d67f66dc0c
Temporarily revert r101075, it's causing invalid iterator assertions
...
in a nightly tester.
llvm-svn: 101158
2010-04-13 18:37:58 +00:00
9d2d053e11
Eliminate MachineBasicBlock::const_livein_iterator and make
...
MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.
llvm-svn: 101147
2010-04-13 16:57:55 +00:00
a1cf9fef70
Use MachineBasicBlock::isLiveIn.
...
llvm-svn: 101144
2010-04-13 16:53:51 +00:00
af7674cbd4
Replace r101053 with a fix for getSOImmValRotate() so that it will correctly
...
recognize all the valid rotated immediates. This fixes the disassembler
issue and will also help codegen for some unusual constant values.
llvm-svn: 101114
2010-04-13 02:11:48 +00:00
5b212a31a2
add llvm codegen support for -ffunction-sections and -fdata-sections,
...
patch by Sylvere Teissier!
llvm-svn: 101106
2010-04-13 00:36:43 +00:00
d0d8e3343a
Use .set expression for x86 pic jump table reference to reduce assembly relocation. rdar://7738756
...
llvm-svn: 101085
2010-04-12 23:07:17 +00:00
b02bbe416f
Micro-optimization:
...
If we have this situation:
jCC L1
jmp L2
L1:
...
L2:
...
We can get a small performance boost by emitting this instead:
jnCC L2
L1:
...
L2:
...
This testcase shows an example of this:
float func(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
llvm-svn: 101075
2010-04-12 22:19:57 +00:00
fc93503c59
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling
...
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2.
Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from
ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V).
[12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc
GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done
(gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
(gdb) r
Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble
Reading symbols for shared libraries ++. done
0xf5 0x71 0xf0 0x53
Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1|
-------------------------------------------------------------------------------------------------
mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229.
Program received signal SIGABRT, Aborted.
0x00007fff88c65886 in __kill ()
(gdb) bt
#0 0x00007fff88c65886 in __kill ()
#1 0x00007fff88d05eae in abort ()
#2 0x00007fff88cf2ef0 in __assert_rtn ()
#3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229
#4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254
#5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236
#6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182
#7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65
#8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153
#9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347
#10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374
(gdb) q
The program is running. Exit anyway? (y or n) y
[13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $
llvm-svn: 101053
2010-04-12 18:46:53 +00:00
4568ed7893
Implement support for varargs functions without any fixed
...
parameters in the CBE by implicitly adding a fixed argument.
This allows eliminating a work-around from DAE. Patch by
Sylvere Teissier!
llvm-svn: 100944
2010-04-10 19:12:44 +00:00
0106063556
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
...
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
llvm-svn: 100892
2010-04-09 20:41:18 +00:00
1ef9826ff8
"On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.
...
this patch disables .lcomm in favour of '.local .comm'
Patch by Kalle Raisklia!
llvm-svn: 100875
2010-04-09 18:27:03 +00:00
80c345927e
delete a forwarding function.
...
llvm-svn: 100815
2010-04-08 21:34:17 +00:00
5418dd5fda
move elf section uniquing to MCContext. Along the way
...
merge XCore's section into MCSectionELF
llvm-svn: 100812
2010-04-08 21:26:26 +00:00
433d40695b
remove the TargetLoweringObjectFileMachO::getMachoSection
...
api and update clients to use MCContext instead.
llvm-svn: 100808
2010-04-08 20:40:11 +00:00
c6a6d39289
use abstract interface in two more places
...
llvm-svn: 100762
2010-04-08 13:50:42 +00:00
1c73242012
fix compile
...
llvm-svn: 100760
2010-04-08 13:08:11 +00:00
11e7b32e4e
use abstract interface
...
llvm-svn: 100758
2010-04-08 12:52:19 +00:00
a6769269f3
Use twines to simplify calls to report_fatal_error. For code size and readability.
...
llvm-svn: 100756
2010-04-08 10:44:28 +00:00
ebe47c872f
Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.
...
llvm-svn: 100751
2010-04-08 07:37:57 +00:00
c0f63cf7a9
mpsadbw is not commutative.
...
Fixes PR3440.
llvm-svn: 100736
2010-04-08 00:52:02 +00:00
03549ee5af
Added support for ARM disassembly to edis.
...
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
llvm-svn: 100735
2010-04-08 00:48:21 +00:00
4b1b4205ed
Update CMake build.
...
llvm-svn: 100714
2010-04-07 23:05:23 +00:00
2104b8d36e
rename llvm::llvm_report_error -> llvm::report_fatal_error
...
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
5109d3e55d
add newlines at end of files.
...
llvm-svn: 100706
2010-04-07 22:54:55 +00:00
85ce9f4f30
Missed this one line for the previous checkin to fix build warnings.
...
llvm-svn: 100697
2010-04-07 22:21:03 +00:00
8b04b550df
Fixed warnings pointed out by clang.
...
llvm-svn: 100696
2010-04-07 22:03:27 +00:00
80f8c3d533
Fixed warnings pointed out by clang.
...
Next to work on is ARMDisassemblerCore.cpp.
llvm-svn: 100695
2010-04-07 21:52:48 +00:00
1efe661b46
Fixed a bug where the disassembler would allow an immediate
...
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
llvm-svn: 100694
2010-04-07 21:42:19 +00:00
3f253e2cb1
Fixed 3 warnings pointed out by clang.
...
llvm-svn: 100693
2010-04-07 21:23:48 +00:00
4e2f8722c4
Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
...
ARMDecoderEmitter.cpp, with FIXME comment.
llvm-svn: 100690
2010-04-07 20:53:12 +00:00
643a55708f
Added an AsmLexer for the ARM target, which uses
...
a simple mapping of register names to IDs to
identify register tokens.
llvm-svn: 100685
2010-04-07 20:29:34 +00:00
60b289709e
Educate GetInstrSizeInBytes implementations that
...
DBG_VALUE does not generate code.
llvm-svn: 100681
2010-04-07 19:51:44 +00:00
6e01726eae
Remove late ARM codegen optimization pass committed by accident.
...
It is not ready for public yet.
llvm-svn: 100673
2010-04-07 18:23:27 +00:00
090323aee5
Split A8/A9 itins - they already were too big.
...
llvm-svn: 100672
2010-04-07 18:22:11 +00:00
32457d6c5e
Add some crude itin approximation for VFP load / stores on A9
...
llvm-svn: 100671
2010-04-07 18:22:03 +00:00
d351104f19
Add some crude approximation for neon load/store instructions
...
llvm-svn: 100670
2010-04-07 18:21:58 +00:00
4acfad7c1b
Add some A8-based approximation for instructions with unknown cycle times
...
llvm-svn: 100669
2010-04-07 18:21:52 +00:00
4fb6a66c8f
Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.
...
llvm-svn: 100668
2010-04-07 18:21:46 +00:00
982f0ceaf8
Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.
...
llvm-svn: 100667
2010-04-07 18:21:41 +00:00
4050d69dcf
Fix A8 FP NEON MAC itins
...
llvm-svn: 100666
2010-04-07 18:21:33 +00:00
9ff2f8f7a5
A9 NEON FP itins
...
llvm-svn: 100665
2010-04-07 18:21:27 +00:00
03b317a286
Some permute goodness for A9
...
llvm-svn: 100664
2010-04-07 18:21:22 +00:00
7ab31047a7
More shift itins for A9
...
llvm-svn: 100663
2010-04-07 18:21:16 +00:00
4d36f8890f
More fixes for itins
...
llvm-svn: 100662
2010-04-07 18:21:10 +00:00
ceb54d5ab0
Fix invalid itins for 32-bit varians of VMLAL and friends
...
llvm-svn: 100661
2010-04-07 18:21:04 +00:00
f64c7ca5c3
Add MAC stuff for A9
...
llvm-svn: 100660
2010-04-07 18:20:58 +00:00
2ef0a12fa1
Fix invalid NEON MAC itins on A8
...
llvm-svn: 100659
2010-04-07 18:20:53 +00:00
5e208dc21b
Fix itins for VPAL
...
llvm-svn: 100658
2010-04-07 18:20:47 +00:00
a248becd6c
Fix itins for VABA
...
llvm-svn: 100657
2010-04-07 18:20:42 +00:00
a3e4989ad8
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
...
llvm-svn: 100656
2010-04-07 18:20:36 +00:00
140a65ce0b
More A9 itineraries
...
llvm-svn: 100655
2010-04-07 18:20:29 +00:00
1a1af5a830
Correct itinerary class for VPADD
...
llvm-svn: 100654
2010-04-07 18:20:24 +00:00
4650fd5fc6
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
...
llvm-svn: 100653
2010-04-07 18:20:18 +00:00
7d4fad5942
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
...
llvm-svn: 100652
2010-04-07 18:20:13 +00:00
2cba05bbe1
Some easy NEON scheduling goodness for A9
...
llvm-svn: 100651
2010-04-07 18:20:07 +00:00
2063705d91
Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
...
llvm-svn: 100650
2010-04-07 18:20:02 +00:00
c1e7a6feac
FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9.
...
llvm-svn: 100649
2010-04-07 18:19:56 +00:00
dad973334b
Proper cycle times for locks, since wbck latency can be larger than fwd latency.
...
llvm-svn: 100648
2010-04-07 18:19:51 +00:00
4c1da0f82a
Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
...
llvm-svn: 100647
2010-04-07 18:19:46 +00:00
baeb210be7
Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.
...
llvm-svn: 100646
2010-04-07 18:19:40 +00:00
15ccae2a46
Some bits of A9 scheduling: VFP
...
llvm-svn: 100643
2010-04-07 18:19:18 +00:00
10fc6e9650
Separate const from non-const stuff during mergeing
...
llvm-svn: 100642
2010-04-07 18:19:13 +00:00
0453de0133
Some initial version of global merger
...
llvm-svn: 100641
2010-04-07 18:19:07 +00:00
dd1c82141c
Fix memory leaks for external symbol name strings.
...
llvm-svn: 100601
2010-04-07 03:36:01 +00:00
6ac5cc973c
Clean up some signedness oddities in this code noticed by clang.
...
llvm-svn: 100599
2010-04-07 01:49:15 +00:00
5d7f0a0fdd
Move printing of target-indepedent DEBUG_VALUE comments
...
into AsmPrinter. Target-dependent form is still generated
by FastISel and still handled in X86 code.
llvm-svn: 100596
2010-04-07 01:15:14 +00:00
796583eec0
Fix a number of clang -Wsign-compare warnings that didn't have an obvious
...
solution. The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.
llvm-svn: 100581
2010-04-06 23:35:53 +00:00
b36c70913b
Revert 100573, it's causing some testsuite problems.
...
llvm-svn: 100578
2010-04-06 22:45:26 +00:00
85b35b6214
Move printing of DEBUG_VALUE comments to target-independent place.
...
There is probably a more elegant way to do this.
llvm-svn: 100573
2010-04-06 22:21:07 +00:00
5202269dc4
Expand SELECT and SELECT_CC for NEON vector types.
...
Radar 7770501.
llvm-svn: 100568
2010-04-06 22:02:24 +00:00
4dac890600
Fix PR6696 and PR6663
...
When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.
For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.
llvm-svn: 100559
2010-04-06 20:26:37 +00:00
41051a0bfe
Don't try to collapse DomainValues onto an incompatible SSE domain.
...
This fixes the Bullet regression on i386/nocona.
llvm-svn: 100553
2010-04-06 19:48:56 +00:00
1a9b3f3484
Properly enable load clustering.
...
Operand 2 on a load instruction does not have to be a RegisterSDNode for this to
work.
llvm-svn: 100497
2010-04-05 23:48:02 +00:00
23d16d5b86
Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler.
...
llvm-svn: 100480
2010-04-05 22:21:09 +00:00
1290fa0f72
Remove FIXME.
...
llvm-svn: 100466
2010-04-05 21:14:32 +00:00
6e39c4a097
don't use emitlabel in the arm asm printer yet, the order
...
isn't well specified. ARM really needs to have its instprinter
finished at some point.
llvm-svn: 100439
2010-04-05 17:52:31 +00:00
6a0e89aefb
fix a couple problems I introduced handling symbols
...
with spaces in them. Sym->getName() != OS << *Sym
llvm-svn: 100434
2010-04-05 16:32:14 +00:00
0151d7b025
Disambiguate else.
...
llvm-svn: 100423
2010-04-05 10:17:15 +00:00
305f2efb63
unthread MMI from FastISel
...
llvm-svn: 100416
2010-04-05 06:05:26 +00:00
82ff9af068
remove the MMI pointer from MachineFrameInfo.
...
llvm-svn: 100415
2010-04-05 05:57:52 +00:00
50b1bf63a7
simplify code.
...
llvm-svn: 100412
2010-04-05 05:48:36 +00:00
dacfd2c6d4
Get rid of traling whitespaces. No functionality change.
...
llvm-svn: 100404
2010-04-05 04:51:50 +00:00
dba13e7922
The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
...
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)
to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.
llvm-svn: 100403
2010-04-05 04:46:17 +00:00
f0ef4e4019
implement EmitFunctionEntryLabel to emit the .cc_top directive,
...
allowing xcore to use the normal runOnMachineFunction
implementation.
llvm-svn: 100402
2010-04-05 04:44:02 +00:00
a49ac8ace0
prune some #includes.
...
llvm-svn: 100399
2010-04-05 04:04:10 +00:00
b93331f3be
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
...
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
2010-04-05 03:10:20 +00:00
7cfa70e9b3
fastisel doesn't need DwarfWriter, remove some tendricles.
...
llvm-svn: 100381
2010-04-05 02:19:28 +00:00
0b8adb0652
Temporarily remove to disable building of ARM disassembler.
...
llvm-svn: 100380
2010-04-05 01:57:50 +00:00
492a82e426
Re-apply 100265 but instead disable building of ARM disassembly for now.
...
llvm-svn: 100379
2010-04-05 01:34:00 +00:00
876a5015af
Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.
...
llvm-svn: 100378
2010-04-05 01:04:27 +00:00
626cb66fdb
just have all targets create the DwarfWriter.
...
llvm-svn: 100377
2010-04-05 00:42:55 +00:00
8b30492da3
simplify various getAnalysisUsage implementations.
...
llvm-svn: 100376
2010-04-05 00:38:44 +00:00
324c86600d
eliminate the magic AbsoluteDebugSectionOffsets MAI hook,
...
which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.
Yay for reduction in magic.
llvm-svn: 100367
2010-04-04 23:22:29 +00:00
8964b838e4
revert my patch, need to reconsider this and figure out what is really going on.
...
llvm-svn: 100358
2010-04-04 21:49:31 +00:00
407f848835
fix pasto, this is the wrong setting for arm elf.
...
llvm-svn: 100357
2010-04-04 21:37:20 +00:00
d03ac95d5d
Clean up SSEDomainFix pass.
...
Restrict bit mask operations to the DomainValue class. Rename methods for
clarity.
llvm-svn: 100353
2010-04-04 21:27:26 +00:00
4af7c5a650
don't reset the default.
...
llvm-svn: 100352
2010-04-04 21:06:50 +00:00
7bde8c07a7
clean up the asmprinter header and privatize some stuff.
...
llvm-svn: 100342
2010-04-04 18:52:31 +00:00
21dc46e256
remove TargetMachine.h #include, also, TRI isn't used frequently
...
enough to warrant caching in AsmPrinter, so remove it.
llvm-svn: 100336
2010-04-04 18:06:11 +00:00
42caaa4f5b
Switch SSEDomainFix to SpecificBumpPtrAllocator.
...
llvm-svn: 100332
2010-04-04 18:00:21 +00:00
d20699bc87
Momentous day: remove the "O" member from AsmPrinter. Now all
...
"asm printering" happens through MCStreamer. This also
Streamerizes PIC16 debug info, which escaped my attention.
This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.
llvm-svn: 100327
2010-04-04 08:18:47 +00:00
3cb9086c26
mc'ize the remaining uses of O.
...
llvm-svn: 100322
2010-04-04 07:23:00 +00:00
4f63f7ee8e
finish eliminating uses of O.
...
llvm-svn: 100321
2010-04-04 07:17:25 +00:00
794b2f1b37
mcize more of ppc stub printing.
...
llvm-svn: 100320
2010-04-04 07:12:28 +00:00
5e5961864f
mcize a bunch more stuff, using EmitRawText for things we
...
don't have mcstreamer support for yet.
llvm-svn: 100319
2010-04-04 07:05:53 +00:00
3d86cd6710
convert the non-MCInstPrinter'ized EmitInstruction
...
implementations to use EmitRawText instead of writing
directly to "O".
llvm-svn: 100318
2010-04-04 06:12:20 +00:00
83a093183c
streamerize the rest of PIC16 asm printer.
...
llvm-svn: 100317
2010-04-04 05:53:03 +00:00
d479317d65
streamerize printing of dbg_value, the x86 backend is now fully
...
streamerized for everything.
llvm-svn: 100316
2010-04-04 05:40:34 +00:00
bf43d4b6e9
split DEBUG_VALUE printing stuff out to its own method.
...
llvm-svn: 100315
2010-04-04 05:38:19 +00:00
9b13639f45
mc'ize elf stub printing, convert cygwin stuff to EmitRawText,
...
which will abort in .o file writing mode.
llvm-svn: 100314
2010-04-04 05:35:04 +00:00
3bb09768cb
fix PrintAsmOperand and PrintAsmMemoryOperand to pass down
...
raw_ostream to print to.
llvm-svn: 100313
2010-04-04 05:29:35 +00:00
787253819a
use predicates in DBG_VALUE printing code to simplify it.
...
llvm-svn: 100312
2010-04-04 05:21:31 +00:00
562e02e4e1
remove more implicit uses of "O".
...
llvm-svn: 100311
2010-04-04 05:19:20 +00:00
7012916275
fix an ugly wart in the MCInstPrinter api where the
...
raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.
llvm-svn: 100307
2010-04-04 05:04:31 +00:00
76c564b1bb
change a ton of code to not implicitly use the "O" raw_ostream
...
member of AsmPrinter. Instead, pass it in explicitly.
llvm-svn: 100306
2010-04-04 04:47:45 +00:00
c576ee9040
Reapply address space patch after fixing an issue in MemCopyOptimizer.
...
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
llvm-svn: 100304
2010-04-04 03:10:48 +00:00
f33c7fcc28
asmstreamerize the .size directive for function bodies, force clients
...
of printOffset to pass in a stream to print to.
llvm-svn: 100296
2010-04-03 22:28:33 +00:00
fc8c3b7547
Get rid of the middleman (ARMAlgorithm), which causes more trouble than the
...
abstraction it brings. And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)
llvm-svn: 100265
2010-04-03 04:10:56 +00:00
884e66a545
Fix comment.
...
llvm-svn: 100259
2010-04-03 01:17:30 +00:00
58e83eb50d
Register ARMAlgorithm::DoCleanup() to be called on exit to free the memory
...
occuplied by the cached ARMAlgorithm objects.
llvm-svn: 100258
2010-04-03 01:09:47 +00:00
000e502eb1
Rewrite aesimc handling. It only takes a single input and has a single
...
dest.
llvm-svn: 100252
2010-04-02 23:48:33 +00:00
a0d74064fe
Fix another build warning.
...
llvm-svn: 100251
2010-04-02 23:43:38 +00:00
7b999ea7b7
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
...
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
llvm-svn: 100233
2010-04-02 22:27:38 +00:00
7ad0ad0b9a
Added support for reporting operand token ranges
...
to the ARM AsmParser.
llvm-svn: 100232
2010-04-02 22:27:05 +00:00
2ef63183a5
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
...
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
llvm-svn: 100231
2010-04-02 21:54:27 +00:00
010b373cf3
Fixes to the X86 disassembler. The disassembler will now
...
return an error status in all failure cases, printing
messages to debugs() only when debugging is enabled.
llvm-svn: 100229
2010-04-02 21:23:51 +00:00
593916d732
rename NewDebugLoc -> DebugLoc, prune #includes in DebugLoc.h.
...
This keeps around temporary typedef for clang/llvm-gcc so the
build won't break when I commit this :)
llvm-svn: 100218
2010-04-02 20:21:22 +00:00
6f306d7d30
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
...
llvm-svn: 100214
2010-04-02 20:16:16 +00:00
915c5f9862
Switch the code generator (except the JIT) onto the new DebugLoc
...
representation. This eliminates the 'DILocation' MDNodes for
file/line/col tuples from -O0 -g codegen.
This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.
I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before. Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.
llvm-svn: 100209
2010-04-02 19:42:39 +00:00
61399375a2
Correctly lower memset / memcpy of undef. It should be a nop. PR6767.
...
llvm-svn: 100208
2010-04-02 19:36:14 +00:00
999c1b927b
Revert r100191 since it breaks objc in clang
...
llvm-svn: 100199
2010-04-02 18:43:02 +00:00
a972ab8564
Reapply address space patch after fixing an issue in MemCopyOptimizer.
...
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
llvm-svn: 100191
2010-04-02 18:04:15 +00:00
06a1639b98
Remove FIXME - if there's a better way to do this it isn't here.
...
llvm-svn: 100176
2010-04-02 04:32:37 +00:00
4bd755419f
Revert the recent alignment changes. They're broken for -Os because,
...
in particular, they end up aligning strings at 16-byte boundaries, and
there's no way for GlobalOpt to check OptForSize.
llvm-svn: 100172
2010-04-02 03:04:37 +00:00
4244d12769
Teach AnalyzeBranch, RemoveBranch and the branch
...
folder to be tolerant of debug info following the
branch(es) at the end of a block.
llvm-svn: 100168
2010-04-02 01:38:09 +00:00
8d6d0d4c58
Disambiguate conditional expression for newer GCCs.
...
llvm-svn: 100167
2010-04-02 01:31:24 +00:00
0e3218f6af
Change variables which are exactly 16 bytes to be 16-byte-aligned too.
...
This fixes test/Transforms/GlobalOpt/gv-align.ll.
llvm-svn: 100161
2010-04-02 00:46:07 +00:00
5342ddaadf
Revert r100143.
...
llvm-svn: 100146
2010-04-01 22:54:42 +00:00
f997c31598
In 64-bit mode, use i64 to lower memcpy / memset instead of f64.
...
llvm-svn: 100137
2010-04-01 20:27:45 +00:00
d9929f03cf
Add comments about DstAlign and SrcAlign.
...
llvm-svn: 100132
2010-04-01 20:10:42 +00:00
4c014c892a
- Avoid using floating point stores to implement memset unless the value is zero.
...
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
llvm-svn: 100118
2010-04-01 18:19:11 +00:00
43cd9e3845
Fix sdisel memcpy, memset, memmove lowering:
...
1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
llvm-svn: 100090
2010-04-01 06:04:33 +00:00
738b0f9ec7
Nehalem unaligned memory access is fast.
...
llvm-svn: 100089
2010-04-01 05:58:17 +00:00
9002ac5d93
Add aeskeygenassist intrinsic and rename all of the aes intrinsics to
...
aes instead of sse4.2. Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.
llvm-svn: 100078
2010-04-01 03:05:45 +00:00
7c90d22f4c
vml[as] are slow on 1136jf-s also.
...
llvm-svn: 100066
2010-04-01 00:13:43 +00:00
503a0ef6f4
reduce indentation, minor cleanups.
...
llvm-svn: 100042
2010-03-31 20:32:51 +00:00
58ca0a649c
Use spaces, not tabs
...
llvm-svn: 100037
2010-03-31 20:05:12 +00:00
d749aefbd5
Comment the changes for r98218 and friends inside the source code.
...
llvm-svn: 100033
2010-03-31 18:48:58 +00:00
866f5764a7
Comment the changes for r98218 and friends inside the source code.
...
llvm-svn: 100031
2010-03-31 18:47:10 +00:00
4cd5866f8e
Fix PR6750. Don't try to merge a DomainValue with itself.
...
llvm-svn: 100016
2010-03-31 17:13:16 +00:00
9986ba954c
Replace V_SET0 with variants for each SSE execution domain.
...
llvm-svn: 99975
2010-03-31 00:40:13 +00:00
710c6892be
Fix typo. Thank you, valgrind.
...
llvm-svn: 99974
2010-03-31 00:40:08 +00:00
6f6ebb663c
Enable -sse-domain-fix by default. Now with tests!
...
llvm-svn: 99954
2010-03-30 22:47:00 +00:00
3493398f13
V_SETALLONES is an integer instruction.
...
Since it is just a pxor in disguise, we should probably expand it to a full
polymorphic triple.
llvm-svn: 99953
2010-03-30 22:46:55 +00:00
dbff4e8103
Renumber SSE execution domains for better code size.
...
SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.
llvm-svn: 99952
2010-03-30 22:46:53 +00:00
6f7fd28824
Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.
...
llvm-svn: 99948
2010-03-30 22:27:04 +00:00
cf35648ebe
Revert "Enable -sse-domain-fix by default. What could possibly go wrong?"
...
Not running 'make check-all' before committing is a bad idea.
llvm-svn: 99933
2010-03-30 21:36:32 +00:00
a654df84e6
Enable -sse-domain-fix by default. What could possibly go wrong?
...
llvm-svn: 99931
2010-03-30 21:09:31 +00:00
7460571381
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
...
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
llvm-svn: 99928
2010-03-30 20:55:56 +00:00
3b9af40938
Add cross-block inference to SSEDomainFix.
...
llvm-svn: 99916
2010-03-30 20:04:01 +00:00
6ad8167714
Remove the pmulld intrinsic and autoupdate it as a vector multiply.
...
Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.
llvm-svn: 99910
2010-03-30 18:49:01 +00:00
9897043928
Rip out the 'is temporary' nonsense from the MCContext interface to
...
create symbols. It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.
This fixes rdar://7807601.
llvm-svn: 99902
2010-03-30 18:10:53 +00:00
0c1dcb083e
XFAIL some PIC16 tests when running under valgrind-leaks. I don't expect these
...
to be fixed any time soon.
llvm-svn: 99888
2010-03-30 14:34:13 +00:00
7cc264bf19
PIC16: Plug a leak in PIC16Section by allocating name & address strings in the
...
MCContext. There is still one leak left in PIC16Section (the Items vector).
llvm-svn: 99887
2010-03-30 13:28:42 +00:00
c1ddaaf5b1
Add FIXME for operand promotion.
...
llvm-svn: 99859
2010-03-30 01:04:59 +00:00
486aa2eadc
Be gentle to MSVC. C++ is hard, after all.
...
llvm-svn: 99855
2010-03-30 00:09:32 +00:00
b551aa4da5
Basic implementation of SSEDomainFix pass.
...
Cross-block inference is primitive and wrong, but the pass is working otherwise.
llvm-svn: 99848
2010-03-29 23:24:21 +00:00
2788f797ca
Make isInt?? and isUint?? template specializations of the generic versions. This
...
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
llvm-svn: 99838
2010-03-29 21:13:41 +00:00
9bdadf0d99
We'll never match these as instructions, just as intrinsics so remove
...
the SDNodes.
llvm-svn: 99835
2010-03-29 20:41:51 +00:00
f633ba8213
Remove a bunch of integer width predicate functions in favor of MathExtras.
...
Most of these were unused, some of them were wrong and unused (isS16Constant<short>,
isS10Constant<short>).
llvm-svn: 99827
2010-03-29 19:07:58 +00:00
f60c556b91
From Kalle Raiskila:
...
"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."
llvm-svn: 99819
2010-03-29 17:38:47 +00:00
9bc1ed9962
add a note.
...
llvm-svn: 99815
2010-03-29 17:02:02 +00:00
c86256fa5d
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
...
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
2010-03-29 01:14:22 +00:00
11f85ccf7d
zap an extra line that Eli noticed!
...
llvm-svn: 99770
2010-03-28 18:52:28 +00:00
b7c48433df
fix a type contradition: XCoreISD::RETSP has one argument, not zero.
...
llvm-svn: 99760
2010-03-28 08:47:39 +00:00
505849d277
remove a pattern with no testcase that doesn't appear to be
...
matchable: it seems like it would always constant fold.
llvm-svn: 99758
2010-03-28 08:40:48 +00:00
3dad5fbeb9
fix integer negates to use the proper type for the zero vectors,
...
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
llvm-svn: 99757
2010-03-28 08:39:10 +00:00
240154e633
fix a typo, bitconvert from node to itself isn't valid.
...
llvm-svn: 99755
2010-03-28 08:36:45 +00:00
6c223ee0e9
fix vnot matching to explicitly specify the type of the
...
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
2010-03-28 08:08:07 +00:00
1c85e3476d
fix up vnot matching, eliminating a dead pattern, correcting a couple of
...
patterns that would never match because of bitcast, and eliminating use
of vnot_conv.
llvm-svn: 99753
2010-03-28 08:00:23 +00:00
e549d9b1f2
stop using vnot_conv
...
llvm-svn: 99750
2010-03-28 07:48:17 +00:00
227a83d6ed
revert r99743, this is saying that the repmovs instructinos have an
...
*input* of other type, which is the VT.
llvm-svn: 99749
2010-03-28 07:38:39 +00:00
be980f2df7
remove a bunch of dead patterns.
...
llvm-svn: 99748
2010-03-28 07:38:00 +00:00
cba70c8162
claiming to return other is pointless.
...
llvm-svn: 99743
2010-03-28 05:57:36 +00:00
a520b166dc
Improve systemz to model cmp and ucmp nodes as returning
...
their flags correctly.
llvm-svn: 99738
2010-03-28 05:21:52 +00:00
e83591c616
the FPCmp node returns an i32.
...
llvm-svn: 99737
2010-03-28 05:12:57 +00:00
ec5fe65838
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest
...
nodes all have an EFLAGS result when made by isel lowering.
llvm-svn: 99736
2010-03-28 05:07:17 +00:00
0f8a02830a
Fix indentation.
...
llvm-svn: 99705
2010-03-27 04:01:23 +00:00
cf603fb1c5
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
...
llvm-svn: 99704
2010-03-27 03:56:52 +00:00
07943af506
eliminate the last of the parallel's!
...
llvm-svn: 99700
2010-03-27 02:47:14 +00:00
6094cdab9f
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
...
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
2010-03-27 01:03:13 +00:00
c5e20d9031
eliminate almost all the rest of the x86-32 parallels.
...
llvm-svn: 99686
2010-03-27 00:45:04 +00:00
44313db557
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
...
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
llvm-svn: 99678
2010-03-27 00:09:12 +00:00
93acfbf441
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
...
to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
llvm-svn: 99676
2010-03-26 23:49:07 +00:00
0b57de3c4c
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
...
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
2010-03-26 22:28:56 +00:00
2cf04957c2
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
...
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
2010-03-26 21:26:28 +00:00
bf59859b2b
vldm/vstm can only do up to 16 double-word registers at a time.
...
Radar 7797856
llvm-svn: 99630
2010-03-26 18:41:09 +00:00
8fc94d6362
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
...
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
llvm-svn: 99628
2010-03-26 18:32:20 +00:00
3365fb1412
Do not sibcall if stack needs to be dynamically aligned.
...
llvm-svn: 99620
2010-03-26 16:26:03 +00:00
00a620c61e
Allow trivial sibcall of vararg callee when no arguments are being passed.
...
llvm-svn: 99598
2010-03-26 02:13:13 +00:00
5d4e917d9f
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
...
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
2010-03-26 01:07:59 +00:00
71fcb4fedd
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
...
Re-commit. This time complete with testsuite updates.
llvm-svn: 99570
2010-03-25 23:47:34 +00:00
42bb89c7d9
need to fix 'make check' tests first. revert for a moment.
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llvm-svn: 99569
2010-03-25 23:34:05 +00:00
7fce4e39aa
switch the flag for using NEON for SP floating point to a subtarget 'feature'
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llvm-svn: 99568
2010-03-25 23:32:19 +00:00
a3617ec88a
Removed instruction class NI from ARMInstrFormats.td.
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It doesn't seem to be used anywhere.
llvm-svn: 99566
2010-03-25 23:11:56 +00:00
a43386ba8f
switch the use-vml[as] instructions flag to a subtarget 'feature'
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llvm-svn: 99565
2010-03-25 23:11:16 +00:00
91d2774416
Add NVDupLnFrm and change NVDupLane class to use that format.
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llvm-svn: 99557
2010-03-25 21:49:12 +00:00
4b3b2ef65c
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
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llvm-svn: 99549
2010-03-25 20:48:50 +00:00
d82f9002e4
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
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expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
d919276bc0
Fix -Asserts warning, again.
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llvm-svn: 99542
2010-03-25 19:35:53 +00:00
3758ff917e
Tag SSE2 integer instructions as SSEPackedInt.
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llvm-svn: 99540
2010-03-25 18:52:04 +00:00
f8d7eda663
Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
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Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.
llvm-svn: 99539
2010-03-25 18:52:01 +00:00
49e121d5e4
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
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On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.
The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.
This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.
The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.
llvm-svn: 99524
2010-03-25 17:25:00 +00:00
45ab3f3ccf
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
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instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
e543e7fcb1
Reapply Kevin's change 94440, now that Chris has fixed the limitation on
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opcode values fitting in one byte (svn r99494).
llvm-svn: 99514
2010-03-25 16:36:14 +00:00
23bf99a97c
eliminate a bunch more parallels now that scheduling
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handles dead implicit results more aggressively. More
to come, I think this is now just a data entry problem.
llvm-svn: 99486
2010-03-25 05:44:01 +00:00
b07a29ecd4
Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this:
...
addl $12, %esp
popl %esi
popl %edi
popl %ebx
popl %ebp
jmpl *__Block_deallocator-L1$pb(%esi) # TAILCALL
The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.
The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.
llvm-svn: 99455
2010-03-25 00:10:31 +00:00
5b2da69f6d
Speculatively revert this to see if it fixes buildbot failures.
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--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 99450
2010-03-24 23:26:29 +00:00
f5584a7397
Added the Advanced Encryption Standard (AES) Instructions.
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llvm-svn: 99440
2010-03-24 22:33:33 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
b96eb68497
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
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not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
llvm-svn: 99435
2010-03-24 22:28:42 +00:00
2ceb288416
Per chris's request, add some comments.
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llvm-svn: 99434
2010-03-24 22:19:06 +00:00
bff23ca690
Trivial formating change.
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llvm-svn: 99428
2010-03-24 21:25:07 +00:00
583e05d8ce
BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.
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llvm-svn: 99423
2010-03-24 20:49:50 +00:00
e99953ce9c
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
da44d5977f
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
llvm-svn: 99409
2010-03-24 18:46:34 +00:00
07607382d8
tweak the arm if conversion heuristic
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llvm-svn: 99402
2010-03-24 16:15:14 +00:00
aa9b1c81a7
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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llvm-svn: 99376
2010-03-24 01:29:25 +00:00
9096bcdeda
Switch INC8r to defining its pattern in terms of X86inc_flag
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and defining the add pattern with Pat<>, eliminating a use of
parallel.
llvm-svn: 99375
2010-03-24 01:02:12 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
f9c8bec6c5
switch SDTBinaryArithWithFlags to be a multiple-result node as well.
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llvm-svn: 99370
2010-03-24 00:49:29 +00:00
db1ac3cf3e
Switch SDTUnaryArithWithFlags to being modeled as a two-result
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ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
llvm-svn: 99369
2010-03-24 00:47:47 +00:00
cca83a7aa4
remove 64-bit or_is_add parallels.
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llvm-svn: 99360
2010-03-24 00:16:52 +00:00
f5e5004327
remove useless or_is_add parallel's.
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llvm-svn: 99359
2010-03-24 00:15:23 +00:00
237d38e748
reduce nesting.
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llvm-svn: 99358
2010-03-24 00:12:57 +00:00
e0874fa02f
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
llvm-svn: 99355
2010-03-24 00:03:13 +00:00
a86ccbfe88
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."
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This reverts commit 99345. It was breaking buildbots.
llvm-svn: 99352
2010-03-23 23:48:51 +00:00
3d9ec39116
[llvm_void_ty] is no longer needed for result types,
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just use an empty result list.
llvm-svn: 99346
2010-03-23 23:46:07 +00:00
31da45b7af
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
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This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
llvm-svn: 99345
2010-03-23 23:14:44 +00:00
6a64320da8
Renamed NVdImmFrm to N1RegModImmFrm.
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llvm-svn: 99344
2010-03-23 23:09:14 +00:00
8a687233e3
Fix typo in the comment for N3VX class.
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llvm-svn: 99328
2010-03-23 21:35:03 +00:00
5be6d5a6a9
Add comment.
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llvm-svn: 99327
2010-03-23 21:30:12 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
020023a3fa
Add New NEON Format NVdVmImmFrm.
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llvm-svn: 99322
2010-03-23 20:40:44 +00:00
b6dee6e015
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?
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llvm-svn: 99320
2010-03-23 20:35:45 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
3968c6a252
Fix bad indentation, 80-column violations, and trailing whitespace.
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llvm-svn: 99295
2010-03-23 17:23:59 +00:00
ac5024bbeb
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
llvm-svn: 99288
2010-03-23 16:43:47 +00:00
9b680e21c0
Rename some instructions to match the corresponding NEON opcode.
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llvm-svn: 99266
2010-03-23 06:26:18 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
86face8333
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.
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llvm-svn: 99249
2010-03-23 03:13:05 +00:00
a9ae3ae698
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.
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llvm-svn: 99248
2010-03-23 02:36:58 +00:00
e0c43577c1
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.
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llvm-svn: 99245
2010-03-23 01:39:09 +00:00
e60e3ab624
Rename one more NEON instruction that I missed earlier.
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llvm-svn: 99201
2010-03-22 20:31:39 +00:00
c286c88db0
Regroup some instructions. No functional change.
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llvm-svn: 99192
2010-03-22 18:22:06 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
98bf5189d7
Remove some redundant instruction classes.
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llvm-svn: 99187
2010-03-22 18:02:38 +00:00
debe0bdb13
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
llvm-svn: 99185
2010-03-22 16:43:10 +00:00
5db5506093
Completely remove Blackfin patterns that thought JustCC was i1.
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Thanks, Chris!
llvm-svn: 99183
2010-03-22 16:30:04 +00:00
7d116ce2e3
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
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llvm-svn: 99182
2010-03-22 16:13:21 +00:00
fbd12cc36c
MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC.
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llvm-svn: 99102
2010-03-20 22:36:38 +00:00
fed917e078
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
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llvm-svn: 99097
2010-03-20 22:36:22 +00:00
162242b63b
pr6652: Use LDM to restore PC to the return address on ARMv4.
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Patch by John Tytgat!
llvm-svn: 99096
2010-03-20 22:20:40 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
59e5141d44
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
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address register writeback.
llvm-svn: 99094
2010-03-20 21:57:36 +00:00
b18adef4ad
Add variants of VST2, VST3 and VST4 with address register writeback, and
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rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
llvm-svn: 99093
2010-03-20 21:45:18 +00:00
89ba42c4ce
Add instructions for double-spaced VST3 and VST4 without address register
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writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99090
2010-03-20 21:15:48 +00:00
322cbff3d3
Add VST1 instructions with address register writeback.
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llvm-svn: 99083
2010-03-20 20:54:36 +00:00
9152d96dfb
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
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address register writeback.
llvm-svn: 99082
2010-03-20 20:47:18 +00:00
9b1584245a
Tidy some more comments and whitespace.
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llvm-svn: 99081
2010-03-20 20:39:53 +00:00
cf324658f6
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
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rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
llvm-svn: 99080
2010-03-20 20:10:51 +00:00
7ee900da22
Tidy some comments and whitespace for consistency.
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llvm-svn: 99078
2010-03-20 19:57:03 +00:00
c0795f8b87
Rename some instructions for consistency and sanity: use "_UPD" suffix for
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load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
2010-03-20 18:35:24 +00:00
d092669b48
Add instructions for double-spaced VLD3 and VLD4 without address register
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writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99065
2010-03-20 18:14:26 +00:00
496766cb56
Add VLD1 instructions with address register writeback.
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llvm-svn: 99062
2010-03-20 17:59:03 +00:00
73fc06f60f
PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*.
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llvm-svn: 99061
2010-03-20 17:41:18 +00:00
2497d85c9e
Revert the rest of 98679.
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--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
llvm-svn: 99049
2010-03-20 06:34:02 +00:00
614d1fdfc3
Fix a very bad typo. Since the register number was off by one, the ARM
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load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
llvm-svn: 99043
2010-03-20 06:05:13 +00:00
3f6f769c4f
If call result is in ST0 and it is not being passed to the caller's
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caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.
llvm-svn: 99032
2010-03-20 02:58:15 +00:00
f833fad813
Add NLdStFrm Format.
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llvm-svn: 99014
2010-03-20 00:17:00 +00:00
053e3510a3
Revert r98679. The disassembler will be updated to depend on the existence of
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IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
llvm-svn: 99013
2010-03-19 23:50:27 +00:00
e4191e719b
Revert this change, since it was causing ARM performance regressions.
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--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
8352941b34
remove the patterns that I commented out in r98930, Dan verified
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that they are dead.
llvm-svn: 99000
2010-03-19 21:43:36 +00:00
cf0843ed93
Fixed the encoding problems of the crc32 instructions. All had the Operand size
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override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
llvm-svn: 98980
2010-03-19 20:04:42 +00:00
c532697372
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
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llvm-svn: 98972
2010-03-19 18:07:48 +00:00
0dab68f3d0
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
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room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
llvm-svn: 98967
2010-03-19 17:39:00 +00:00
4d7c8645fd
MC: Add TargetAsmBackend::createObjectWriter.
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- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
llvm-svn: 98955
2010-03-19 10:43:26 +00:00
eaa367f5ae
MCCodeEmitter: Add target independent fixup flag for is-pc-relative.
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llvm-svn: 98954
2010-03-19 10:43:23 +00:00
c5084cccc8
MC: Add TargetAsmBackend::isVirtualSection hook.
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llvm-svn: 98950
2010-03-19 09:29:03 +00:00
f0517efc6c
MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.
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llvm-svn: 98947
2010-03-19 09:28:12 +00:00
22a411ff5b
Remove a memory leak from the CBackend.
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llvm-svn: 98941
2010-03-19 07:06:46 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
4822dfcc9a
Remove a memory leak from ThumbTargetMachine.
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llvm-svn: 98936
2010-03-19 05:25:28 +00:00
83aeaab462
add a new SDNPVariadic SDNP node flag, and use it in
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dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
llvm-svn: 98934
2010-03-19 05:07:09 +00:00
e5ac9382ce
remove some damaged sign extend patterns that can never match.
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llvm-svn: 98932
2010-03-19 04:53:47 +00:00
6d984166fc
disable some illegal blackfin patterns. sext from i32 to i32 can never
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match. Jakob, please take a look when you get a chance.
llvm-svn: 98931
2010-03-19 04:53:21 +00:00
607795f917
comment out a bunch of parallel store patterns that apparently
...
can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
llvm-svn: 98930
2010-03-19 04:14:21 +00:00
857955243e
Fix -Asserts warnings.
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llvm-svn: 98928
2010-03-19 03:18:23 +00:00
c9deca20e8
X86: Fix encoding for TEST64rr.
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llvm-svn: 98919
2010-03-19 01:15:03 +00:00
83facb0812
Now that tblgen can handle matching implicit defs of instructions
...
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
llvm-svn: 98903
2010-03-19 00:01:11 +00:00
a4d86b63c7
Update comment to refer to the right filename.
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llvm-svn: 98902
2010-03-18 23:57:57 +00:00
8e9b895c37
tidy up
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llvm-svn: 98901
2010-03-18 23:57:57 +00:00
f11aa9e7b4
Get rid of target-specific fp <-> int nodes when still I'm here.
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llvm-svn: 98889
2010-03-18 22:35:45 +00:00
64578d5599
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
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llvm-svn: 98888
2010-03-18 22:35:37 +00:00
422dd6608a
Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.
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llvm-svn: 98887
2010-03-18 22:35:02 +00:00
5e95aee159
Couple of changes that Dan mentioned for llvm.stackprotector fast-isel.
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llvm-svn: 98881
2010-03-18 21:58:33 +00:00
2ca1108254
X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we
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were missing it on some movq instructions and were not including the appropriate
PCrel bias.
llvm-svn: 98880
2010-03-18 21:53:54 +00:00
fb2ceede8f
fix some buggy ops concatentation
...
llvm-svn: 98869
2010-03-18 21:06:54 +00:00
983b479c91
use ins/outs.
...
llvm-svn: 98866
2010-03-18 20:55:18 +00:00
0204bc3de1
outs come before ins.
...
llvm-svn: 98864
2010-03-18 20:50:06 +00:00
52ecfdf3c5
Make fast-isel understand llvm.stackprotector.
...
llvm-svn: 98862
2010-03-18 20:27:26 +00:00
a7f236ae3a
Refactor NEON ld/st instructions to hardcode class arguments that are constants.
...
No functional changes.
llvm-svn: 98860
2010-03-18 20:18:39 +00:00
63ec093b6e
MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a
...
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
llvm-svn: 98858
2010-03-18 20:06:02 +00:00
b3f659c8c8
fix an x86-64 encoding bug Daniel found.
...
llvm-svn: 98855
2010-03-18 20:04:36 +00:00
a3a66b28b6
add a special relocation type for movq loads for object
...
files that produce special relocation types where the
linker changes movq's into lea's.
llvm-svn: 98839
2010-03-18 18:10:56 +00:00
eaceb9fd39
callq is pcrelative
...
llvm-svn: 98835
2010-03-18 17:52:22 +00:00
ce51f782dd
Check if function names start with "llvm." before trying to lookup them up as
...
intrinsics. The intrinsic lookup code assumes that this check has been done
and assumes the names are at least 6 characters long. Valgrind complained
about this. pr6638.
llvm-svn: 98831
2010-03-18 16:52:15 +00:00
4f67227625
Try to fix a valgrind error on 32 bit platforms: use %zu instead of %llu to format a size_t.
...
llvm-svn: 98819
2010-03-18 12:18:36 +00:00
bf724b9ee0
Turning off post-ra scheduling for x86. It isn't a consistent win.
...
llvm-svn: 98810
2010-03-18 06:55:42 +00:00
6544baff6f
MC/Darwin: Add a new target hook for whether the target uses "reliable" symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols.
...
Also, avoid some virtual call overhead.
llvm-svn: 98789
2010-03-18 00:58:53 +00:00
68333f5c6e
X86 address mode matching code MatchAddressRecursively does some aggressive hack which require doing a RAUW. It may end up deleting some SDNode up stream. It should avoid referencing deleted nodes.
...
llvm-svn: 98780
2010-03-17 23:58:35 +00:00
274a0d3794
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
...
There is a better way coming up.
llvm-svn: 98777
2010-03-17 23:26:50 +00:00
0910b5afac
Fixed a bug in the IT mask printing where T means the cond bit in the mask
...
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing. The disassembler also depends
on this arrangement. This is similar to what's described in A2.5.2 ITSTATE.
Ran:
utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2
successfully.
llvm-svn: 98775
2010-03-17 23:14:23 +00:00
8609782366
Refines 98745 so that it only contains the patch related to the output of the
...
addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.
This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp. It is used by disassembler as of now.
llvm-svn: 98774
2010-03-17 23:01:59 +00:00
a6fe21a79a
Clean up whitespace.
...
llvm-svn: 98769
2010-03-17 21:16:45 +00:00
69ba1bcd05
Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f
...
in svn r74988 but the format field was never widened.
llvm-svn: 98768
2010-03-17 21:13:43 +00:00
a4d1c8f59f
Initialize Size member to appease valgrind.
...
llvm-svn: 98763
2010-03-17 19:55:31 +00:00
6e81f67b09
98745 contains something unrelated to the patch.
...
Remove it from ARMAddressingModes.h.
llvm-svn: 98751
2010-03-17 18:32:39 +00:00
8f3004cff2
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
...
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98745
2010-03-17 17:52:21 +00:00
aed00fa039
fix GetOrCreateTemporarySymbol to require a name, clients
...
should use CreateTempSymbol() if they don't care about the
name.
llvm-svn: 98712
2010-03-17 05:41:18 +00:00
c7ba918b84
Revert 98683. It is breaking something in the disassembler.
...
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
c953bca10b
Remove redundant writeback flag from ARM address mode 6. Also remove the
...
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
8fce3dddfa
reapply r98656 unmodified, which exposed the asmprinter not
...
handling constant unions.
llvm-svn: 98680
2010-03-16 21:25:55 +00:00
71ab18bdd5
Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.
...
This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
llvm-svn: 98679
2010-03-16 21:25:05 +00:00
3a374da973
Revert r98656, its breaking all over the place.
...
llvm-svn: 98662
2010-03-16 19:35:34 +00:00
9ae99e0df5
improve support for uniontype and ConstantUnion, patch by Tim Northover!
...
llvm-svn: 98656
2010-03-16 19:15:03 +00:00
466d1e3dc2
Remove redundant writeback flag in ARM addressing mode 5.
...
llvm-svn: 98648
2010-03-16 18:38:09 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
ceda0780f9
Fix unused variable warnings.
...
llvm-svn: 98642
2010-03-16 17:44:45 +00:00
1b4e8cc69c
--- Reverse-merging r98637 into '.':
...
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm-svn: 98640
2010-03-16 16:59:47 +00:00
3d9327bd06
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
...
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98637
2010-03-16 16:36:54 +00:00
298a83ecfe
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
...
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.
llvm-svn: 98635
2010-03-16 16:19:07 +00:00
cf910439ee
fix the same bug on the x86-64 side of the fence.
...
llvm-svn: 98616
2010-03-16 06:39:08 +00:00
f5fec8fd8d
fix the encoding of TAILJMPd. This fixes Benchmarks/Olden/bisort
...
with the integrated assembler!
llvm-svn: 98615
2010-03-16 06:30:18 +00:00
ba75e81644
Wrap a long line and add some parens to be consistent.
...
llvm-svn: 98596
2010-03-16 00:31:15 +00:00
5599256415
MC: Allow modifiers in MCSymbolRefExpr, and eliminate X86MCTargetExpr.
...
- Although it would be nice to allow this decoupling, the assembler needs to be able to reason about MCSymbolRefExprs in too many places to make this viable. We can use a target specific encoding of the variant if this becomes an issue.
- This patch also extends llvm-mc to support parsing of the modifiers, as opposed to lumping them in with the symbol.
llvm-svn: 98592
2010-03-15 23:51:06 +00:00
c6ddebd6d1
Recognize code for doing vector gather/scatter index calculations with
...
32-bit indices. Instead of shuffling each element out of the index vector,
when all indices are needed, just store the input vector to the stack and
load the elements out.
llvm-svn: 98588
2010-03-15 23:23:03 +00:00
3f2293bc02
Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.
...
Radar 7459078.
llvm-svn: 98586
2010-03-15 23:09:18 +00:00
fe8d866fc7
MC/Mach-O/x86_64: Temporary labels in cstring sections require symbols (and external relocations, but we don't have x86_64 relocations yet).
...
llvm-svn: 98583
2010-03-15 21:56:50 +00:00
bbcaa40227
Now that the default for Darwin platforms is to place the LSDA into the TEXT
...
section, remove the target-specific code that performs this.
llvm-svn: 98580
2010-03-15 21:09:38 +00:00
c116a8707a
use Mang->getSymbol()
...
llvm-svn: 98578
2010-03-15 20:37:57 +00:00
0344874921
Place the LSDA into the TEXT section for x86 Darwin. If the global it's pointing
...
to is local to the translation unit, we need to place fill the value of that
symbol into the non-lazy pointer.
This should conclude all Darwin changes for placing the LSDA into the TEXT
section. There is some cleanup to do. I.e., there's no longer a special need for
target-specific code here. But that can come later.
llvm-svn: 98564
2010-03-15 19:04:37 +00:00
ae5edee6c8
Avoid sibcall optimization if either caller or callee is using sret semantics.
...
llvm-svn: 98561
2010-03-15 18:54:48 +00:00
eb319f36b9
do some serious surgery on CellSPU to get it back into a world
...
where it uses types consistently.
llvm-svn: 98532
2010-03-15 05:53:47 +00:00
26e6273772
fix a few more ambiguous types.
...
llvm-svn: 98531
2010-03-15 05:53:30 +00:00
4f26c1a960
add some missing types
...
llvm-svn: 98530
2010-03-15 05:35:37 +00:00
3ddd88f523
Tell Valgrind when we modify already-executed machine code so it knows
...
to re-instrument the code. We depend on the system valgrind.h to
avoid adding a new license.
llvm-svn: 98529
2010-03-15 04:57:55 +00:00
ce81b3c120
fix an ambiguous pattern, contrary to expectations, scalar_to_vector
...
doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.
llvm-svn: 98527
2010-03-15 00:52:43 +00:00
9fa851b9d4
tidy indentation
...
llvm-svn: 98523
2010-03-14 22:44:11 +00:00
402d6442c5
no really, all 64-bit cpu's have cmov support. This should
...
fix the rest of the buildbot failures on non-x86 hosts.
llvm-svn: 98522
2010-03-14 22:39:35 +00:00
77f7dba60c
all 64-bit cpus have cmov, this should fix CodeGen/X86/cmov.ll
...
(at least) on non-x86 builders.
llvm-svn: 98520
2010-03-14 22:24:34 +00:00
6a9e10905b
Fix jit encoding bugs.
...
llvm-svn: 98510
2010-03-14 19:28:34 +00:00
6feb7e3325
fix PR6605, X86ISD::CMP always returns i32 (EFLAGS), not
...
the operand type.
llvm-svn: 98507
2010-03-14 18:44:35 +00:00
0a65a37344
Add substarget feature for FP16
...
llvm-svn: 98503
2010-03-14 18:42:38 +00:00
d7fece38fc
Add codegen support for FP16 on ARM
...
llvm-svn: 98502
2010-03-14 18:42:31 +00:00
a30d4ce194
add support for pentium class CPUs which do not have cmov,
...
PR4841. Patch by Craig Smith!
llvm-svn: 98496
2010-03-14 18:31:44 +00:00
87dd2d6388
comment fix.
...
llvm-svn: 98494
2010-03-14 17:10:52 +00:00
28aae17fee
shrink 4-byte branches to 1-byte branches when lowering from
...
MachineInstr -> MCInst. This is what the assembler backend wants,
it relaxes from smaller to larger things. This fixes rdar://7750815
llvm-svn: 98493
2010-03-14 17:04:18 +00:00
6e52e9db31
get MMI out of the label uniquing business, just go to MCContext
...
to get unique assembler temporary labels.
llvm-svn: 98489
2010-03-14 08:36:50 +00:00
d5e8d9f29a
Now that DBG_LABEL is updated, we can finally make MachineMove
...
contain an MCSymbol instead of a label index.
llvm-svn: 98482
2010-03-14 08:12:40 +00:00
c26f44fb07
change the DBG_LABEL MachineInstr to always be created
...
with an MCSymbol instead of an immediate.
llvm-svn: 98481
2010-03-14 07:56:48 +00:00
1065f49ad9
switch GC_LABEL to use an MCSymbol operand instead of a label ID operand.
...
llvm-svn: 98474
2010-03-14 07:27:07 +00:00
d703df67ce
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
...
llvm-svn: 98465
2010-03-14 03:48:46 +00:00
ee2fbbc978
change the LabelSDNode to be EHLabelSDNode and make it hold
...
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
llvm-svn: 98463
2010-03-14 02:33:54 +00:00
34adc8d225
change EH related stuff (other than EH_LABEL) to use MCSymbol
...
instead of label ID's. This cleans up and regularizes a bunch
of code and makes way for future progress.
Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places. This is very sad and disturbing. :(
One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction. There should not be any
functionality change from doing this, but I'm not an EH expert.
llvm-svn: 98459
2010-03-14 01:41:15 +00:00
f3530bdd8a
X86_64: Fix encoding for the rest of the 64i32 instructions too.
...
llvm-svn: 98458
2010-03-13 22:57:53 +00:00
d324a7c990
X86: Fix ADD64i32 encoding.
...
llvm-svn: 98457
2010-03-13 22:49:39 +00:00
29bdac4928
eliminate the now-unneeded context argument of MBB::getSymbol()
...
llvm-svn: 98451
2010-03-13 21:04:28 +00:00
e468f88b26
rearrange MCContext ownership. Before LLVMTargetMachine created it
...
and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
llvm-svn: 98450
2010-03-13 20:55:24 +00:00
906a432031
MC/X86_64: Fix matching of leaq.
...
llvm-svn: 98444
2010-03-13 19:31:44 +00:00
e60c883bf4
MC/X86_64: Fix matching of callq.
...
llvm-svn: 98443
2010-03-13 19:31:38 +00:00
5bb8207c13
simplify some overly general code. The stack always grows down on x86.
...
llvm-svn: 98431
2010-03-13 08:04:35 +00:00
13f4db8c29
Fix another warning. There is a functionality change but I believe it's correct.
...
llvm-svn: 98430
2010-03-13 07:50:22 +00:00
f1e8f7ff7d
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
...
base register updating load/store-multiple instructions.
llvm-svn: 98427
2010-03-13 07:34:35 +00:00
81fe45d911
switch to the text section at the start of the .s file for darwin/x86
...
targets. This is a temporary hack for the .o file writer that Daniel
wants :)
llvm-svn: 98413
2010-03-13 02:10:00 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
18fc344290
MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing
...
other functionality on 403.gcc compiled at -O0.
llvm-svn: 98405
2010-03-13 00:47:29 +00:00
53149401ee
Combine the code to build VLDM and VSTM instructions, since they are
...
mostly the same.
llvm-svn: 98402
2010-03-13 00:43:32 +00:00
af10d27d80
Tidy up. No functional changes.
...
llvm-svn: 98398
2010-03-12 22:50:09 +00:00
27cce1c0b6
Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
...
llvm-svn: 98395
2010-03-12 22:00:08 +00:00
9eeda13a52
Fix LLVM build when the user specifies CPPFLAGS on the make command line.
...
llvm-svn: 98394
2010-03-12 21:42:14 +00:00
013f794dc0
remove special case code that isn't needed anymore.
...
llvm-svn: 98391
2010-03-12 21:21:19 +00:00
0b822ab447
inline GetGlobalValueSymbol into the rest its callers and
...
remove it.
llvm-svn: 98390
2010-03-12 21:19:23 +00:00
9e4cafe6f1
inline the now-trivial implementation of GetGlobalValueSymbol into
...
some of its callers.
llvm-svn: 98388
2010-03-12 21:09:07 +00:00
e80055f8fc
eliminate the X86 version of GetGlobalValueSymbol, allowing
...
it to be non-virtual and soon disappear.
llvm-svn: 98387
2010-03-12 21:06:41 +00:00
d3ca1e2854
prune #includes, this file should be removed pending hte cygwin stub issue being resolved.
...
llvm-svn: 98386
2010-03-12 21:04:31 +00:00
8d99c764d3
move fastcall/stdcall mangling up into Mangler.
...
llvm-svn: 98384
2010-03-12 21:03:47 +00:00
968b36a0bd
MC: Constify MCAsmLayout argument to MCExpr::EvaluteAs...
...
llvm-svn: 98380
2010-03-12 21:00:45 +00:00
c7b46f9d9c
give Mangler access to TargetData.
...
llvm-svn: 98378
2010-03-12 20:47:28 +00:00
892ac21f06
make DecorateCygMingName a static method.
...
llvm-svn: 98377
2010-03-12 20:43:52 +00:00
74026ffcae
minor tidying, only do work if a function is
...
actually X86_StdCall or X86_FastCall.
llvm-svn: 98374
2010-03-12 19:48:03 +00:00
e397df7af0
eliminate the string form of DecorateCygMingName
...
llvm-svn: 98373
2010-03-12 19:42:40 +00:00
c795a5235f
remove the FnArgWords cache to make way for future changes.
...
llvm-svn: 98372
2010-03-12 19:31:03 +00:00
3d0cd822a9
Add a beta-test for placing the LSDA into the TEXT section on X86.
...
llvm-svn: 98370
2010-03-12 19:20:40 +00:00
d19e302f77
Fix llc crash on invalid input.
...
llvm-svn: 98369
2010-03-12 19:18:30 +00:00
8abe1ce883
Remove some dead code. This method only gets called on
...
definitions.
llvm-svn: 98368
2010-03-12 19:14:18 +00:00
6428db5089
use Mang->getSymbol instead of duplicating the logic, reduce indentation.
...
llvm-svn: 98367
2010-03-12 19:04:14 +00:00
be3242b523
finally give Mangler a getSymbol method, which returns an MCSymbol
...
for a global instead of messing around with string buffers.
llvm-svn: 98366
2010-03-12 18:55:20 +00:00
d75813970a
simplify code to use OutContext.GetOrCreateTemporarySymbol with
...
no arguments instead of having to come up with a unique name.
This also makes the code less fragile.
llvm-svn: 98364
2010-03-12 18:47:50 +00:00
2eff505fba
make the mangler take an MCContext instead of an MAI.
...
No functionality change.
llvm-svn: 98363
2010-03-12 18:44:54 +00:00
d69ee90f2f
Use StringRef::substr instead of std::string::substr to avoid using a free'd
...
string temporary. This should fix PR6590.
llvm-svn: 98349
2010-03-12 13:54:59 +00:00
dd3fe94336
The same situation that effected ARM effects PPC with regards to placing the
...
LSDA into the TEXT section. We need to generate non-lazy pointers to it on
Mach-O. However, the object the NLP points to may be local to the translation
unit. If so, then the NLP needs to have the value of that object specified
instead of "0", which the linker interprets as "external".
llvm-svn: 98325
2010-03-12 02:00:43 +00:00
47bef1a8a2
make TargetLoweringObjectFile::getExprForDwarfReference
...
just make unnamed temp symbols instead of having to come
up with its own names.
llvm-svn: 98324
2010-03-12 01:56:43 +00:00
faec0815a3
MC-ize PPC's asm printing of stubs.
...
llvm-svn: 98300
2010-03-11 23:39:44 +00:00
03627cb12c
fix a fixme in TargetLoweringObjectFile::getExprForDwarfReference
...
where we used ot create an MCSymbol for ".". Now emit an assembler
temporary label and reference it instead of "." textually.
rdar://7739457
llvm-svn: 98292
2010-03-11 21:55:20 +00:00
576aec4363
Remove getWidenVectorType, which is no longer used.
...
llvm-svn: 98289
2010-03-11 21:39:57 +00:00
c1d1229d78
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
...
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
llvm-svn: 98285
2010-03-11 21:02:50 +00:00
00810c39da
revert r98270.
...
llvm-svn: 98281
2010-03-11 19:50:31 +00:00
2562356992
rename getSymbolForDwarf* to getExprForDwarf* since it returns
...
an MCExpr and not an MCSymbol. Change it to take an MCStreamer,
which is currently unused.
No functionality change.
llvm-svn: 98278
2010-03-11 19:41:58 +00:00
31fe835bf2
Bad bad bug. x86 force indirect tail call address into eax when it's meant to force it into a call preserved register instead. Change it to ecx for now.
...
llvm-svn: 98270
2010-03-11 18:49:14 +00:00
7aa06ac2b9
Remove dead code. (S|U)MUL_LO is now lowered to LMUL or MACC(S|U)
...
llvm-svn: 98269
2010-03-11 18:38:59 +00:00
4780109254
Add dag combine to simplify lmul(x, 0, a, b)
...
llvm-svn: 98258
2010-03-11 16:26:35 +00:00
29ffbf123f
Switch XCore over to using inline jump table entries.
...
llvm-svn: 98256
2010-03-11 14:58:56 +00:00
304f13c637
Have fast-isel understand llvm.objectsize. Update testcase for slightly
...
different codegen.
llvm-svn: 98244
2010-03-11 06:20:22 +00:00
ac8a95498a
MC: Sketch initial MCAsmLayout class, which encapsulates the current layout of an assembly file. The MCAsmLayout is also available for use by MCExpr::EvaluateAs{Absolute,Relocatable}, to allow target specific hooks and "absolutizing" of symbols.
...
llvm-svn: 98227
2010-03-11 02:28:59 +00:00
77c4141c8f
MC: Sketch some TargetAsmBackend hooks we are going to need.
...
llvm-svn: 98221
2010-03-11 01:34:21 +00:00
245f5b2810
MC: Provide the target triple to AsmBackend constructors.
...
llvm-svn: 98220
2010-03-11 01:34:16 +00:00
e8e79524d2
When outputing a non-lazy pointer for a stub, we may need to fill in the value
...
for the NLP because the object it's pointing to may be internal to the file.
This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:
GCC_except_tbl:
.long Lfoo-.
__ZTIA: @ This is local
...
Lfoo:
.long __ZTIA
LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.
llvm-svn: 98218
2010-03-11 01:18:13 +00:00
f5e81aeba5
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
...
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
llvm-svn: 98217
2010-03-11 01:13:36 +00:00
1b0e614b10
Fix ARM buildbot breakage.
...
llvm-svn: 98215
2010-03-11 00:46:22 +00:00
a179e4d0a8
add support, testcases, and dox for the new GHC calling
...
convention. Patch by David Terei!
llvm-svn: 98212
2010-03-11 00:22:57 +00:00
c499fae068
Lower small memcpys to load/stores on Thumb2.
...
Radar 7686922.
llvm-svn: 98210
2010-03-11 00:20:49 +00:00
963b233f2c
Work around a bug in the openbsd assembler on i386,
...
which doesn't support .quad correctly because it is
"really really old". PR6528.
Yet another reason the mc assembler should take over ;-)
llvm-svn: 98205
2010-03-11 00:06:19 +00:00
c4ceb1e2f8
Fix an obvious typo in an assert.
...
Patch by Sean Callanan.
llvm-svn: 98200
2010-03-10 22:38:45 +00:00
a810bdfcca
Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
...
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.
llvm-svn: 98199
2010-03-10 22:34:10 +00:00
49de0607a8
Progress towards shepherding debug info through SelectionDAG.
...
No functional effect yet. This is still evolving and should
not be viewed as final.
llvm-svn: 98195
2010-03-10 22:13:47 +00:00
1f6689a8ba
move PR6576 here.
...
llvm-svn: 98194
2010-03-10 21:42:42 +00:00
f0a7e8e77d
Make sure the LR gets pushed in functions that use vaargs. This fixes
...
400.perlbench for the nightly tests.
llvm-svn: 98183
2010-03-10 20:01:30 +00:00
77f781405d
comment why we use custom epilogue for t1 functions using vaargs.
...
llvm-svn: 98182
2010-03-10 19:59:47 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
66839831a7
The backend now makes a reasonable job of targeting lmul / macc
...
llvm-svn: 98169
2010-03-10 18:14:47 +00:00
54a2c32670
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
...
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
llvm-svn: 98168
2010-03-10 18:12:27 +00:00
c99b9b2193
Fix checking of intermediates having one use in isADDADDMUL
...
llvm-svn: 98164
2010-03-10 17:16:29 +00:00
5a457de4b2
Extract recognition of patterns such as add(add(mul(x,y),a),b)
...
into a seperate function.
llvm-svn: 98162
2010-03-10 17:10:35 +00:00
11ec7ee125
Fix thinko.
...
llvm-svn: 98158
2010-03-10 16:27:11 +00:00
1a396d53ed
Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate
...
results are unused elsewhere.
llvm-svn: 98157
2010-03-10 16:19:31 +00:00
f57aea3d38
Prefer LMUL to MACCU as LMUL has no tied operands.
...
llvm-svn: 98153
2010-03-10 13:27:10 +00:00
0012bc1e41
Custom lower (S|U)MUL_LOHI -> MACC(S|U)
...
llvm-svn: 98152
2010-03-10 13:20:07 +00:00
ef00c1bd6f
Fix indentation
...
llvm-svn: 98151
2010-03-10 11:42:05 +00:00
54dfa01adc
Lower add (mul a, b), c into MACCU / MACCS nodes which translate
...
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
llvm-svn: 98150
2010-03-10 11:41:08 +00:00
71c30c164f
move three lowering hooks from MAI to TLOF and make one of them
...
semantic instead of syntactic. This completes MCization of
darwin/x86[-64]!
llvm-svn: 98145
2010-03-10 07:20:42 +00:00
ac2361a9b0
set the temporary bit on MCSymbols correctly.
...
llvm-svn: 98124
2010-03-10 02:25:11 +00:00
e620178436
Clear up the last (famous last words) frame index value reuse issues for Thumb1.
...
llvm-svn: 98109
2010-03-10 00:13:42 +00:00
b70c2f795e
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
...
llvm-svn: 98098
2010-03-09 22:50:46 +00:00
f5b6a1118d
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
...
llvm-svn: 98097
2010-03-09 22:50:40 +00:00
fae913adf8
Change the Value argument to eliminateFrameIndex to a type-tagged value. This
...
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
llvm-svn: 98086
2010-03-09 21:45:49 +00:00
15804db55c
MSR (Move to Special Register from ARM core register) requires a mask to specify
...
what fields of the CPSR or SPSR are affected.
llvm-svn: 98085
2010-03-09 21:39:34 +00:00
90eab67320
The address of an indirect call must be in R12 on Darwin.
...
Make it so. (This patch is in LowerCall_Darwin, which seems
to be used by SVR4 code as well; since that doesn't belong here,
I haven't worried about this case.)
llvm-svn: 98077
2010-03-09 20:15:42 +00:00
31f275e63c
scavenged frame index value re-use gets confused when more than one base
...
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.
llvm-svn: 98071
2010-03-09 19:07:28 +00:00
9481181d40
The ARM EH experiment worked!
...
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.
llvm-svn: 98068
2010-03-09 18:31:07 +00:00
c420c4cb4e
In cases where the carry / borrow unused converted ladd / lsub
...
to an add or a sub.
llvm-svn: 98059
2010-03-09 16:34:25 +00:00
c5ff63d70f
Canonicalize ladd constant to RHS.
...
llvm-svn: 98058
2010-03-09 16:13:57 +00:00
f4e76cf44d
Add DAG combine for ladd / lsub.
...
llvm-svn: 98057
2010-03-09 16:07:47 +00:00
772952f46e
Don't try to fold V_SET0 and V_SETALLONES to loads in medium and
...
large code models.
llvm-svn: 98042
2010-03-09 03:01:40 +00:00
46ffefc66c
This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
...
bear with the awful code. It won't last in its current state beyond tonight.
llvm-svn: 98040
2010-03-09 02:46:12 +00:00
ffba5fafb6
Print blank line and clear stubs vector.
...
llvm-svn: 98019
2010-03-09 00:43:34 +00:00
f1eae222c9
MC-ize the stub printing in ARM.
...
llvm-svn: 98018
2010-03-09 00:40:17 +00:00
d802615d0c
don't reset defaults.
...
llvm-svn: 98004
2010-03-08 23:18:21 +00:00
0bfbd9b68c
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
...
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
llvm-svn: 98001
2010-03-08 22:56:15 +00:00
d2030e38a6
Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
...
for the encoding and is not the same as vmptrld.
llvm-svn: 97992
2010-03-08 22:17:26 +00:00
b59f7734b9
X86: Fix encoding for TEST{8,16,32}rr.
...
llvm-svn: 97982
2010-03-08 21:10:36 +00:00
3b548aa8e2
Avoid using DIDescriptor.isNull().
...
This is a first step towards eliminating checks in Descriptor constructors.
llvm-svn: 97975
2010-03-08 20:52:55 +00:00
bc97f6b757
Revert r97947.
...
llvm-svn: 97963
2010-03-08 19:20:38 +00:00
e77f993262
disambiguate some types, add a fixme about some
...
inconsistent intrinsics.
llvm-svn: 97959
2010-03-08 18:59:49 +00:00
d8045649a6
fix some more ambiguous patterns, remove another nontemporalstore
...
pattern which is broken (source and address swapped).
llvm-svn: 97958
2010-03-08 18:57:56 +00:00
a6d842fac0
Correct immediate sizes.
...
llvm-svn: 97957
2010-03-08 18:55:15 +00:00
6742f1f338
fix a type compatibility bug. imm is i32 in the input
...
pattern, not i64.
llvm-svn: 97956
2010-03-08 18:52:55 +00:00
b8a7427636
fix a bunch of partially ambiguous patterns on ARM. As an
...
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
2010-03-08 18:51:21 +00:00
dac58bd094
Fix a bunch of ambiguous patterns which tblgen happens to infer types
...
for, due to a bug.
llvm-svn: 97953
2010-03-08 18:44:04 +00:00
2b7ecfbe40
tidy up
...
llvm-svn: 97950
2010-03-08 18:29:38 +00:00
fe28599f6f
Avoid using DIDescriptor.isNull().
...
This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers.
llvm-svn: 97947
2010-03-08 18:25:48 +00:00
ca8d590c28
remove a non-temporal store pattern which is not tested and
...
could never have matched because the operand list was backwards.
llvm-svn: 97933
2010-03-08 03:18:28 +00:00
1fb4edc05d
Re-committing the failed r97807 commit with changes to eliminate warnings.
...
llvm-svn: 97891
2010-03-06 23:23:12 +00:00
c9c8b2713c
Describe what's going on with mingw alloca and why do we need separate instruction.
...
llvm-svn: 97888
2010-03-06 20:07:32 +00:00
bf16a17fc1
Initial bits of ARMv4-only support.
...
Patch by John Tytgat!
llvm-svn: 97886
2010-03-06 19:39:36 +00:00
d5e3fd6dc8
Lower dynamic stack allocation on mingw32 to separate instruction.
...
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.
llvm-svn: 97884
2010-03-06 19:32:29 +00:00
6f5523aa8b
Do not use '&' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).
...
This fixes PR6349
llvm-svn: 97877
2010-03-06 11:41:12 +00:00
29146d417e
clean this up.
...
llvm-svn: 97870
2010-03-06 07:02:28 +00:00
4279a078a5
revert r97807, it introduced build warnings.
...
llvm-svn: 97869
2010-03-06 04:32:46 +00:00
24c9b550b2
Thumb1 epilogue code generation needs to take into account that callee-saved
...
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.
llvm-svn: 97867
2010-03-06 03:28:39 +00:00
27494232d4
Fix typo.
...
llvm-svn: 97818
2010-03-05 19:55:55 +00:00
f0692603d5
fix bss section printing for cell, patch by Kalle Raiskila!
...
llvm-svn: 97814
2010-03-05 18:55:36 +00:00
34004170c5
Reworking the stack layout that the MicroBlaze backend generates.
...
The MicroBlaze backend was generating stack layouts that did not
conform correctly to the ABI. This update generates stack layouts
which are closer to what GCC does.
Variable arguments support was added as well but the stack layout
for varargs has not been finalized.
llvm-svn: 97807
2010-03-05 15:26:02 +00:00
654ec2a663
Fix an oops in x86 sibcall optimization. If the ByVal callee argument is itself passed as a pointer, then it's obviously not safe to do a tail call.
...
llvm-svn: 97797
2010-03-05 08:38:04 +00:00
cf67ffa500
Rever 96389 and 96990. They are causing some miscompilation that I do not fully understand.
...
llvm-svn: 97782
2010-03-05 03:08:23 +00:00
70e01cd001
Trivial comment change.
...
llvm-svn: 97776
2010-03-05 01:45:46 +00:00
543ce1f64a
Revert r97766. It's deleting a tag.
...
llvm-svn: 97768
2010-03-05 00:33:59 +00:00
6517f88f25
Micro-optimization:
...
This code:
float floatingPointComparison(float x, float y) {
double product = (double)x * y;
if (product == 0.0)
return product;
return product - 1.0;
}
produces this:
_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jne 0x00000004
0000000000000016 jp 0x00000002
0000000000000018 jmp 0x00000008
000000000000001a addsd 0x00000006(%rip),%xmm0
0000000000000022 cvtsd2ss %xmm0,%xmm0
0000000000000026 ret
The "jne/jp/jmp" sequence can be reduced to this instead:
_floatingPointComparison:
0000000000000000 cvtss2sd %xmm1,%xmm1
0000000000000004 cvtss2sd %xmm0,%xmm0
0000000000000008 mulsd %xmm1,%xmm0
000000000000000c pxor %xmm1,%xmm1
0000000000000010 ucomisd %xmm1,%xmm0
0000000000000014 jp 0x00000002
0000000000000016 je 0x00000008
0000000000000018 addsd 0x00000006(%rip),%xmm0
0000000000000020 cvtsd2ss %xmm0,%xmm0
0000000000000024 ret
for a savings of 2 bytes.
This xform can happen when we recognize that jne and jp jump to the same "true"
MBB, the unconditional jump would jump to the "false" MBB, and the "true" branch
is the fall-through MBB.
llvm-svn: 97766
2010-03-05 00:24:26 +00:00
ece1797542
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
...
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
llvm-svn: 97760
2010-03-04 22:24:41 +00:00
749ba9a7d5
pr6478: The frame pointer spill frame index is only defined when there is a
...
frame pointer.
llvm-svn: 97755
2010-03-04 21:42:36 +00:00
cf6e29a818
pr6480: Don't try producing ld/st-multiple instructions when the address is
...
an undef value. This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.
llvm-svn: 97745
2010-03-04 21:04:38 +00:00
af6ca23294
Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH.
...
These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.
Fix PR6489.
llvm-svn: 97742
2010-03-04 20:42:07 +00:00
b8ebd408da
Fix recognition of 16-bit bswap for C front-ends which emit the
...
clobber registers in a different order.
llvm-svn: 97741
2010-03-04 19:58:08 +00:00
795667b424
not committing what you test = bad.
...
llvm-svn: 97740
2010-03-04 19:54:45 +00:00
6ce8e24b70
make gep matching in fastisel match the base of the gep as a
...
register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.
llvm-svn: 97739
2010-03-04 19:48:19 +00:00
334db0ce7f
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
...
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0 ]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
llvm-svn: 97731
2010-03-04 17:40:44 +00:00
82cc53388e
add a comment.
...
llvm-svn: 97709
2010-03-04 01:43:43 +00:00
25a7b297ad
Teach the pic16 target to recognize pic16-*-* triples.
...
llvm-svn: 97691
2010-03-04 00:21:47 +00:00
1d63b9574d
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
...
MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
llvm-svn: 97675
2010-03-03 23:15:43 +00:00
a8e87d57be
Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that error. May not fix it in an ABI complient way. It wasn't clear what gcc does
...
llvm-svn: 97660
2010-03-03 20:15:31 +00:00
f1e25c7163
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
...
and STRHT for disassembly only.
llvm-svn: 97655
2010-03-03 18:45:36 +00:00
db42f3ef2b
remove nvload and two patterns that use it which are
...
better done by dag combine.
llvm-svn: 97633
2010-03-03 02:14:54 +00:00
f1ea86b567
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
...
for disassembly only.
llvm-svn: 97632
2010-03-03 02:09:43 +00:00
46897d35cb
factor the 'in the default address space' check out to a single
...
'dsload' pattern. tblgen doesn't check patterns to see if they're
textually identical. This allows better factoring.
llvm-svn: 97630
2010-03-03 01:52:59 +00:00
3fcbbd8673
factor the 'sign extended from 8 bit' patterns better so
...
that they are not destination type specific. This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.
llvm-svn: 97629
2010-03-03 01:45:01 +00:00
e9c46c25a1
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
...
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
llvm-svn: 97628
2010-03-03 01:44:33 +00:00
d8c50c67dc
Eliminate unused instruction classes.
...
llvm-svn: 97617
2010-03-03 00:43:15 +00:00
334af68052
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
...
disassembly only.
llvm-svn: 97614
2010-03-03 00:16:28 +00:00
8d63704021
merge two loops over all nodes in the graph into one.
...
llvm-svn: 97606
2010-03-02 23:12:51 +00:00
1eb6eb059c
eliminate PreprocessForRMW now that isel handles it.
...
We still preprocess calls and fp return stuff.
llvm-svn: 97598
2010-03-02 22:33:56 +00:00
71ddd8e2aa
remove 300 lines of code that is now dead in the MSP430 backend
...
now that isel handles chains more aggressively. This also
allows us to make isLegalToFold non-virtual.
llvm-svn: 97597
2010-03-02 22:30:08 +00:00
dd030701bd
Fix some issues in WalkChainUsers dealing with
...
CopyToReg/CopyFromReg/INLINEASM. These are annoying because
they have the same opcode before an after isel. Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.
With that done, give IsLegalToFold a new flag that causes it to
ignore chains. This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing. This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.
I currently #if out the dead code in the X86 backend and MSP
backend, I'll remove it for real in a follow-on patch.
The testcase changes are:
test/CodeGen/X86/sse3.ll: we generate better code
test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was
miscompiling this before, we now generate correct code
Convert it to filecheck while I'm at it.
test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
folding to make anton happy. :)
llvm-svn: 97596
2010-03-02 22:20:06 +00:00
7041f2cef6
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
...
llvm-svn: 97595
2010-03-02 22:11:06 +00:00
9dc2105478
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
...
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
llvm-svn: 97582
2010-03-02 19:38:59 +00:00
44908a5e17
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
...
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
0dae1cbf1c
AL is an optional mnemonic extension for always, except in IT instructions.
...
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
llvm-svn: 97571
2010-03-02 17:57:15 +00:00
d520eabcb9
Change some asm shift opcode strings to lowercase.
...
llvm-svn: 97567
2010-03-02 17:03:18 +00:00
09d9a690d2
fix typo add missing (
...
llvm-svn: 97565
2010-03-02 13:42:03 +00:00
b1baf6583e
Unbreak llvm-arm-linux buildbot and fix PR5309.
...
llvm-svn: 97564
2010-03-02 13:26:18 +00:00
f98f124a73
Sink InstructionSelect() out of each target into SDISel, and rename it
...
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
2010-03-02 06:34:30 +00:00
118dc6a645
Only save vector registers if we've defined for the vector registers.
...
Fixes PR5309.
llvm-svn: 97554
2010-03-02 06:25:00 +00:00
78c5b7a76d
Remove dead parameter passing.
...
llvm-svn: 97536
2010-03-02 01:55:18 +00:00
6f34abd092
Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,
...
respectively.
llvm-svn: 97531
2010-03-02 01:11:08 +00:00
bd6e193f54
remove a little hack I did for the old isel, not needed
...
now that it is gone.
llvm-svn: 97516
2010-03-01 22:51:11 +00:00
87d50aa18a
Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization.
...
llvm-svn: 97507
2010-03-01 22:00:11 +00:00
55ef1ebe52
remove a terrible hack that disabled assertions from this file because of build time
...
problems. rdar://7697850.
llvm-svn: 97500
2010-03-01 21:20:46 +00:00
3780ca6ef2
stop using generated sdnodexforms.
...
llvm-svn: 97485
2010-03-01 19:38:53 +00:00
718ed8a6d5
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
...
bit should be set to 0 instead of 1.
llvm-svn: 97481
2010-03-01 19:22:00 +00:00
b0e07d53c1
Add explicit keywords.
...
llvm-svn: 97460
2010-03-01 17:56:46 +00:00
312d604ee2
This is now done.
...
llvm-svn: 97450
2010-03-01 17:43:57 +00:00
42a5be5121
Add JIT support to the TODO list (test commit)
...
llvm-svn: 97443
2010-03-01 10:40:41 +00:00
abd56bde0e
80-col violations/trailing whitespace.
...
llvm-svn: 97427
2010-02-28 22:54:30 +00:00
56c50da3f6
remove redundant instruction.
...
llvm-svn: 97374
2010-02-28 07:23:21 +00:00
0d8a9af7b8
Add a flag to addPassesToEmit* to disable the Verifier pass run
...
after LSR, so that clients can opt in.
llvm-svn: 97357
2010-02-28 00:41:59 +00:00
bdd6405f29
Implement XMM subregs.
...
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.
Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.
llvm-svn: 97354
2010-02-28 00:17:42 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
f159afc951
remove a bogus pattern, which had the same pattern as STDU
...
but codegen'd differently. This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something. However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.
llvm-svn: 97345
2010-02-27 21:15:32 +00:00
a2075d44ad
fix an incorrect (overly conservative) predicate.
...
llvm-svn: 97316
2010-02-27 08:18:55 +00:00
228c31f045
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap.
...
llvm-svn: 97310
2010-02-27 07:36:59 +00:00
38e7bb6f34
Added the follwoing 32-bit Thumb instructions for disassembly only:
...
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
llvm-svn: 97276
2010-02-26 22:04:29 +00:00
17d54920d7
Merge PPC instructions FMRS and FMRD into a single FMR instruction.
...
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.
Also allow folding of memory operands on FMRSD.
llvm-svn: 97275
2010-02-26 21:53:24 +00:00
ddbf7a858e
Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().
...
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.
Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.
X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.
llvm-svn: 97262
2010-02-26 21:09:24 +00:00
dd33104203
Move dbg_value generation to target-independent FastISel,
...
as X86 is currently the only FastISel target. Per review.
llvm-svn: 97255
2010-02-26 20:01:55 +00:00
ef686dc38d
The cloner has nothing to do if any of the main or ISR entrypoints are not
...
present in the module.
llvm-svn: 97232
2010-02-26 18:32:18 +00:00
2bdbb3c167
Reapply things reverted back in 97220, with the fixed test case.
...
llvm-svn: 97228
2010-02-26 17:59:28 +00:00
952f6f98bb
movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq.
...
llvm-svn: 97227
2010-02-26 16:49:27 +00:00
333300e0df
Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.
...
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.
llvm-svn: 97226
2010-02-26 16:44:51 +00:00
663f658d87
Revert r97211 and r97213 to get the build green again.
...
llvm-svn: 97220
2010-02-26 08:43:09 +00:00
7828ff9535
Currently in LLVM, names of libcalls are assigned during TargetLowering
...
object construction. There is no provision to change them when the
code for a function generated.
So we have to change these names while printing assembly.
llvm-svn: 97213
2010-02-26 07:31:15 +00:00
528b1465e5
Before converting an operand to mem, check if it is legal to do so.
...
llvm-svn: 97211
2010-02-26 07:27:35 +00:00
9300486d68
Delete a bunch of redundant predicates.
...
llvm-svn: 97201
2010-02-26 01:14:30 +00:00
3adff378cc
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
...
and SRS.
llvm-svn: 97164
2010-02-25 20:25:24 +00:00
871e5b0926
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
...
llvm-svn: 97163
2010-02-25 19:05:29 +00:00
e285f70a42
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
...
llvm-svn: 97159
2010-02-25 18:46:43 +00:00
68e22cb5a0
Fix TextAlignFillValue in a few places
...
llvm-svn: 97151
2010-02-25 18:07:10 +00:00
74cca5a989
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
...
WFI, SEV, SETEND.
llvm-svn: 97149
2010-02-25 17:51:03 +00:00
9b80f86e5b
Revert r97064. Duncan pointed out that bitcasts are defined in
...
terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.
llvm-svn: 97137
2010-02-25 15:20:39 +00:00
ad117dac4b
Each field of auxiliary debug entry is only 1 byte long.
...
llvm-svn: 97108
2010-02-25 03:54:49 +00:00
90adefcf7e
Added tNOP for disassembly only.
...
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
ec4e1b67bf
Truncate from i64 to i32 is "free" on x86-32, because it involves
...
just discarding one of the registers.
llvm-svn: 97100
2010-02-25 03:04:36 +00:00
4a99c34873
Revert this patch for the time being. Needs more testing.
...
llvm-svn: 97099
2010-02-25 02:32:54 +00:00
57656da73f
Added tSVC and tTRAP for disassembly only.
...
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
0ab0ad93bd
Large stack frame patch for the CellSPU: handle stack frames that exceed 8176
...
(511*16) bytes register displacement (D-form).
NOTE: This is a potential headache, given the SPU's local core limitations,
allowing the software developer to commit stack overrun suicide unknowingly.
Also, large SPU stack frames will cause code size explosion. But, one presumes
that the software developer knows what they're doing...
Contributed by Kalle.Raiskila@nokia.com , edited slightly before commit.
llvm-svn: 97091
2010-02-25 01:53:17 +00:00
63af51c1c8
Create a stack frame on ARM when
...
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.
In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.
llvm-svn: 97071
2010-02-24 22:43:17 +00:00
ba8ac74fd9
Check for comparisons of +/- zero when optimizing less-than-or-equal and
...
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.
llvm-svn: 97065
2010-02-24 22:15:53 +00:00
4b2b48daba
Make getTypeSizeInBits work correctly for array types; it should return
...
the number of value bits, not the number of bits of allocation for in-memory
storage.
Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.
Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.
This fixes PR1784.
llvm-svn: 97064
2010-02-24 22:05:23 +00:00
05d9124625
Adding function "lookupGCCName" to MBlazeIntrinsicInfo
...
Adding the function "lookupGCCName" to the MBlazeIntrinsicInfo
class to support the Clang MicroBlaze target.
Additionally, minor fixes which remove some unused PIC code
(PIC is not supported yet in the MicroBlaze backend) and
removed some unused variables.
llvm-svn: 97054
2010-02-24 20:16:27 +00:00
86ba44a4c7
Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
...
A8.6.405
llvm-svn: 97052
2010-02-24 20:06:07 +00:00
0b94eb19e4
Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
...
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.
llvm-svn: 97046
2010-02-24 18:57:08 +00:00
03ac201ad9
Fixed typo of opcodestr, should be "vst1", not "vld1".
...
llvm-svn: 97044
2010-02-24 18:00:40 +00:00
4811d004be
Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again in
...
the hopes of fixing PPC bootstrap.
llvm-svn: 97040
2010-02-24 17:05:47 +00:00
3860521406
When forming SSE min and max nodes for UGE and ULE comparisons, it's
...
necessary to swap the operands to handle NaN and negative zero properly.
Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.
llvm-svn: 97025
2010-02-24 06:52:40 +00:00
f0485ed9ac
Remove an unused variable. Was this intentional?
...
llvm-svn: 97022
2010-02-24 06:09:03 +00:00
d5c472d811
Added for disassembly VST1 (multiple single elements) which stores elements to
...
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.
A8.6.391 & A8.6.393
llvm-svn: 97018
2010-02-24 02:57:20 +00:00
2921550485
handle very large call frames when require SPAdj != 0 for Thumb1
...
llvm-svn: 97013
2010-02-24 02:15:43 +00:00
6ad4bcb0da
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
...
Machine instruction selection is much happier when operands are in virtual
registers.
llvm-svn: 97012
2010-02-24 01:43:03 +00:00
328a607490
Re-apply 96540 and 96556 with fixes.
...
llvm-svn: 97011
2010-02-24 01:42:31 +00:00
a2d8c97b65
DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it
...
instead of %AL/%AH.
llvm-svn: 97006
2010-02-24 00:39:35 +00:00
da52f449a0
Fix rev 96389 by restricting the xform to mask that's either signbit or max signed value.
...
llvm-svn: 96990
2010-02-23 21:51:54 +00:00
00fb2ce233
Don't mark call instruction as a barrier.
...
llvm-svn: 96983
2010-02-23 21:08:11 +00:00
b14a5c52bc
Added for disassembly VLD1 (multiple single elements) which loads memory into
...
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
llvm-svn: 96980
2010-02-23 20:51:23 +00:00
3cc6673fd0
Use the module's context instead of the global context.
...
llvm-svn: 96977
2010-02-23 19:42:44 +00:00
8d7b4393d2
no need to override IsLegalToFold, the base implementation
...
disables load folding at -O0.
llvm-svn: 96973
2010-02-23 19:33:11 +00:00
e4801e49c9
Adding the MicroBlaze backend.
...
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze
The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.
llvm-svn: 96969
2010-02-23 19:15:24 +00:00
3a53f4e240
ECALLF, ECALLT shouldn't be marked as barriers.
...
llvm-svn: 96964
2010-02-23 18:29:49 +00:00
f81db146b4
Mark unconditional branches as barriers. Found using -verify-machineinstrs
...
llvm-svn: 96960
2010-02-23 18:13:38 +00:00
2f840382e2
Spelling. s/suppor /support /
...
llvm-svn: 96954
2010-02-23 17:16:27 +00:00
e3eb3105d9
Remove unused lowering function LowerJumpTable
...
llvm-svn: 96943
2010-02-23 14:17:20 +00:00
f578196968
Lower BR_JT on the XCore to a jump into a series of jump instructions.
...
llvm-svn: 96942
2010-02-23 13:25:07 +00:00
89f6ec462d
disable two patterns that are using non-sensical result pattern types.
...
llvm-svn: 96903
2010-02-23 07:21:15 +00:00
7489838a89
remove a confused pattern that is trying to match an address
...
then use it as an MMX register (!?).
llvm-svn: 96901
2010-02-23 07:16:12 +00:00
d17089231a
remove a bunch of dead named arguments in input patterns,
...
though some look dubious afaict, these are all ok.
llvm-svn: 96899
2010-02-23 06:54:29 +00:00
48370e14e7
fix a type mismatch in this pattern, where we were using an i64 imm in a
...
place where an i32 imm was required, the old isel just got lucky.
This fixes CodeGen/X86/x86-64-and-mask.ll
llvm-svn: 96894
2010-02-23 06:09:57 +00:00
c51b7198a9
reapply my cellspu changes with a fix to not break the old isel.
...
llvm-svn: 96885
2010-02-23 05:30:43 +00:00
7e5c4906dd
Revert 96854, 96852, and 96849, unbreaking test/CodeGen/CellSPU/i64ops.ll.
...
llvm-svn: 96871
2010-02-23 02:33:29 +00:00
a828850b4d
X86InstrInfoSSE.td declares PINSRW as having type v8i16,
...
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes. This fixes an x86 testcase.
llvm-svn: 96859
2010-02-23 02:07:48 +00:00
21dbd6f449
Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
...
(immediate #0 ) for disassembly only.
A8.6.283, A8.6.285, A8.6.287, A8.6.290
llvm-svn: 96856
2010-02-23 01:42:58 +00:00
22bc26e4cf
fix hte last cellspu failure.
...
llvm-svn: 96854
2010-02-23 01:37:39 +00:00
807666783c
hack around more crimes in instruction selection.
...
llvm-svn: 96852
2010-02-23 01:33:17 +00:00
fbbe2617dc
the cell backend is making all sorts of unsafe and incorrect assumptions
...
about ownership and update policies. It isn't clear why it is doing all
this lowering at isel time instead of in legalize. This fixes fcmp64.ll
llvm-svn: 96849
2010-02-23 01:20:00 +00:00
886915e3bb
Added VCEQ (immediate #0 ) NEON instruction for disassembly only.
...
A8.6.281
llvm-svn: 96838
2010-02-23 00:33:12 +00:00
45fceea0e4
Updated version of r96634 (which was reverted due to failing 176.gcc and
...
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
017a505716
Clean up a bit and fix for when SPAdj != 0
...
llvm-svn: 96818
2010-02-22 22:54:55 +00:00
15f6ed348f
The predicate index isn't fixed, so scan for it to make sure we get the proper
...
value.
Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.
llvm-svn: 96817
2010-02-22 22:47:46 +00:00
3ac438b920
remove dupes now.
...
llvm-svn: 96811
2010-02-22 22:15:05 +00:00
435611200b
move #includes earlier.
...
llvm-svn: 96810
2010-02-22 22:14:47 +00:00
5ddd4aca97
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD,
...
for disassembly only.
llvm-svn: 96806
2010-02-22 21:50:40 +00:00
9d4a3e2a7c
Added a bunch of instructions for disassembly only:
...
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual
llvm-svn: 96795
2010-02-22 18:50:54 +00:00
30ece5b807
Mark the return address stack slot as mutable when moving the return address
...
during a tail call. A parameter might overwrite this stack slot during the tail
call.
The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg
If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).
This fixes bug 6225.
llvm-svn: 96783
2010-02-22 16:18:09 +00:00
c1a545c307
Fix a typo in a comment.
...
llvm-svn: 96778
2010-02-22 04:09:26 +00:00
b87de8d30d
Remove the logic for reasoning about NaNs from the code that forms
...
SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.
Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.
llvm-svn: 96775
2010-02-22 04:03:39 +00:00
db8d6678e9
fix an incorrect VT: eflags is always i32. The bug was causing us to
...
create an X86ISD::Cmp node with result type i64 on the
CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it
downstream.
llvm-svn: 96768
2010-02-22 00:28:59 +00:00
40eb7f0991
MC/X86: Add stub AsmBackend.
...
llvm-svn: 96763
2010-02-21 21:54:14 +00:00
31a9212b0b
It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.
...
This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.
llvm-svn: 96755
2010-02-21 20:28:15 +00:00
455201ba71
Remove a bunch of duplicated code, where there was one version taking a std::ostream
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and another taking a raw_ostream, but otherwise identical. Use raw_ostream everywhere.
llvm-svn: 96746
2010-02-21 19:15:19 +00:00
e96503faa1
IT turns out that during jumpless setcc lowering eq and ne were swapped.
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This fixes PR6348
llvm-svn: 96734
2010-02-21 12:28:58 +00:00
3c29aff9ff
fix and un-xfail X86/vec_ss_load_fold.ll
...
llvm-svn: 96720
2010-02-21 04:53:34 +00:00
a07c9c7c56
Undo r96654. The printing of ARM shift instructions in canonical forms can be
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handled in ARMInstPrinter.cpp.
And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.
llvm-svn: 96719
2010-02-21 04:42:01 +00:00
18a32ce0f3
rename SelectScalarSSELoad -> SelectScalarSSELoadXXX and rewrite
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it to follow the mode needed by the new isel. Instead of returning
the input and output chains, it just returns the (currently only one,
which is a silly limitation) node that has input and output chains.
Since we want the old thing to still work, add a new
SelectScalarSSELoad to emulate the old interface. The XXX suffix
and the wrapper will eventually go away.
llvm-svn: 96715
2010-02-21 03:17:59 +00:00
986ab3fb1d
Eliminate some uses of immAllOnes, just use -1, it does
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the same thing and is more efficient for the matcher.
llvm-svn: 96712
2010-02-21 03:12:16 +00:00
fbc9d8d424
Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
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the armv6 nightly tests.
llvm-svn: 96691
2010-02-19 18:59:53 +00:00
7e47767763
Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254.
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Also, FileCheck'ize a test.
llvm-svn: 96686
2010-02-19 18:17:13 +00:00
336c0a1c87
Revert Anton's most recent EH patch (r96637), since it breaks a lot of
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ARM and Thumb tests.
llvm-svn: 96680
2010-02-19 17:10:59 +00:00
d0bf6f640f
Revert commits 96556 and 96640, because commit 96556 breaks the
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dragonegg self-host build. I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier. The
symptom of the 96556 miscompile is the following crash:
llvm[3]: Compiling AlphaISelLowering.cpp for Release build
cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
Stack dump:
0. Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
g++: Internal error: Aborted (program cc1plus)
This occurs when building LLVM using LLVM built by LLVM (via
dragonegg). Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM. Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.
Found by bisection.
r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines
Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines
Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.
e.g. On x86_64
%0 = icmp eq i32 %x, 0
%1 = icmp eq i32 %y, 0
%2 = xor i1 %1, %0
br i1 %2, label %bb, label %return
=>
testl %edi, %edi
sete %al
testl %esi, %esi
sete %cl
cmpb %al, %cl
je LBB1_2
llvm-svn: 96672
2010-02-19 11:30:41 +00:00
1ca8af9b76
Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints
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out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.
DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
asr r0, r0, #1
llvm-svn: 96654
2010-02-19 02:12:06 +00:00
9baeb02000
Use the same encoding for EH stuff uniformly on all MachO targets.
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This hopefulyl should unbreak EH on PPC/Darwin.
llvm-svn: 96637
2010-02-19 00:29:36 +00:00
aa34003f6f
Radar 7636153. In the presence of large call frames, it's not sufficient
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for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.
llvm-svn: 96634
2010-02-19 00:16:24 +00:00
688a90e2d7
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
...
llvm-svn: 96619
2010-02-18 22:31:18 +00:00
654528e8a7
Generate DBG_VALUE from dbg.value intrinsics. These currently
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comes out as comments but will eventually generate DWARF.
llvm-svn: 96601
2010-02-18 18:51:15 +00:00
a124a46748
Remap the call sites of a shared function in interrupt line functions.
...
llvm-svn: 96591
2010-02-18 18:00:35 +00:00
32db8a17c5
Re-factoring.
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llvm-svn: 96589
2010-02-18 17:32:25 +00:00
fd47c79774
add a missing type cast.
...
llvm-svn: 96574
2010-02-18 06:33:42 +00:00
c6c13a3515
Use NEON vmin/vmax instructions for floating-point selects.
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Radar 7461718.
llvm-svn: 96572
2010-02-18 06:05:53 +00:00
74c904589e
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
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of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.
llvm-svn: 96565
2010-02-18 03:27:42 +00:00
0ceb68a552
Some dag combiner goodness:
...
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"
llvm-svn: 96556
2010-02-18 02:13:50 +00:00
f3d79a5025
Added for disassembly only the variants of DMB, DSB, and ISB.
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llvm-svn: 96540
2010-02-18 00:19:08 +00:00
cb2deb2aaf
Remove the NEON N2VSInt instruction class: it's only used in one place and
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since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
llvm-svn: 96525
2010-02-17 22:42:54 +00:00
1d793a5e0e
Added CLREX (Clear-Exclusive) for disassembly only.
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A8.6.30
llvm-svn: 96523
2010-02-17 22:37:58 +00:00
004d280d5e
More cleanup for NEON:
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* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
llvm-svn: 96521
2010-02-17 22:23:11 +00:00
5454e0633e
Added RFE for disassembly only.
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B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
llvm-svn: 96519
2010-02-17 21:39:10 +00:00
34d6a4ff17
Remember to define super registers in mips calls.
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llvm-svn: 96504
2010-02-17 20:18:50 +00:00
bdceca6f49
"Fix and issue in SparcAsmPrinter where multiple identical .LLGETPCHn symbols could be emitted in the same file (it was uniqued by block number, but not by function number). " Patch by Nathan Keynes!
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llvm-svn: 96495
2010-02-17 18:57:19 +00:00
1fa9c2cce4
move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter,
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and add a sparc implementation that knows about delay slots. Patch by
Nathan Keynes!
llvm-svn: 96492
2010-02-17 18:52:56 +00:00
cb80e2527e
add a note, from PR5100
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llvm-svn: 96490
2010-02-17 18:42:24 +00:00
69346eb94f
Added routine to clone the body of a function and maintain a map of already
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cloned functions.
llvm-svn: 96485
2010-02-17 18:11:29 +00:00
81b3aa1b2f
Added a function to clone locals of a function.( which for pic16 are globals
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with mangled names).
llvm-svn: 96465
2010-02-17 06:48:50 +00:00
0f5c8f2339
Removed header files from .h by adding forward decls.
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Renamed PIC16FrameOverlay namespace to PIC16OVERLAY.
Renamed PIC16FrameOverlay class to PIC16Overlay.
llvm-svn: 96463
2010-02-17 06:46:23 +00:00
036b2f6542
Added BFI for disassembly only.
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A8.6.18 BFI - Bitfield insert (Encoding A1)
llvm-svn: 96462
2010-02-17 06:31:48 +00:00
3f48215480
rename and document some arguments so I don't have to keep
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reverse engineering what they are.
llvm-svn: 96456
2010-02-17 06:07:47 +00:00
cf1f5b0286
Use pointer-wide encoding for LSDA and FDE on Darwin.
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Hopefully, this will fix the remaining issues seen there.
llvm-svn: 96454
2010-02-17 05:53:11 +00:00
b67807e7ef
daniel remembered why this was needed.
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llvm-svn: 96440
2010-02-17 01:55:54 +00:00
d8716676ea
add a comment explaining why darwin/i386 uses ## as a comment.
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It's not clear why this is really required, but it was explicitly
added in r48808 with no real explanation or rdar #.
llvm-svn: 96438
2010-02-17 01:38:01 +00:00
84a85fcb91
Initial implementation of PIC16 Cloner pass.
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This pass is supposed to be run on the linked .bc module.
It traveses the module call graph twice. Once starting from the main function
and marking each reached function as "ML". Again, starting from the ISR
and cloning any reachable function that was marked as "ML". After cloning
the function, it remaps all the call sites in IL functions to call the
cloned functions.
Currently only marking is being done.
llvm-svn: 96435
2010-02-17 01:11:53 +00:00
12995ba3c0
Make the operand and format specifier match, and print all
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64 bits, fixing a variety of problems.
llvm-svn: 96421
2010-02-17 00:37:20 +00:00
9e89907ed5
Wrap lines to 80 columns and generally try to clean up whitespace and
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indentation. No functional changes.
llvm-svn: 96418
2010-02-17 00:31:29 +00:00
85e5081c77
Make error statement more personal.
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llvm-svn: 96410
2010-02-16 22:47:14 +00:00
afac7dad21
fix rdar://7653908, a crash on a case where we would fold a load
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into a roundss intrinsic, producing a cyclic dag. The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection. Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.
llvm-svn: 96408
2010-02-16 22:35:06 +00:00
37f106e18c
Handle tGPR register class in a few more places. This fixes some llvm-gcc
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build failures due to my fix for pr6111.
llvm-svn: 96402
2010-02-16 22:01:59 +00:00
4c444bf606
Add SMC (Secure Monitor Call) system instruction for disassembly only.
...
llvm-svn: 96401
2010-02-16 21:59:54 +00:00
1b967bf0e4
Really reserve R2 on PPC Darwin. PR 6314.
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llvm-svn: 96399
2010-02-16 21:53:27 +00:00
3e2cad3b1a
80 column cleanup
...
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
82b04130cb
Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)).
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If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).
Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335
llvm-svn: 96389
2010-02-16 21:09:44 +00:00
fba7fce5be
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
9641d06809
Add support for emitting non-temporal stores for DAGs marked
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non-temporal. Fix from r96241 for botched encoding of MOVNTDQ.
Add documentation for !nontemporal metadata.
Add a simpler movnt testcase.
llvm-svn: 96386
2010-02-16 20:50:18 +00:00
2284ddab56
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
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to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
2010-02-16 20:42:29 +00:00
756ab53e60
Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs.
...
llvm-svn: 96383
2010-02-16 20:35:59 +00:00
0a334d0df9
First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates.
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They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
llvm-svn: 96381
2010-02-16 20:17:57 +00:00
46c39d4f1f
Added for disassembly the following instructions:
...
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
llvm-svn: 96380
2010-02-16 20:04:27 +00:00
70aa8d0745
Fix pr6111: Avoid using the LR register for the target address of an indirect
...
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
llvm-svn: 96360
2010-02-16 17:24:15 +00:00
cbd43f89ac
Introduce isOpaqueTy and use it rather than isa<OpaqueType>. Also, move some
...
methods to try to have the type predicates be more logically positioned.
llvm-svn: 96349
2010-02-16 14:50:09 +00:00
19d0b47b1f
There are two ways of checking for a given type, for example isa<PointerType>(T)
...
and T->isPointerTy(). Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
2010-02-16 11:11:14 +00:00
d7d8afabd0
Minor warning fixes (semicolons, newline at EOF).
...
llvm-svn: 96343
2010-02-16 10:25:04 +00:00
52bfe24e2c
mark all the generated node predicates 'const'.
...
llvm-svn: 96337
2010-02-16 07:26:36 +00:00
4964ef88c2
make pcrel immediate values relative to the start of the field,
...
not the end of the field, fixing rdar://7651978
llvm-svn: 96330
2010-02-16 05:03:17 +00:00
adcee844ea
The code section for an ISR has a specific address.
...
Currently, whether a function is ISR or not is encoded in the section attribute for that function.
llvm-svn: 96322
2010-02-16 03:41:07 +00:00
af25cf825c
Drop support for the InReg attribute on the ppc backend. This was used by
...
llvm-gcc but has been replaced with pad argument which don't need any
special backend support.
llvm-svn: 96312
2010-02-16 01:50:18 +00:00
a945c64b5a
Put repeated empty pattern into the AQI instruction class.
...
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
llvm-svn: 96297
2010-02-15 23:43:47 +00:00
c9adb6a463
Fix a silly darwin-only typo introduced during merge.
...
llvm-svn: 96289
2010-02-15 22:38:10 +00:00
ab663a0bfe
Move TLOF implementations to libCodegen to resolve layering violation.
...
llvm-svn: 96288
2010-02-15 22:37:53 +00:00
397aecb6d6
Add suffix for stubs, so we won't have name clashes with private symbols.
...
llvm-svn: 96286
2010-02-15 22:36:26 +00:00
ae4ccc10da
Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there
...
llvm-svn: 96285
2010-02-15 22:35:59 +00:00
bcbaaba532
revert r96241. It breaks two regression tests, isn't documented,
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and the testcase needs improvement.
llvm-svn: 96265
2010-02-15 20:53:01 +00:00
5e73ff2e3a
Split SelectionDAGISel::IsLegalAndProfitableToFold to
...
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
2010-02-15 19:41:07 +00:00
63cedef74b
Add support for emitting non-temporal stores for DAGs marked
...
non-temporal.
llvm-svn: 96241
2010-02-15 17:02:56 +00:00
cbd39c5def
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96239
2010-02-15 16:57:43 +00:00
15478ac350
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96238
2010-02-15 16:57:13 +00:00
772fc34209
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96237
2010-02-15 16:57:02 +00:00
87a5abea33
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96236
2010-02-15 16:56:53 +00:00
2138b0fc90
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96235
2010-02-15 16:56:34 +00:00
27d044d65d
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96234
2010-02-15 16:56:22 +00:00
3cd87cc5ee
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96233
2010-02-15 16:56:10 +00:00
cfa68983e8
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96232
2010-02-15 16:55:58 +00:00
af2931d7bf
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96231
2010-02-15 16:55:37 +00:00
0d0149f5ac
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96230
2010-02-15 16:55:24 +00:00
e2e2073303
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96229
2010-02-15 16:55:07 +00:00
ff34702b04
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96228
2010-02-15 16:53:33 +00:00
68ea4da8cb
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96227
2010-02-15 16:49:52 +00:00
9dff9bec31
Uniformize the names of type predicates: rather than having isFloatTy and
...
isInteger, we now have isFloatTy and isIntegerTy. Requested by Chris!
llvm-svn: 96223
2010-02-15 16:12:20 +00:00
6b5e62fb0b
Fix changes from r75027
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llvm-svn: 96220
2010-02-15 15:00:44 +00:00
d4df64d15f
no need to add the instruction count anymore.
...
llvm-svn: 96212
2010-02-15 06:38:41 +00:00
4aa57ba3ef
mark "addr" as having type "iPTR", eliminating some type comparisons
...
in hte generated dag isel fil.
llvm-svn: 96193
2010-02-14 21:53:19 +00:00
d6cbe9f23f
fixes to pagesel/banksel inserter.
...
1. restore these across direct/indirect calls.
2. restore pagesel for any macros with gotos.
llvm-svn: 96175
2010-02-14 18:27:42 +00:00
0a5e0371b0
Forgot to commit the header
...
llvm-svn: 96174
2010-02-14 18:25:41 +00:00
ce77ce3072
Drop winmcasminfo and use normal AT&T COFF for all windows targets.
...
Otherwise AT&T asm printer is used with non-compatible MCAsmInfo and
there is no way to override this behaviour.
llvm-svn: 96165
2010-02-14 15:19:54 +00:00
c95a814ec3
Try to factorize the specification of saturating add/subtract operations a bit,
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as suggested by Bob Wilson.
llvm-svn: 96153
2010-02-14 06:32:20 +00:00
406cd61828
teach the encoder to handle pseudo instructions like FP_REG_KILL,
...
encoding them into nothing.
llvm-svn: 96110
2010-02-13 19:16:53 +00:00
2610a34b15
X86: Move extended MCFixupKinds into X86FixupKinds.h
...
llvm-svn: 96088
2010-02-13 09:27:52 +00:00
f83726f6ba
add encoder support and tests for rdtscp
...
llvm-svn: 96076
2010-02-13 03:42:24 +00:00
52a6ab3ba7
Add SETEND and BXJ instructions for disassembly only.
...
llvm-svn: 96075
2010-02-13 02:51:09 +00:00
4d804d794f
Added the rdtscp instruction to the x86 instruction
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tables.
llvm-svn: 96073
2010-02-13 02:06:11 +00:00
3b065cdb64
Teach MachineFrameInfo to track maximum alignment while stack objects are being
...
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
llvm-svn: 96069
2010-02-13 01:56:41 +00:00
44232af55a
Fixed encodings for invlpg, invept, and invvpid.
...
llvm-svn: 96065
2010-02-13 01:48:34 +00:00
b0208d2a06
Added a bunch of saturating add/subtract instructions for disassembly only.
...
llvm-svn: 96063
2010-02-13 01:21:01 +00:00
509154e0f9
rip out the 'heinous' x86 MCCodeEmitter implementation.
...
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.
llvm-svn: 96059
2010-02-13 00:49:29 +00:00
140caa7240
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs
...
fix swapgs to be spelled right.
llvm-svn: 96058
2010-02-13 00:41:14 +00:00
224340cabe
MC/X86: Push immediate operands as immediates not expressions when possible.
...
llvm-svn: 96055
2010-02-13 00:17:21 +00:00
064e926362
Remove special cases for [LM]FENCE, MONITOR and MWAIT from
...
encoder and decoder by using new MRM_ forms.
llvm-svn: 96048
2010-02-12 23:54:57 +00:00
1e827fd8ca
implement the rest of correct x86-64 encoder support for
...
rip-relative addresses, and add a testcase.
llvm-svn: 96040
2010-02-12 23:24:09 +00:00
626b79d6a6
Add the problem I just hacked around in 96015/96020.
...
The solution there produces correct code, but is seriously
deficient in several ways.
llvm-svn: 96039
2010-02-12 23:16:24 +00:00
741580a5bd
give MCCodeEmitters access to the current MCContext.
...
llvm-svn: 96038
2010-02-12 23:12:47 +00:00
4ad96055fb
implement infrastructure to support fixups for rip-rel
...
addressing. This isn't complete because I need an MCContext
to generate new MCExprs.
llvm-svn: 96036
2010-02-12 23:00:36 +00:00
29a9103ee6
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
...
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
llvm-svn: 96032
2010-02-12 22:53:19 +00:00
d18320361f
pull the rip-relative addressing mode case up early.
...
llvm-svn: 96031
2010-02-12 22:47:55 +00:00
6c1c0141be
fixme resolved!
...
llvm-svn: 96029
2010-02-12 22:39:06 +00:00
0055e75249
start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls.
...
llvm-svn: 96028
2010-02-12 22:36:47 +00:00
12455ca03d
enhance the immediate field encoding to know whether the immediate
...
is pc relative or not, mark call and branches as pcrel.
llvm-svn: 96026
2010-02-12 22:27:07 +00:00
439bda9d3f
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
...
llvm-svn: 96023
2010-02-12 22:17:21 +00:00
cb39340b81
This should have gone in with 26015, see comments there.
...
llvm-svn: 96020
2010-02-12 22:00:40 +00:00
dc2051c802
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
...
llvm-svn: 96019
2010-02-12 21:59:23 +00:00
26062150fa
When save/restoring CR at prolog/epilog, in a large
...
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.
SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.
Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.
llvm-svn: 96015
2010-02-12 21:35:34 +00:00
392be58cad
Add support for a union type in LLVM IR. Patch by Talin!
...
llvm-svn: 96011
2010-02-12 20:49:41 +00:00
bdf1b9520c
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
...
llvm-svn: 96010
2010-02-12 20:48:24 +00:00
cf20cbec49
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
...
llvm-svn: 95999
2010-02-12 18:55:33 +00:00
c3c357006e
Setup correct data layout to match gcc's expectations on mingw32.
...
llvm-svn: 95981
2010-02-12 15:28:56 +00:00
c9276dfe04
Cleanup stdcall / fastcall name mangling.
...
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
llvm-svn: 95980
2010-02-12 15:28:40 +00:00
f7477e599f
add a bunch of mod/rm encoding types for fixed mod/rm bytes.
...
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
llvm-svn: 95960
2010-02-12 02:06:33 +00:00
44ac89f517
revert r95949, it turns out that adding new prefixes is not a
...
great solution for the disassembler, we'll go with "plan b".
llvm-svn: 95957
2010-02-12 01:55:31 +00:00
905a2d7727
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
...
MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
2010-02-12 01:44:23 +00:00
d7e9212e2d
X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented
...
with "tied memory operands", which is wrong.
llvm-svn: 95950
2010-02-12 01:22:03 +00:00
336f9abb45
add another bit of space for new kinds of instruction prefixes.
...
llvm-svn: 95949
2010-02-12 01:15:16 +00:00
c780af6471
Add a missing pattern for movhps so that we get:
...
movq (%ecx,%edx,2), %xmm2
movhps (%ecx,%eax,2), %xmm2
rather than:
movq (%eax, %edx, 2), %xmm2
movq (%eax, %ebx, 2), %xmm3
movlhps %xmm3, %xmm2
Testcase forthcoming.
llvm-svn: 95948
2010-02-12 01:10:45 +00:00
1572e760bc
fix the encodings of monitor and mwait, which were completely
...
busted in both encoders. I'm not bothering to fix it in the
old one at this point.
llvm-svn: 95947
2010-02-12 01:06:22 +00:00
b1913c4df9
enhance llvm-mc -show-inst to print the enum of an instruction, like so:
...
testb %al, %al ## <MCInst #2412 TEST8rr
## <MCOperand Reg:2>
## <MCOperand Reg:2>>
jne LBB1_7 ## <MCInst #938 JNE_1
## <MCOperand Expr:(LBB1_7)>>
llvm-svn: 95935
2010-02-11 22:57:32 +00:00
524138176d
add a new MCInstPrinter::getOpcodeName interface, when it is
...
implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.
llvm-svn: 95929
2010-02-11 22:39:10 +00:00
b8af65ed0b
improve encoding information for branches. We now know they have
...
8 or 32-bit immediates, which allows the new encoder to handle
them.
llvm-svn: 95927
2010-02-11 21:45:31 +00:00
ddeceae839
make getFixupKindInfo return a const reference, allowing
...
the tables to be const. Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.
llvm-svn: 95924
2010-02-11 21:27:18 +00:00
2a34015abc
switch to target-indep fixups for 1/2/4/8 byte data.
...
llvm-svn: 95920
2010-02-11 21:17:54 +00:00
af88c0a84d
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
...
llvm-svn: 95916
2010-02-11 20:31:08 +00:00
1f298326b0
unbreak the build.
...
llvm-svn: 95915
2010-02-11 19:52:11 +00:00
2b0a7a2592
refactor the conditional jump instructions in the .td file to
...
use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
llvm-svn: 95901
2010-02-11 19:25:55 +00:00
3964059a16
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
...
Sorry!
llvm-svn: 95892
2010-02-11 18:47:03 +00:00
2588efd071
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
...
A8.6.297
llvm-svn: 95885
2010-02-11 18:17:16 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
9c13dfb5dd
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
...
as the "Permanently UNDEFINED" instruction.
llvm-svn: 95873
2010-02-11 17:14:31 +00:00
fbf1f02fee
dont' call getX86RegNum on X86::RIP, it doesn't like that. This
...
fixes the remaining x86-64 jit failures afaik.
llvm-svn: 95867
2010-02-11 08:45:56 +00:00
5a4ec879bf
fix a really nasty bug I introduced in r95693: r12 (and r12d,
...
r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.
This fixes x86-64 jit miscompilations of a bunch of programs.
llvm-svn: 95866
2010-02-11 08:41:21 +00:00
6bb2463f85
Add and commonize encoder support for all immediates.
...
Stub out some dummy fixups to make things work.
We can now emit fixups like this:
subl $20, %esp ## encoding: [0x83,0xec,A]
## fixup A - offset: 2, value: 20, kind: fixup_1byte_imm
Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which
should be producing an imm of 20, not an MCExpr of 20.
llvm-svn: 95860
2010-02-11 07:06:31 +00:00
167842f90b
generalize EmitDisplacementField to work with any size
...
and rename it to EmitImmediate.
llvm-svn: 95859
2010-02-11 06:54:23 +00:00
3555993312
eliminate the dead IsPCRel argument.
...
llvm-svn: 95858
2010-02-11 06:51:36 +00:00
5a40e6c95c
eliminate the dead "PCAdj" logic.
...
llvm-svn: 95857
2010-02-11 06:49:52 +00:00
5b77f0dac1
The previous fix of widening divides that trap was too fragile as it depends on custom
...
lowering and requires that certain types exist in ValueTypes.h. Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements. It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.
llvm-svn: 95823
2010-02-10 23:37:45 +00:00
4d4c6944e9
A few missed optimizations; the last one could have a significant impact on
...
code with lots of bitfields.
llvm-svn: 95809
2010-02-10 21:26:04 +00:00
3e0c9790f2
MC/X86 AsmMatcher: Fix a use after free spotted by d0k, and de-XFAIL
...
x86_32-encoding.s in on expectation of it passing.
llvm-svn: 95806
2010-02-10 21:19:28 +00:00
c7e14704d0
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
...
llvm-svn: 95784
2010-02-10 18:02:25 +00:00
4a618827de
Fix "the the" and similar typos.
...
llvm-svn: 95781
2010-02-10 16:03:48 +00:00
de03bd0ab4
emit some simple (and probably incorrect) fixups for symbolic
...
displacement values.
llvm-svn: 95773
2010-02-10 06:52:12 +00:00
f58d0074d7
keep track of what the current byte being emitted is
...
throughout the X86 encoder.
llvm-svn: 95771
2010-02-10 06:41:02 +00:00
a725d785a9
simplify displacement handling, emit displacements by-operand
...
even for the immediate case. No functionality change.
llvm-svn: 95770
2010-02-10 06:30:00 +00:00
605474463f
MC: Switch MCFixup to just hold an MCExpr pointer instead of index into the
...
MCInst it came from.
llvm-svn: 95767
2010-02-10 04:47:08 +00:00
ff68a42121
print all the newlines at the end of instructions with
...
OutStreamer.AddBlankLine instead of textually.
llvm-svn: 95734
2010-02-10 00:36:00 +00:00
a7c1d6cfd1
Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66
...
prefix which is part of the opcode encoding.
llvm-svn: 95729
2010-02-10 00:10:31 +00:00
482bf69bfe
Add ability for MCInstPrinters to add comments for instructions.
...
Enhance the x86 backend to show the hex values of immediates in
comments when they are large. For example:
movl $1072693248, 4(%esp) ## imm = 0x3FF00000
llvm-svn: 95728
2010-02-10 00:10:18 +00:00
509be1fe5e
TableGen fragment refactoring.
...
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files. We will use this for
the AVX specification to help with the transition from the current
SSE specification.
llvm-svn: 95727
2010-02-09 23:52:19 +00:00
1215c774f2
Add VBIF/VBIT for disassembly only.
...
A8.6.279
llvm-svn: 95713
2010-02-09 23:05:23 +00:00
0e42dc0dac
MC/X86: Add a dummy implementation of MCFixup generation for hacky X86 MCCodeEmitter.
...
llvm-svn: 95709
2010-02-09 23:00:03 +00:00
b311a6b3ae
MC: First cut at MCFixup, for getting fixup/relocation information out of an MCCodeEmitter.
...
llvm-svn: 95708
2010-02-09 22:59:55 +00:00
b618f66c5f
Added VMRS/VMSR for disassembly only.
...
A8.6.335 & A8.6.336
llvm-svn: 95703
2010-02-09 22:35:38 +00:00
8aef06f8eb
port encoder enhancements over to the new encoder.
...
llvm-svn: 95699
2010-02-09 21:57:34 +00:00
0c3b66cd87
fix X86 encoder to output [disp] only addresses with no SIB byte
...
in X86-32 mode. This is still required in x86-64 mode to avoid
forming [disp+rip] encoding. Rewrite the SIB byte decision logic
to be actually understandable.
llvm-svn: 95693
2010-02-09 21:47:19 +00:00
45d89644ae
revert r95689: getX86RegNum(BaseReg) != N86::ESP is
...
a confusing idiom to check for ESP or RSP.
llvm-svn: 95690
2010-02-09 21:21:26 +00:00
e464a4d815
simplify.
...
llvm-svn: 95689
2010-02-09 21:00:12 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
f7279bd10f
Radar 7417921
...
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
64e0ae8dd4
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
...
For disassembly only.
A8.6.300
llvm-svn: 95669
2010-02-09 17:21:56 +00:00
f5f335da37
move PR3462 to here.
...
llvm-svn: 95650
2010-02-09 05:55:14 +00:00
cf11e602a2
add a note from PR6194
...
llvm-svn: 95649
2010-02-09 05:45:29 +00:00
d00faaa9c7
Implement x86 asm parsing support for %st and %st(4)
...
llvm-svn: 95634
2010-02-09 00:49:22 +00:00
60db0a6ba5
pass stringref by value instead of by const&
...
llvm-svn: 95627
2010-02-09 00:34:28 +00:00
187242b3ab
move PR6212 to this file.
...
llvm-svn: 95624
2010-02-09 00:11:10 +00:00
08297ad15d
this is done, tested by CodeGen/ARM/iabs.ll
...
llvm-svn: 95609
2010-02-08 23:48:10 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
d9d7186dc0
unify the paths for external symbols and global variables:
...
2 files changed, 48 insertions(+), 83 deletions(-)
llvm-svn: 95599
2010-02-08 23:03:41 +00:00
99777dd78f
switch the rest of the "@ concatentation" logic in the X86
...
backend to use X86MCTargetExpr, simplifying a bunch of code.
llvm-svn: 95595
2010-02-08 22:52:47 +00:00
4d16049c61
Fixed the AT&T AsmLexer to report the proper strings
...
for register tokens. Before, if it encountered
'%al,' it would report 'al,' as the token. Now it
correctly reports '%al'.
llvm-svn: 95594
2010-02-08 22:50:23 +00:00
b8479fb309
switch ELF @GOTOFF references to use X86MCTargetExpr.
...
llvm-svn: 95593
2010-02-08 22:33:55 +00:00
b6b2164e28
add an x86 implementation of MCTargetExpr for
...
representing @GOT and friends. Use it for
personality references as a first use.
llvm-svn: 95588
2010-02-08 22:09:08 +00:00
9e60686a83
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
...
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
llvm-svn: 95584
2010-02-08 22:02:41 +00:00
3464a5b609
Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect
...
its current purpose.
llvm-svn: 95564
2010-02-08 20:27:50 +00:00
beb1238a85
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
...
llvm-svn: 95560
2010-02-08 19:41:48 +00:00
c7e606f132
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
...
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
llvm-svn: 95548
2010-02-08 17:26:09 +00:00
6e29e9d262
Fix x86 JIT stub on MSVC.
...
Thanks to Kristaps Straupe for noticing the bug.
llvm-svn: 95537
2010-02-08 08:37:27 +00:00
d59cddc098
Add suport for VASTART on Mips.
...
llvm-svn: 95506
2010-02-06 21:00:02 +00:00
d6fff557db
First step towards varargs support in Mips:
...
- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.
llvm-svn: 95500
2010-02-06 19:20:49 +00:00
ea5c6be766
Run codegen dce pass for all targets at all optimization levels. Previously it's
...
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.
llvm-svn: 95493
2010-02-06 09:07:11 +00:00
4536b9a904
Fix alignment on ppc linux. This fixes the build of crtend.o
...
llvm-svn: 95477
2010-02-06 03:32:21 +00:00
d064aefefc
Do not emit callseq instructions around sibcalls. This eliminated some unnecessary stack adjustments.
...
llvm-svn: 95475
2010-02-06 03:28:46 +00:00
74bb06c0f0
Reintroduce the InlineHint function attribute.
...
This time it's for real! I am going to hook this up in the frontends as well.
The inliner has some experimental heuristics for dealing with the inline hint.
When given a -respect-inlinehint option, functions marked with the inline
keyword are given a threshold just above the default for -O3.
We need some experiments to determine if that is the right thing to do.
llvm-svn: 95466
2010-02-06 01:16:28 +00:00
5638c36efd
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
...
Radar 7614112.
llvm-svn: 95456
2010-02-06 00:24:38 +00:00
9d624778a3
fix incorrect encoding of SBB8mi that Kevin noticed.
...
llvm-svn: 95448
2010-02-05 22:56:11 +00:00
d91f302a05
fix a case where we'd mis-encode fisttp because of an incorrect (and
...
redundant with a correct one) pattern that was added for the disassembler.
llvm-svn: 95446
2010-02-05 22:49:06 +00:00
a60af09414
add note.
...
llvm-svn: 95445
2010-02-05 22:48:33 +00:00
58827ff98e
port X86InstrInfo::determineREX over to the new encoder.
...
llvm-svn: 95440
2010-02-05 22:10:22 +00:00
9c9453e582
wire up 64-bit MCCodeEmitter.
...
llvm-svn: 95438
2010-02-05 21:51:35 +00:00
86bd194234
really kill off the last MRMInitReg inst, remove logic from encoder.
...
llvm-svn: 95437
2010-02-05 21:34:18 +00:00
e96d534ce0
lower the last of the MRMInitReg instructions in MCInstLower.
...
llvm-svn: 95435
2010-02-05 21:30:49 +00:00
90916287ed
teach X86MCInstLower to lower the MOV32r0 and MOV8r0
...
pseudo instructions.
llvm-svn: 95433
2010-02-05 21:21:06 +00:00
fd7976a432
genericize helpers, use them for MOV16r0/MOV64r0
...
llvm-svn: 95432
2010-02-05 21:15:57 +00:00
340b542f8b
factor code better in X86MCInstLower::Lower, teach it to
...
lower the SETB* instructions.
llvm-svn: 95431
2010-02-05 21:13:48 +00:00
89f7dfff21
implement the rest of the encoding types.
...
llvm-svn: 95414
2010-02-05 19:37:31 +00:00
503243559a
move functions for decoding X86II values into the X86II namespace.
...
llvm-svn: 95410
2010-02-05 19:24:13 +00:00
342762fdba
constant propagate a method away.
...
llvm-svn: 95408
2010-02-05 19:20:30 +00:00
b8d375fd21
change getSizeOfImm and getBaseOpcodeFor to just take
...
TSFlags directly instead of a TargetInstrDesc.
llvm-svn: 95405
2010-02-05 19:16:26 +00:00
37166eb419
add some more encodings.
...
llvm-svn: 95403
2010-02-05 19:04:37 +00:00
a778db9a91
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
...
llvm-svn: 95397
2010-02-05 18:04:58 +00:00
df84b1aa50
implement the non-relocation forms of memory operands
...
llvm-svn: 95368
2010-02-05 06:16:07 +00:00
a366c61f77
Handle tail call with byval arguments.
...
llvm-svn: 95351
2010-02-05 02:21:12 +00:00
610c84a7c2
start adding MRMDestMem, which requires memory form mod/rm encoding
...
to start limping.
llvm-svn: 95350
2010-02-05 02:18:40 +00:00
4f627ba89f
Add a few more encodings, we can now encode all of:
...
pushl %ebp
movl %esp, %ebp
movl $42, %eax
popl %ebp
ret
llvm-svn: 95344
2010-02-05 01:53:19 +00:00
ee9d33b4e7
Disable external stubs for X86-32 and X86-64
...
Instruction selection for X86 now can choose an instruction
sequence that will fit any address of any symbol, no matter
the pointer width. X86-64 uses a mov+call-via-reg sequence
for this.
llvm-svn: 95323
2010-02-04 19:56:59 +00:00
fb5670fc16
move the PR6214 microoptzn to this file.
...
llvm-svn: 95299
2010-02-04 07:32:01 +00:00
aeba2250a5
Re-enable x86 tail call optimization.
...
llvm-svn: 95295
2010-02-04 06:47:24 +00:00
8228b11abc
add support for the sparcv9-*-* target triple to turn on
...
64-bit sparc codegen. Patch by Nathan Keynes!
llvm-svn: 95293
2010-02-04 06:34:01 +00:00
9976832a05
Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen.
...
This fixes 483.xalancbmk (with tail call opt).
llvm-svn: 95280
2010-02-04 02:40:39 +00:00
c337d6538a
Rewrite FP constant handling in DEBUG_VALUE yet
...
again, so it more or less handles long double.
Restore \n removed in latest MC frenzy.
llvm-svn: 95271
2010-02-04 01:33:43 +00:00
223084d3ac
enhance new encoder to support prefixes + RawFrm
...
instructions with no operands. It can now handle
define void @test2() nounwind { ret void }
llvm-svn: 95261
2010-02-03 21:57:59 +00:00
6794f9b9f6
set up some infrastructure, some minor cleanups.
...
llvm-svn: 95260
2010-02-03 21:43:43 +00:00
f4139067ee
Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue.
...
llvm-svn: 95259
2010-02-03 21:40:40 +00:00
f914be06d2
stub out a new X86 encoder, which can be tried with
...
-enable-new-x86-encoder until its stable.
llvm-svn: 95256
2010-02-03 21:24:49 +00:00
2f750f3b5a
rename createX86MCCodeEmitter to more accurately reflect what it creates.
...
llvm-svn: 95254
2010-02-03 21:14:33 +00:00
00f1e6c030
Added support for X86 instruction prefixes so llvm-mc can assemble them. The
...
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.
llvm-svn: 95252
2010-02-03 21:04:42 +00:00
3bcbdb8a28
reapply r95206, this time actually delete the code I'm replacing in the third stub case.
...
llvm-svn: 95209
2010-02-03 06:42:38 +00:00
37fad99a05
revert r95206, it is apparently causing bootstrap failure on i386-darwin9
...
llvm-svn: 95208
2010-02-03 06:41:18 +00:00
3eef965b06
make the x86 backend emit darwin stubs through mcstreamer
...
instead of textually.
llvm-svn: 95206
2010-02-03 06:21:16 +00:00
082f484074
make MachineModuleInfoMachO hold non-const MCSymbol*'s instead
...
of const ones. non-const ones aren't very useful, because you can't
even, say, emit them.
llvm-svn: 95205
2010-02-03 06:18:30 +00:00
40905b4302
Allow all types of callee's to be tail called. But avoid automatic tailcall if the callee is a result of bitcast to avoid losing necessary zext / sext etc.
...
llvm-svn: 95195
2010-02-03 03:28:02 +00:00
0b78cc2af5
don't emit \n's at the start of X86AsmPrinter::runOnMachineFunction,
...
.o files don't like that.
llvm-svn: 95187
2010-02-03 01:49:49 +00:00
aaa1db66a1
rename printMachineInstruction -> EmitInstruction
...
llvm-svn: 95184
2010-02-03 01:41:03 +00:00
6f1f865fba
print instructions through the mcstreamer.
...
llvm-svn: 95181
2010-02-03 01:16:28 +00:00
402a111318
emit instructions through the streamer.
...
llvm-svn: 95180
2010-02-03 01:15:03 +00:00
183ef68ef7
Finally eliminate printMCInst and send instructions through
...
the streamer. Demo:
$ cat t.ll
define i32 @test() nounwind {
ret i32 42
}
$ llc t.ll -o -
...
_test:
movl $42, %eax
ret
$ llc t.ll -o t.o -filetype=obj
$ otool -tv t.o
t.o:
(__TEXT,__text) section
_test:
00000000 movl $0x0000002a,%eax
00000005 ret
llvm-svn: 95179
2010-02-03 01:13:25 +00:00
996ec840d0
rejigger the world so that EmitInstruction prints the \n at
...
the end of the instruction instead of expecting the caller to
do it. This currently causes the asm-verbose instruction
comments to be on the next line.
llvm-svn: 95178
2010-02-03 01:09:55 +00:00
41ad1905c9
sink handling of target-independent machine instrs (other
...
than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp
file. This allows elimination of the
NO_ASM_WRITER_BOILERPLATE hack among other things.
llvm-svn: 95177
2010-02-03 01:00:52 +00:00
55e768c99a
Print FPImm a less kludgy way; APFloat.toString seems
...
to have some problems anyway.
llvm-svn: 95171
2010-02-03 00:36:40 +00:00
5f238a9650
ByVal frame object size should be that of the byval argument, not the size of the type which is just a pointer. This is not known to break stuff but is wrong nevertheless.
...
llvm-svn: 95163
2010-02-02 23:58:13 +00:00
d0a2f52f8f
As of r79039, we still try to eliminate the frame pointer on leaf functions,
...
even when -disable-fp-elim is specified.
llvm-svn: 95161
2010-02-02 23:56:14 +00:00
6f36a083ef
Revert 95130.
...
llvm-svn: 95160
2010-02-02 23:55:14 +00:00
b3cfc2b77c
Accept floating point immediates in DEBUG_VALUE.
...
llvm-svn: 95159
2010-02-02 23:54:23 +00:00
bdbffbedf0
AsmParser/X86: Add temporary hack to allow parsing "sal". Eventually we need
...
some mechanism for specifying alternative syntaxes, but I'm not sure what form
that should take yet.
llvm-svn: 95158
2010-02-02 23:46:47 +00:00
b0d44c3807
refactor code so that LLVMTargetMachine creates the asmstreamer and
...
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
llvm-svn: 95155
2010-02-02 23:37:42 +00:00
f46359642f
tidy some targets.
...
llvm-svn: 95146
2010-02-02 22:13:21 +00:00
6a6137832d
remove dead code.
...
llvm-svn: 95144
2010-02-02 22:03:00 +00:00
308acc4ab0
detemplatize the ppc code emitter.
...
llvm-svn: 95142
2010-02-02 21:55:58 +00:00
a3fa43932d
remove dead code.
...
llvm-svn: 95141
2010-02-02 21:52:03 +00:00
e8565d8eaf
add a definition for ID.
...
llvm-svn: 95140
2010-02-02 21:49:29 +00:00
8d806876c0
detemplatize ARM code emitter.
...
llvm-svn: 95138
2010-02-02 21:48:51 +00:00
3184f22447
MCAsmParser/X86: Represent absolute memory operands as CodeGen does, with scale
...
== 1.
llvm-svn: 95137
2010-02-02 21:44:16 +00:00
d28d6db735
MCCodeEmitter/X86: Handle tied registers better when converting MCInst ->
...
MCMachineInstr. This also fixes handling of tied registers for MRMSrcMem
instructions.
llvm-svn: 95136
2010-02-02 21:44:10 +00:00
c83cfb9dfa
remove dead code.
...
llvm-svn: 95134
2010-02-02 21:38:59 +00:00
4578098b97
detemplatize alpha code emission, it is now JIT specific.
...
llvm-svn: 95133
2010-02-02 21:35:47 +00:00
0cd6c2a047
eliminate all the dead addSimpleCodeEmitter implementations.
...
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
llvm-svn: 95131
2010-02-02 21:31:47 +00:00
c1b0116ff1
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
...
llvm-svn: 95130
2010-02-02 21:29:10 +00:00
f0cb12acf2
eliminate FileModel::Model, just use CodeGenFileType. The client
...
of the code generator shouldn't care what object format a target
uses.
llvm-svn: 95124
2010-02-02 21:06:45 +00:00
29e0702dc8
remove the remnants of TargetMachOWriterInfo.
...
llvm-svn: 95114
2010-02-02 19:41:23 +00:00
8487d65ea2
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
...
llvm-svn: 95112
2010-02-02 19:31:58 +00:00
d1e821f7eb
remove PPCMachOWriterInfo.
...
llvm-svn: 95111
2010-02-02 19:23:55 +00:00
55afd2564c
Perform sibcall in some cases when arguments are passes memory. Look for cases
...
where callee's arguments are already in the caller's own caller's stack and
they line up perfectly. e.g.
extern int foo(int a, int b, int c);
int bar(int a, int b, int c) {
return foo(a, b, c);
}
llvm-svn: 95053
2010-02-02 02:22:50 +00:00
5b66b31774
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
...
Rn operand.
llvm-svn: 95025
2010-02-01 23:06:04 +00:00
a49d8e6d38
Fix PR6196. GV callee may not be a function.
...
llvm-svn: 95017
2010-02-01 22:40:09 +00:00
aa8c429a53
MulOp is actually a Mips specific node, so do the match using Opcode. This fixes PR6192
...
llvm-svn: 94977
2010-02-01 12:16:39 +00:00
ed8ca56eeb
Undo r94946 now all the tests are passing again.
...
llvm-svn: 94970
2010-02-01 02:13:39 +00:00
1cb8b33d61
Fix stack size bug while using o32 abi
...
llvm-svn: 94969
2010-02-01 02:03:24 +00:00
b3562f7cf6
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
...
llvm-svn: 94955
2010-01-31 11:22:28 +00:00
b33dbc5019
Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc.
...
llvm-svn: 94950
2010-01-31 07:28:44 +00:00
9adc6f46cf
Fix a missing check from my last commit.
...
llvm-svn: 94949
2010-01-31 07:27:31 +00:00
7f62def0f9
Avoid recursive sibcall's.
...
llvm-svn: 94946
2010-01-31 06:44:49 +00:00
0de0b3677a
Remove a completed item, add a couple new ones.
...
llvm-svn: 94945
2010-01-31 04:55:32 +00:00
9aeccadce4
Moved InstallLexer() from the X86-specific AsmLexer
...
to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
llvm-svn: 94940
2010-01-31 02:28:18 +00:00
193e64c699
Fix PR6144. Reload GP before the emission of CALLSEQ_END to guarantee the right reload order
...
llvm-svn: 94915
2010-01-30 18:32:07 +00:00
7ee71912ed
Fix mov.d out register by using the FFR register class directly
...
llvm-svn: 94914
2010-01-30 18:29:19 +00:00
25df248382
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
...
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
llvm-svn: 94889
2010-01-30 14:08:12 +00:00
70f714fdbe
Allow more tailcall optimization: calls with inputs that are all passed in registers.
...
llvm-svn: 94873
2010-01-30 01:22:00 +00:00
2d5a75b42a
Don't forget to transfer target flag when inserting a tailcall instruction.
...
llvm-svn: 94872
2010-01-30 01:16:15 +00:00
76e5d70c57
MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing
...
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
movl $0, %eax
as
movl 0, %eax
Feel free to guess how well that worked.
llvm-svn: 94869
2010-01-30 01:02:48 +00:00
f05d00787a
X86.td: Refactor to bring operands that use print_pcrel_imm together.
...
llvm-svn: 94861
2010-01-30 00:24:12 +00:00
a97adee959
AsmMatcher/X86: Separate out sublass for memory operands that have no segment
...
register, and use to cleanup a FIXME in X86AsmParser.cpp.
llvm-svn: 94859
2010-01-30 00:24:00 +00:00
34a6afc68d
Modified encoding bits specification for VFP instructions. In particular, the D
...
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
llvm-svn: 94855
2010-01-29 23:21:10 +00:00
25217ffaed
PPC is not ready for sibcall optimization.
...
llvm-svn: 94853
2010-01-29 23:05:56 +00:00
ad00f03e86
Add assertion to humor the paranoid.
...
llvm-svn: 94843
2010-01-29 21:21:28 +00:00
7c42b9d51e
Improve isSafeToLoadUnconditionally to recognize that GEPs with constant
...
indices are safe if the result is known to be within the bounds of the
underlying object.
llvm-svn: 94829
2010-01-29 19:19:08 +00:00
297a494f55
Catch more trivial tail call opportunities: no inputs and output types match.
...
llvm-svn: 94804
2010-01-29 06:45:59 +00:00
82436d1666
Added a custom TableGen backend to support the
...
enhanced disassembler, and the necessary makefile
rules to build the table for X86.
llvm-svn: 94764
2010-01-29 00:21:04 +00:00
29063eac23
Replace strcpy with memcpy when we have the length around anyway.
...
llvm-svn: 94746
2010-01-28 18:04:38 +00:00
cc9a6f0580
convert the last 3 targets to use EmitFunctionBody() now that
...
it has before/end body hooks.
lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 49 ++-----------
lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 87 ++++++------------------
lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp | 56 +++------------
test/CodeGen/XCore/ashr.ll | 2
4 files changed, 48 insertions(+), 146 deletions(-)
llvm-svn: 94741
2010-01-28 06:22:43 +00:00
346af88396
Fix a bug introduced by r94490 where it created a X86ISD::CMP whose output type is different from its inputs.
...
This fixes PR6146.
llvm-svn: 94731
2010-01-28 01:57:22 +00:00
125c118cd8
switch blackfin to the default runOnMachineFunction
...
llvm-svn: 94729
2010-01-28 01:54:33 +00:00
b662b7c801
eliminate a now-useless class.
...
llvm-svn: 94728
2010-01-28 01:50:22 +00:00
fd97a3369e
Switch MSP430, SPU, Sparc, and SystemZ to use EmitFunctionBody().
...
Diffstat:
6 files changed, 30 insertions(+), 284 deletions(-)
llvm-svn: 94727
2010-01-28 01:48:52 +00:00
73de5fbfc3
Give AsmPrinter the most common expected implementation of
...
runOnMachineFunction, and switch PPC to use EmitFunctionBody.
The two ppc asmprinters now don't heave to define
runOnMachineFunction.
llvm-svn: 94722
2010-01-28 01:28:58 +00:00
fa1f67ea38
switch ARM to EmitFunctionBody().
...
llvm-svn: 94719
2010-01-28 01:10:34 +00:00
94a946cac4
Remove the argument from EmitJumpTableInfo, because it doesn't need it.
...
Move the X86 implementation of function body emission up to
AsmPrinter::EmitFunctionBody, which works by calling the virtual
EmitInstruction method.
llvm-svn: 94716
2010-01-28 01:02:27 +00:00
2b796241a7
Drop the argument to AsmPrinter::EmitConstantPool and make it virtual.
...
Overload it in the ARM backend to do nothing, since is does insane
constant pool emission.
llvm-svn: 94708
2010-01-28 00:19:24 +00:00
80108921be
don't emit constant pools twice.
...
llvm-svn: 94706
2010-01-28 00:15:18 +00:00
56db8c3008
switch ARM to use EmitFunctionHeader.
...
llvm-svn: 94703
2010-01-27 23:58:11 +00:00
feba1e2495
eliminate the ARMFunctionInfo::Align member, using
...
MachineFunction::Alignment instead.
llvm-svn: 94701
2010-01-27 23:37:36 +00:00
1aef3717bd
switch blackfin to use EmitFunctionHeader. BlackfinAsmPrinter.cpp
...
is now less than 200 LOC!
llvm-svn: 94699
2010-01-27 23:26:37 +00:00
5d9fb4b746
switch mips to use the shared EmitFunctionHeader() function
...
llvm-svn: 94698
2010-01-27 23:23:58 +00:00
77b108e17b
Treat MO_REG 0 location as undefined in DEBUG_VALUE,
...
per document.
llvm-svn: 94693
2010-01-27 22:11:16 +00:00
091217be6f
Kill ModuleProvider and ghost linkage by inverting the relationship between
...
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735 .
llvm-svn: 94686
2010-01-27 20:34:15 +00:00
bc1e6f0873
add a new AsmPrinter::EmitFunctionEntryLabel virtual function,
...
which allows targets to override function entry label emission.
Use it to convert linux/ppc to use EmitFunctionHeader().
llvm-svn: 94667
2010-01-27 07:21:55 +00:00
85476f304c
Perform trivial tail call optimization for callees with "C" ABI. These are done
...
even when -tailcallopt is not specified and it does not require changing ABI.
First case is the most trivial one. Perform tail call optimization when both
the caller and callee do not return values and when the callee does not take
any input arguments.
llvm-svn: 94664
2010-01-27 06:25:16 +00:00
57f064722a
ppc/linux isn't ready for this and it was an accident that it was included.
...
This should fix a bunch of linux buildbot failures.
llvm-svn: 94643
2010-01-27 01:02:43 +00:00
2ab11001cc
use existing basic block numbers instead of recomputing
...
a new set of them.
llvm-svn: 94631
2010-01-27 00:20:02 +00:00
9da5e1f650
Switch MSP430, CellSPU, SystemZ, Darwin/PPC, Alpha, and Sparc to
...
EmitFunctionHeader:
7 files changed, 16 insertions(+), 210 deletions(-)
llvm-svn: 94630
2010-01-27 00:17:20 +00:00
640b58b8d7
Clarify what -tailcallopt option actually do.
...
llvm-svn: 94628
2010-01-27 00:10:09 +00:00
a3575ca846
Adjust setjmp instruction sequence to not need 32-bit alignment padding
...
llvm-svn: 94627
2010-01-27 00:07:20 +00:00
67a69dd2ed
Eliminate target hook IsEligibleForTailCallOptimization.
...
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
llvm-svn: 94626
2010-01-27 00:07:07 +00:00
Evan Cheng