cdbec62510
Add AVX only vzeroall and vzeroupper instructions
...
llvm-svn: 109002
2010-07-21 08:56:24 +00:00
a77f3d3b37
Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
...
llvm-svn: 108991
2010-07-21 06:09:07 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
...
llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
...
llvm-svn: 108983
2010-07-21 02:46:58 +00:00
a2489d1bb6
Give MDNode printing has access to the current Module in more
...
cases. This will be needed when function-local metadata can
appear in places that aren't intrinsic function arguments.
llvm-svn: 108971
2010-07-20 23:55:01 +00:00
0fef9dda8e
Change the createSpiller interface to take a MachineFunctionPass argument.
...
The spillers can pluck the analyses they need from the pass reference.
Switch some never-null pointers to references.
llvm-svn: 108969
2010-07-20 23:50:15 +00:00
afbe4a7a10
Make this code a little more readable.
...
llvm-svn: 108968
2010-07-20 23:49:44 +00:00
7373bd9973
Use DebugLocs instead of MDNodes.
...
llvm-svn: 108967
2010-07-20 23:49:05 +00:00
7fc9fe7553
Move the handling of PassRegistrationListener's to PassRegistry.
...
llvm-svn: 108966
2010-07-20 23:41:56 +00:00
e706501975
Add new AVX vextractf128 instructions
...
llvm-svn: 108964
2010-07-20 23:19:02 +00:00
b22dd85bb3
Fix a typo.
...
llvm-svn: 108962
2010-07-20 23:10:36 +00:00
5c2e65b7bf
Don't look up the "dbg" metadata kind by name.
...
llvm-svn: 108961
2010-07-20 23:09:34 +00:00
41ff5d4d91
make asmprinter optional, even though passing in null will cause things to explode right now.
...
llvm-svn: 108955
2010-07-20 22:45:33 +00:00
b4dc58975b
continue pushing dependencies around.
...
llvm-svn: 108952
2010-07-20 22:35:40 +00:00
2366d95af9
reduce X86MCInstLower dependencies on asmprinter.
...
llvm-svn: 108950
2010-07-20 22:30:53 +00:00
7fbdd7c852
pass around MF, not MMI.
...
llvm-svn: 108949
2010-07-20 22:26:07 +00:00
48a995f7e9
Rename removeAllMetadata to clearMetadataHashEntries and simplify
...
it to just do the things that need to be done when an instruction
is deleted.
llvm-svn: 108948
2010-07-20 22:25:04 +00:00
d3f3a89425
cleanups.
...
llvm-svn: 108947
2010-07-20 22:23:57 +00:00
5ca516b87c
move two asmprinter methods into the asmprinter .cpp file.
...
llvm-svn: 108945
2010-07-20 22:18:19 +00:00
ed4075cc3b
Implement loop splitting analysis.
...
Determine which loop exit blocks need a 'pre-exit' block inserted.
Recognize when this would be impossible.
llvm-svn: 108941
2010-07-20 21:46:58 +00:00
43aa8f03c1
Add support for remapping metadata kind IDs when reading in a
...
bitcode file, so that two bitcode files where the same metadata kind
name happens to have been assigned a different ID can still be
linked together.
Eliminate the restriction that metadata kind IDs can't be 0.
Change MD_dbg from 1 to 0, because we can now, and because it's
less mysterious that way.
llvm-svn: 108939
2010-07-20 21:42:28 +00:00
6e5ec6263e
Fix test for switch statements and increase
...
threshold a bit per experimentation.
llvm-svn: 108935
2010-07-20 21:29:12 +00:00
4154061b92
Move more functionality from Pass.cpp to PassRegistry.cpp. This global will go away eventually, but for now we still need it around.
...
llvm-svn: 108932
2010-07-20 21:22:24 +00:00
cbe9856fce
prune #includes a little.
...
llvm-svn: 108929
2010-07-20 21:17:29 +00:00
a8f6c1cc26
Add some more handlers for ELF section directives.
...
llvm-svn: 108928
2010-07-20 21:12:46 +00:00
47a0f0d56f
Remove setDbgMetadata and getDbgMetadata; their users have been
...
replaced with setDebugLoc and getDebugLoc.
llvm-svn: 108914
2010-07-20 20:18:21 +00:00
14d74d649a
Let's get those buildbots green: #include is needed in the header, not just the implementation.
...
llvm-svn: 108912
2010-07-20 20:16:11 +00:00
d2c7e52d05
Use getDebugLoc and setDebugLoc instead of getDbgMetadata and setDbgMetadata,
...
avoiding MDNode overhead.
llvm-svn: 108909
2010-07-20 20:09:07 +00:00
073660336c
apparently also missing an include.
...
llvm-svn: 108908
2010-07-20 20:06:19 +00:00
4e8e93f142
this is in System
...
llvm-svn: 108895
2010-07-20 19:54:01 +00:00
3b505848fd
Add new AVX instruction vinsertf128
...
llvm-svn: 108892
2010-07-20 19:44:51 +00:00
6faea9668f
turn this into a normal header.
...
llvm-svn: 108891
2010-07-20 19:43:19 +00:00
55cdb62dd0
hopefully heal the linux builders
...
llvm-svn: 108890
2010-07-20 19:40:51 +00:00
660466ed42
I just fail with SVN today.
...
llvm-svn: 108888
2010-07-20 19:23:55 +00:00
91773ea9b2
there is no reason to dynamically generate a static header.
...
llvm-svn: 108887
2010-07-20 18:59:58 +00:00
7e52a45f8a
drop edinfo.inc into the objdir for src!=objdir builds.
...
llvm-svn: 108886
2010-07-20 18:53:27 +00:00
529989b8b6
Update header.
...
llvm-svn: 108883
2010-07-20 18:46:43 +00:00
1e8ae64f83
Convert the internal PassRegistrar class into a new, external PassRegistry class. No intended functionality change at this point.
...
llvm-svn: 108877
2010-07-20 18:39:06 +00:00
79d68ddda8
hopefully teach cmake to build the .inc file.
...
llvm-svn: 108874
2010-07-20 18:33:21 +00:00
6219596ff6
cmake too
...
llvm-svn: 108872
2010-07-20 18:30:37 +00:00
3a14721829
forgot to add a file
...
llvm-svn: 108870
2010-07-20 18:29:50 +00:00
979634bbb0
start straightening out libedis's dependencies and make it fit
...
better in the llvm world. Among other things, this changes:
1. The guts of libedis are now moved into lib/MC/MCDisassembler
2. llvm-mc now depends on lib/MC/MCDisassembler, not tools/edis,
so edis and mc don't have to be built in series.
3. lib/MC/MCDisassembler no longer depends on the C api, the C
API depends on it.
4. Various code cleanup changes.
There is still a lot to be done to make edis fit with the llvm
design, but this is an incremental step in the right direction.
llvm-svn: 108869
2010-07-20 18:25:19 +00:00
12725c7d46
Remember that the induction variable is always a PHINode and
...
use getIncomingValueForBlock instead of
LoopInfo::getCanonicalInductionVariableIncrement.
llvm-svn: 108865
2010-07-20 17:18:52 +00:00
625fd2292d
Fix SCEV denormalization of expressions where the exit value from
...
one loop is involved in the increment of an addrec for another
loop. This fixes rdar://8168938.
llvm-svn: 108863
2010-07-20 17:06:20 +00:00
3183ef1120
Pull out r108755. After offline discussion with Chris, we're going to go a different direction with this.
...
llvm-svn: 108856
2010-07-20 16:55:05 +00:00
46f00a25f9
Add a fast path for x - x.
...
llvm-svn: 108855
2010-07-20 16:53:00 +00:00
31158756e4
Simplify this code; LoopInfo::getCanonicalInductionVariable will only
...
find integer induction variables.
llvm-svn: 108853
2010-07-20 16:46:58 +00:00
4fd92434f1
Make getOrInsertCanonicalInductionVariable guarantee that its
...
result is a PHINode*.
llvm-svn: 108852
2010-07-20 16:44:52 +00:00
191f2e4dbd
Change an argument from an Instruction* to a Value*, which is all
...
that is needed here.
llvm-svn: 108850
2010-07-20 16:34:50 +00:00
d1488fd8bc
Minor code cleanups.
...
llvm-svn: 108848
2010-07-20 16:32:11 +00:00
ff095507e3
Appease the colonials.
...
llvm-svn: 108845
2010-07-20 16:12:37 +00:00
3680f70c9d
Using BIC for immediates needs an extra bump for its complexity to get
...
instruction selection to prefer it when possible. rdar://7903972
llvm-svn: 108844
2010-07-20 16:07:04 +00:00
36d12c679d
Beginning SplitKit - utility classes for live range splitting.
...
This is a work in progress. So far we have some basic loop analysis to help
determine where it is useful to split a live range around a loop.
The actual loop splitting code from Splitter.cpp is also going to move in here.
llvm-svn: 108842
2010-07-20 15:41:07 +00:00
9c7708cc1b
Removed un-used code.
...
llvm-svn: 108841
2010-07-20 14:51:32 +00:00
31dfb75b52
Updated css classes for the pressure table legend.
...
llvm-svn: 108839
2010-07-20 14:35:55 +00:00
2ff2193a80
Oops - I tables render poorly in Chrome without this explicit height specification.
...
llvm-svn: 108824
2010-07-20 10:29:46 +00:00
a475ab7f02
Use run-length encoding to represent identical adjacent cells in the pressure
...
and interval table. Reduces output HTML file sizes by ~80% in my test cases.
Also fix access of private member type by << operator.
llvm-svn: 108823
2010-07-20 10:18:54 +00:00
716b184108
Added support for turning HTML indentation on and off (indentation off by default).
...
Reduces output file size ~20% on my test cases.
llvm-svn: 108822
2010-07-20 09:13:29 +00:00
160695fecb
Fix PR7174, a couple o Mips fixes:
...
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
llvm-svn: 108820
2010-07-20 08:37:04 +00:00
81781220d2
Speculatively revert r108813, in an attempt to get the self-host buildbots working again. I don't see why this patch
...
would cause them to fail the way they are, but none of the other intervening patches seem likely either.
llvm-svn: 108818
2010-07-20 08:26:15 +00:00
ea7863647b
Fix Mips PR7473. Patch by stetorvs@gmail.com
...
llvm-svn: 108816
2010-07-20 07:58:51 +00:00
a93fe2de3c
Switched to rendering after allocation (but before rewriting) in PBQP.
...
Updated renderer to use allocation information from VirtRegMap (if
available) to render spilled intervals differently.
llvm-svn: 108815
2010-07-20 07:41:44 +00:00
8dc129325f
Reapply r108794, a fix for the failing test from last time.
...
llvm-svn: 108813
2010-07-20 06:52:42 +00:00
4adaccf0bf
Constify some arguments.
...
llvm-svn: 108812
2010-07-20 06:52:21 +00:00
4a35d6f8cd
Revert r108794, "Separate PassInfo into two classes: a constructor-free
...
superclass (StaticPassInfo) and a constructor-ful subclass (PassInfo).", it is
breaking teh everything.
llvm-svn: 108805
2010-07-20 03:06:07 +00:00
e7c5fe586a
Separate PassInfo into two classes: a constructor-free superclass (StaticPassInfo) and a constructor-ful subclass (PassInfo).
...
llvm-svn: 108794
2010-07-20 01:19:58 +00:00
3ff13affda
Minor code simplification.
...
llvm-svn: 108793
2010-07-20 00:57:18 +00:00
08645f1991
Don't hoist things out of a large switch inside a
...
loop, for the reasons in the comments. This is a
major win on 253.perlbmk on ARM Darwin. I expect it
to be a good heuristic in general, but it's possible
some things will regress; I'll be watching.
7940152
2010-07-20 00:50:13 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
...
llvm-svn: 108788
2010-07-20 00:11:13 +00:00
0aff8033c6
Update CMake files.
...
llvm-svn: 108787
2010-07-20 00:08:13 +00:00
61475c5c3c
Correct line info for declarations/definitions. Radar 8063111.
...
llvm-svn: 108784
2010-07-19 23:56:30 +00:00
b792b463af
sink the arm implementations of ASmPrinter and MCInstLower
...
out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
llvm-svn: 108783
2010-07-19 23:44:46 +00:00
64fffadad3
fix a layering problem by moving the x86 implementation
...
of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory. Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.
llvm-svn: 108782
2010-07-19 23:41:57 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
...
llvm-svn: 108769
2010-07-19 23:32:44 +00:00
d61b735d25
Fix memory leak reported by valgrind.
...
Do not visit operands of old instruction. Visit all operands of new instruction.
llvm-svn: 108767
2010-07-19 23:25:39 +00:00
b5e918dc05
After a custom inserter, in a block which has constant instructions,
...
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.
llvm-svn: 108765
2010-07-19 22:48:56 +00:00
10f99a3490
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
...
llvm-svn: 108761
2010-07-19 22:15:08 +00:00
0edf6a1131
Change the implemented interfaces list on PassInfo from a std::vector to a manually implemented
...
linked list. This is a little slower and involves more malloc'ing, but these lists are
typically short, and it allows PassInfo to be entirely constant initializable.
llvm-svn: 108755
2010-07-19 21:44:48 +00:00
6b4391aa69
MC/Mach-O: Silently ignore .file directives instead of error'ing out on
...
them. They aren't important enough to abort the entire assembly, and failing
early makes testing more annoying.
llvm-svn: 108747
2010-07-19 20:44:20 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
...
instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
84774eda4b
Tweak per Chris' comments.
...
llvm-svn: 108736
2010-07-19 19:23:32 +00:00
7a135510e3
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
...
This property will be used by the register pressure tracking instruction scheduler.
llvm-svn: 108735
2010-07-19 18:47:01 +00:00
a58a7e7f9e
Spillers may alter MachineLoopInfo when breaking critical edges, so make it
...
non-const.
llvm-svn: 108734
2010-07-19 18:41:20 +00:00
18efced1a2
Fix PR 7662.
...
Do not try to insert local variable info to a DIE used for function declaration.
llvm-svn: 108731
2010-07-19 17:53:55 +00:00
8d3ba7349c
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.
llvm-svn: 108730
2010-07-19 17:20:38 +00:00
d9ad52adff
revert so I can get the right PR# in the log message.
...
llvm-svn: 108727
2010-07-19 17:19:40 +00:00
c685756cfb
Since ARM emits inline jump tables as part of the ConstantIsland pass,
...
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.
llvm-svn: 108722
2010-07-19 17:18:28 +00:00
58c283ee85
Update CMake build.
...
llvm-svn: 108700
2010-07-19 15:37:03 +00:00
b1d61aab06
Expose BasicBlock::moveBefore and moveAfter in C API, patch
...
by Benjamin Saunders.
llvm-svn: 108699
2010-07-19 15:31:07 +00:00
6624efb711
Render MachineFunctions to HTML pages, with options to render register
...
pressure estimates and liveness alongside.
Still experimental.
llvm-svn: 108698
2010-07-19 15:22:28 +00:00
39c06b3b23
precompute 20 tags
...
llvm-svn: 108695
2010-07-19 14:48:15 +00:00
953e617de6
Fix indentation.
...
llvm-svn: 108691
2010-07-19 09:36:45 +00:00
330134bf15
Expose JIT::recompileAndRelinkFunction for use through the C API.
...
Patch by Benjamin Saunders.
llvm-svn: 108690
2010-07-19 09:33:13 +00:00
9c271e2835
Remove r108639 now that it is handled by InstCombine instead.
...
llvm-svn: 108688
2010-07-19 08:10:24 +00:00
32a58342ed
Reimplement r108639 in InstCombine rather than DAGCombine.
...
llvm-svn: 108687
2010-07-19 08:09:34 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
...
llvm-svn: 108685
2010-07-19 07:21:07 +00:00
2e9f58517d
X86: Mark some tail call pseduo instruction as code gen only.
...
llvm-svn: 108684
2010-07-19 07:21:04 +00:00
1cd02510d3
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
...
llvm-svn: 108683
2010-07-19 07:21:01 +00:00
2ed9f4bd39
_[A-Z] identifiers are reserved for the implementation.
...
llvm-svn: 108682
2010-07-19 06:26:19 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
...
assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
150d948d3a
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
...
llvm-svn: 108680
2010-07-19 06:14:49 +00:00
961543377d
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.
...
llvm-svn: 108679
2010-07-19 06:14:44 +00:00
e2da0a478d
MC: Add WinCOFFStreamer implementation and merge common code from MachO
...
into MCObjectStreamer.
Origonal Windows COFF implementation by Nathan Jedffords.
llvm-svn: 108678
2010-07-19 06:13:10 +00:00
eefe8616be
TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
...
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.
llvm-svn: 108677
2010-07-19 05:44:09 +00:00
20b026464e
Make .align parse correctly on platforms where .align is measured in bytes.
...
llvm-svn: 108674
2010-07-19 04:17:25 +00:00
419197cc4d
Target: Give the TargetAsmParser access to the TargetMachine.
...
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.
llvm-svn: 108664
2010-07-19 00:33:49 +00:00
8897d479b5
MC/AsmParser: Stop playing unsafe member function pointer calls, this isn't
...
portable enough.
- Downside is we now double dispatch through a stub function, but this isn't
performance critical.
llvm-svn: 108661
2010-07-18 22:22:07 +00:00
40a564f09f
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
...
sequences, not just strings.
llvm-svn: 108655
2010-07-18 20:15:59 +00:00
6fb1c3ad8a
MC/AsmParser: Add macro argument substitution support.
...
llvm-svn: 108654
2010-07-18 19:00:10 +00:00
4323571efb
MC/AsmParser: Add basic support for macro instantiation.
...
llvm-svn: 108653
2010-07-18 18:54:11 +00:00
c1f58ec83c
MC/AsmParser: Add basic parsing support for .macro definitions.
...
llvm-svn: 108652
2010-07-18 18:47:21 +00:00
828984ff4e
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
...
support macros.
llvm-svn: 108649
2010-07-18 18:38:02 +00:00
d8a1845c31
MC/AsmParser: Use Error() instead of calling PrintMessage() directly.
...
llvm-svn: 108648
2010-07-18 18:31:45 +00:00
ba6e354b61
MC/AsmParser: Fix TokError() to accept a Twine.
...
llvm-svn: 108647
2010-07-18 18:31:42 +00:00
2a2c6cf5f9
MC/AsmParser: Hide the AsmParser implementation.
...
llvm-svn: 108646
2010-07-18 18:31:38 +00:00
7f5bf5ae2a
MC: Move several clients to using AsmParser constructor function.
...
llvm-svn: 108645
2010-07-18 18:31:33 +00:00
8ff89f5c02
Fix struct/class mismatch
...
llvm-svn: 108642
2010-07-18 11:47:56 +00:00
f7f9c8a2f7
Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
...
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.
This fixed <rdar://problem/8197504>.
llvm-svn: 108639
2010-07-18 08:47:54 +00:00
1392b8eb79
Added -pbqp-pre-coalescing flag to PBQP. If enabled this will cause PBQP to require
...
LoopSplitter be run prior to register allocation.
Entirely for testing purposes at the moment.
llvm-svn: 108634
2010-07-18 00:57:59 +00:00
2960987ddb
fullStopTag cannot happen here, it is handled above
...
llvm-svn: 108631
2010-07-17 20:52:46 +00:00
ac67e99d53
Use isPrologLabel() instead of checking the opcode directly.
...
llvm-svn: 108628
2010-07-17 19:18:44 +00:00
5218343970
the stackifier is global!
...
llvm-svn: 108626
2010-07-17 17:42:04 +00:00
8f440bb9b0
doxygenify some comments.
...
llvm-svn: 108625
2010-07-17 17:40:51 +00:00
b653ce648d
update CMakeLists.txt
...
llvm-svn: 108620
2010-07-17 12:12:42 +00:00
5864012cc0
Removed unused inRange variable.
...
llvm-svn: 108618
2010-07-17 11:43:07 +00:00
225977d4f9
LoopSplitter - intended to split live intervals over loop boundaries.
...
Still very much under development. Comments and fixes will be forthcoming.
(This commit includes some small tweaks to LiveIntervals & LoopInfo to support the splitter)
llvm-svn: 108615
2010-07-17 07:34:01 +00:00
7d2818b073
Another attempt at getting the clang self-host to like my instcombine patch.
...
llvm-svn: 108614
2010-07-17 06:56:35 +00:00
211e7ce7e7
Iterating over sets of pointers in a heuristic was a bad idea. Switching
...
any command line paramater changed the register allocation produced by
PBQP.
Turns out variety is not the spice of life.
Fixed some comparators, added others. All good now.
llvm-svn: 108613
2010-07-17 06:31:41 +00:00
9de5967244
Start of .sleb128/.uleb128 parsing support.
...
llvm-svn: 108612
2010-07-17 06:27:28 +00:00
718da70ca2
Fix PR7658, a problem where type refinement can trigger
...
constant replacement which was botching its handling of
types. Use of getType() instead of getRawType() was causing
the type map in constant folding to be updated wrong.
llvm-svn: 108610
2010-07-17 06:13:52 +00:00
9e36dd001a
Work-in-progress parsing for ELF .section directive.
...
llvm-svn: 108609
2010-07-17 04:29:04 +00:00
b97e2bbe32
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
...
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
llvm-svn: 108608
2010-07-17 03:30:54 +00:00
56178a07bf
Add support for parsing .size directives for ELF.
...
llvm-svn: 108606
2010-07-17 03:09:18 +00:00
01e3607d70
MC/AsmParser: Lift Run() and TargetParser to base class.
...
Also, add constructor function for creating AsmParser instances.
llvm-svn: 108604
2010-07-17 02:26:10 +00:00
6e3b5fa91c
add BFI to getTargetNodeName()
...
llvm-svn: 108603
2010-07-17 01:50:57 +00:00
adc81f8ee8
Fix logic think-o
...
llvm-svn: 108601
2010-07-17 01:22:19 +00:00
83f250f005
Remove unnecessary check that was subsumed into canRealignStack.
...
llvm-svn: 108588
2010-07-17 00:33:04 +00:00
0baaa9bcc1
Propagate alloca alignment information via variable size object frame
...
information.
No functional change yet.
llvm-svn: 108583
2010-07-17 00:28:22 +00:00
24e3aa011a
Make more explicit and add some currently disabled error messages for
...
stack realignment on ARM.
Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.
llvm-svn: 108582
2010-07-17 00:27:24 +00:00
c0be37287c
Make comment a bit more clear as well as return statement since
...
needsStackRealignment is currently checking the can conditions as well.
llvm-svn: 108581
2010-07-17 00:25:41 +00:00
11013eda5a
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
...
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
llvm-svn: 108570
2010-07-16 23:05:05 +00:00
9a54c17582
Fix whitespace.
...
llvm-svn: 108569
2010-07-16 22:58:39 +00:00
bf8370ff36
Consider this function:
...
void foo() { __builtin_unreachable(); }
It will output the following on Darwin X86:
_func1:
Leh_func_begin0:
pushq %rbp
Ltmp0:
movq %rsp, %rbp
Ltmp1:
Leh_func_end0:
This prolog adds a new Call Frame Information (CFI) row to the FDE with an
address that is not within the address range of the code it describes -- part is
equal to the end of the function -- and therefore results in an invalid EH
frame. If we emit a nop in this situation, then the CFI row is now within the
address range.
llvm-svn: 108568
2010-07-16 22:51:10 +00:00
8289f78569
Remove the isMoveInstr() hook.
...
llvm-svn: 108567
2010-07-16 22:35:46 +00:00
8e767bde16
Avoid isMoveInstr when printing XCore pseudo-moves.
...
llvm-svn: 108566
2010-07-16 22:35:37 +00:00
2c130b8ead
Use MI.isCopy.
...
llvm-svn: 108565
2010-07-16 22:35:34 +00:00
54bcf5049e
Use a small local function for a single remaining late isMoveInstr call in
...
Thumb2ITBlockPass.
llvm-svn: 108564
2010-07-16 22:35:32 +00:00
499f797cdd
Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
...
thus is a much more meaningful name.
llvm-svn: 108563
2010-07-16 22:20:36 +00:00
8d51149102
Keep valgrind quiet.
...
The isLive() method can read uninitialized memory, but it still gives correct
results.
llvm-svn: 108561
2010-07-16 22:00:33 +00:00
c9c22862d4
tidy up
...
llvm-svn: 108560
2010-07-16 21:20:46 +00:00
b15cbd343c
Remove remaining calls to TII::isMoveInstr.
...
llvm-svn: 108556
2010-07-16 21:03:55 +00:00
44629eb81b
Emit COPY instead of FMR/FMSD instructions for floating point conversion on
...
PowerPC.
llvm-svn: 108555
2010-07-16 21:03:52 +00:00
27e997a168
eliminate unlockedRefineAbstractTypeTo, types are all per-llvmcontext,
...
so there is no locking involved in type refinement.
llvm-svn: 108553
2010-07-16 20:50:13 +00:00
fee4dafbd0
get the first few tags from a precomputed table (count can be increased if desired)
...
llvm-svn: 108549
2010-07-16 20:35:19 +00:00
ba9b25a6ba
Add missing attributes to cpp backend.
...
llvm-svn: 108547
2010-07-16 18:47:20 +00:00
da3e05db70
Accept registers with P modifier. PR 5314.
...
llvm-svn: 108545
2010-07-16 18:35:46 +00:00
6353e534ec
Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory
...
operands.
Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.
llvm-svn: 108540
2010-07-16 18:22:00 +00:00
efd7f9c360
Reorder the contents of various getAnalysisUsage functions, eliminating
...
a redundant loopsimplify run from the default -O2 sequence.
llvm-svn: 108539
2010-07-16 17:58:45 +00:00
1e936277c3
Revert r108369, sorting llvm.dbg.declare information by source position,
...
since it doesn't work for front-ends which don't emit column information
(which includes llvm-gcc in its present configuration), and doesn't
work for clang for K&R style variables where the variables are declared
in a different order from the parameter list.
Instead, make a separate pass through the instructions to collect the
llvm.dbg.declare instructions in order. This ensures that the debug
information for variables is emitted in this order.
llvm-svn: 108538
2010-07-16 17:54:27 +00:00
c30b4ddc58
Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill
...
pass that inserted it.
It is no longer necessary to limit the live ranges of FP registers to a single
basic block.
llvm-svn: 108536
2010-07-16 17:41:44 +00:00
f0af236874
Search for a free FP register instead of just assuming FP7 is not in use.
...
llvm-svn: 108535
2010-07-16 17:41:40 +00:00
8a39c807e2
Remove the rest of my instcombine changes. Back to the drawing board on this one.
...
llvm-svn: 108530
2010-07-16 16:39:00 +00:00
0e5fb020a0
Allow x87 FP registers to be alive globally in a function.
...
FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.
CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.
This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.
llvm-svn: 108529
2010-07-16 16:38:12 +00:00
6d673953e3
eliminate CallInst::ArgOffset
...
llvm-svn: 108522
2010-07-16 09:38:02 +00:00
17c5a23559
Get rid of a bunch of duplicated ELF enum values.
...
llvm-svn: 108520
2010-07-16 07:53:29 +00:00
375efe3157
Arrays and vectors with different numbers of elements are not equivalent.
...
llvm-svn: 108517
2010-07-16 06:31:12 +00:00
3d84c9c793
LoopSimplify does not update domfrontier correctly.
...
This fixes PR7649.
llvm-svn: 108513
2010-07-16 05:59:45 +00:00
bd7c9f701b
Add dump() to DominanceFrontier
...
llvm-svn: 108512
2010-07-16 05:59:39 +00:00
37c42a3d02
Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
...
TII::isMoveInstr is going tobe completely removed.
llvm-svn: 108507
2010-07-16 04:45:42 +00:00
103c4ebea5
Use the source-order scheduler instead of the "fast" scheduler at -O0,
...
because it's more likely to keep debug line information in its original
order.
llvm-svn: 108496
2010-07-16 02:01:19 +00:00
15a81cddb4
Also revert 108422, it's causing some test failures.
...
Working on testcases for Owen.
llvm-svn: 108494
2010-07-16 01:36:12 +00:00
bfd4fd7bb7
The SelectionDAGBuilder's handling of debug info, on rare
...
occasions, caused code to be generated in a different order.
All cases I've seen involved float softening in the type
legalizer, and this could be perhaps be fixed there, but
it's better not to generate things differently in the first
place. 7797940 (6/29/2010..7/15/2010).
llvm-svn: 108484
2010-07-16 00:02:08 +00:00
4bda1c8e68
Revert. This isn't the correct way to go.
...
llvm-svn: 108478
2010-07-15 23:42:21 +00:00
fbbdfcaea7
Fix the order that SCEVExpander considers add operands in so that
...
it doesn't miss an opportunity to form a GEP, regardless of the
relative loop depths of the operands. This fixes rdar://8197217.
llvm-svn: 108475
2010-07-15 23:38:13 +00:00
973dc3b1d8
Handle code gen for the unreachable instruction if it's the only instruction in
...
the function. We'll just turn it into a "trap" instruction instead.
The problem with not handling this is that it might generate a prologue without
the equivalent epilogue to go with it:
$ cat t.ll
define void @foo() {
entry:
unreachable
}
$ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables
.section __TEXT,__text,regular,pure_instructions
.globl _foo
.align 4, 0x90
_foo: ## @foo
Leh_func_begin0:
## BB#0: ## %entry
pushq %rbp
Ltmp0:
movq %rsp, %rbp
Ltmp1:
Leh_func_end0:
...
The unwind tables then have bad data in them causing all sorts of problems.
Fixes <rdar://problem/8096481>.
llvm-svn: 108473
2010-07-15 23:32:40 +00:00
55f0c6b9fc
Split -enable-finite-only-fp-math to two options:
...
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.
llvm-svn: 108465
2010-07-15 22:07:12 +00:00
60b131654b
fix the definitions of ConstTextCoalSection/ConstDataCoalSection
...
to keep "Text" in sync with the "pure instructions" section attribute.
Lack of this attribute was preventing the assembler from emitting
multibyte noops instructions for templates (and inlines, and other
coalesced stuff) and was causing the assembler to mismatch .o files.
This fixes rdar://8018335
llvm-svn: 108461
2010-07-15 21:22:00 +00:00
c2b3675f8b
fix indentation and 80 cols
...
llvm-svn: 108460
2010-07-15 21:19:31 +00:00
1415208292
Don't merge uses when they are targetting fixup sites with
...
different widths. In a use with a narrower fixup, formulae
may be wider than the fixup, in which case the high bits
aren't necessarily meaningful, so it isn't safe to reuse
them for uses with wider fixups.
This fixes PR7618, though the testcase is too large for a
reasonable regression test, since it heavily dependes on
hitting LSR's heuristics in a certain way.
llvm-svn: 108455
2010-07-15 20:24:58 +00:00
620693806a
fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,
...
this fixes rdar://8192860. Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.
llvm-svn: 108454
2010-07-15 20:13:34 +00:00
a1501b9c50
Use dbgs() instead of errs() in a DEBUG.
...
llvm-svn: 108453
2010-07-15 20:12:42 +00:00
2da75ef315
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
...
llvm-svn: 108452
2010-07-15 20:04:36 +00:00
64b1e82a7c
Teach ScalarEvolution how to fold trunc(undef) and anyext(undef) to undef.
...
This helps LSR behave more consistently on bugpoint-reduced testcases.
llvm-svn: 108451
2010-07-15 20:02:11 +00:00
dd5e9d8faf
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
...
llvm-svn: 108450
2010-07-15 20:01:02 +00:00
51a9c0a1b3
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time
...
make sure to allocate enough space in the std::vector.
llvm-svn: 108449
2010-07-15 19:58:14 +00:00
5a8d15c553
Reserve a goodly amount of room for the vectors.
...
llvm-svn: 108448
2010-07-15 19:41:20 +00:00
df09db62e2
Fix crash reported in PR7653.
...
llvm-svn: 108441
2010-07-15 18:45:27 +00:00
030b0286ec
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
...
llvm-svn: 108440
2010-07-15 18:43:09 +00:00
57681404b0
Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
...
llvm-svn: 108438
2010-07-15 18:40:50 +00:00
eaf64d5c1e
Speculatively revert r108429 to fix the clang self-host.
...
llvm-svn: 108436
2010-07-15 18:18:57 +00:00
eb08d01061
Per Chris' suggestion, get rid of the select canonicalization and just add
...
the corresponding or-icmp-and pattern. This has the added benefit of doing
the matching earlier, and thus being less susceptible to being confused by
earlier transforms.
llvm-svn: 108429
2010-07-15 17:24:23 +00:00
13700ebb02
Remove unneeded check, and correct style.
...
llvm-svn: 108427
2010-07-15 16:38:22 +00:00
4afd412d6b
Watch out for a constant offset cancelling out a base register, forming
...
a zero. This situation arrises in Fortran code with induction variables
that start at 1 instead of 0. This fixes PR7651.
llvm-svn: 108424
2010-07-15 15:14:45 +00:00
7151dfd48a
Reapply r108378, with bugfixes, testcase, and improved comment formatting.
...
This now passes LIT, nighty test, and llvm-gcc bootstrap on my machine.
llvm-svn: 108422
2010-07-15 15:00:23 +00:00
26ec65ac3c
cache another dereferenced iterator
...
llvm-svn: 108421
2010-07-15 10:19:23 +00:00
c48adb60ca
revert bill's patches in an attempt to fix the buildbot.
...
llvm-svn: 108419
2010-07-15 06:51:46 +00:00
485ce5a49c
This is a full sentence.
...
llvm-svn: 108418
2010-07-15 06:51:22 +00:00
e6f3287cbb
Disable aliases on all platforms.
...
llvm-svn: 108417
2010-07-15 06:48:56 +00:00
19eff2a9f6
Fix PR7647, handling the case when 'To' ends up being
...
mutated by recursive simplification. This also enhances
ReplaceAndSimplifyAllUses to actually do a real RAUW
at the end of it, which updates any value handles
pointing to "From" to start pointing to "To". This
seems useful for debug info and random other VH users.
llvm-svn: 108415
2010-07-15 06:36:08 +00:00
e41ab07c61
make various clients of ReplaceAndSimplifyAllUses tolerate
...
it *changing* the things it replaces, not just causing them
to drop to null. There is no functionality change yet, but
this is required for a subsequent patch.
llvm-svn: 108414
2010-07-15 06:06:04 +00:00
1f7071a3e4
Fix headers.
...
llvm-svn: 108413
2010-07-15 06:05:18 +00:00
e7e6ca5c57
Use std::vector instead of a hard-coded array. The length of that array could
...
get *very* large, but we only need it to be the size of the number of pregs.
llvm-svn: 108412
2010-07-15 06:04:38 +00:00
d5b390189d
Use std::vector instead of a hard-coded array. The length of that array could
...
get *very* large, but we only need it to be the size of thenumber of pregs.
llvm-svn: 108411
2010-07-15 05:56:32 +00:00
8b3a17e613
Revert r108401; it breaks bootstrap :(
...
llvm-svn: 108407
2010-07-15 05:09:31 +00:00
fd473a746c
Add AssertingVH which makes PR7647 break consistently.
...
llvm-svn: 108401
2010-07-15 04:46:14 +00:00
e4be4308a9
Random note about bswap.
...
llvm-svn: 108396
2010-07-15 02:20:38 +00:00
28fd6785bc
a more graceful fix for test/Other/inline-asm-newline-terminator.ll,
...
follow on to r103765
llvm-svn: 108390
2010-07-15 00:37:34 +00:00
a8b4e3732b
Speculatively revert r108378; may be causing bootstrap failures.
...
llvm-svn: 108389
2010-07-15 00:33:00 +00:00
8b1bb8cfbd
Last COPY conversion.
...
llvm-svn: 108387
2010-07-14 23:58:21 +00:00
0b9aafddc5
Remove restriction on NEON alignment values. Some of the NEON ld/st
...
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
llvm-svn: 108386
2010-07-14 23:54:43 +00:00
9b449d5a92
Use TargetOpcode::COPY instead of X86-native register copy instructions when
...
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
llvm-svn: 108385
2010-07-14 23:50:27 +00:00
474e56a2bf
80-col.
...
llvm-svn: 108381
2010-07-14 23:41:32 +00:00
37d91d84af
Add instcombine transforms to optimize tests of multiple bits of the same value into a single larger comparison.
...
llvm-svn: 108378
2010-07-14 23:33:51 +00:00
f10cd5c6cb
Make the order in which variables are described in debug information
...
independent of the order that isel happens to visit the dbg_declare
intrinsics. This fixes a bug in which the formal arguments were
being printed in reverse order, now that fast isel is going bottom up.
llvm-svn: 108369
2010-07-14 23:08:16 +00:00
769aedd523
fix indentation
...
llvm-svn: 108368
2010-07-14 23:04:59 +00:00
92d8998348
Don't pass StringRef by reference.
...
llvm-svn: 108366
2010-07-14 22:38:02 +00:00
c12a6731c5
Properly restore DebugLoc after leaving the local constant area.
...
llvm-svn: 108364
2010-07-14 22:01:31 +00:00
1513217e27
Just use getParent() instead of getModuleFromVal when the value is a Function.
...
llvm-svn: 108358
2010-07-14 21:12:44 +00:00
efb8dbb3f1
Rename WriteConstantInt to WriteConstantInternal, to avoid confusion.
...
llvm-svn: 108357
2010-07-14 20:57:55 +00:00
2cfe91379b
Extend SimplifyCFG's common-destination folding heuristic to allow a single
...
"bonus" instruction to be speculatively executed. Add a heuristic to
ensure we're not tripping up out-of-order execution by checking that this bonus
instruction only uses values that were already guaranteed to be available.
This allows us to eliminate the short circuit in (x&1)&&(x&2).
llvm-svn: 108351
2010-07-14 19:52:16 +00:00
8939ba337d
Factor out metadata parsing into a separate function.
...
llvm-svn: 108343
2010-07-14 18:26:50 +00:00
254858031a
Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,
...
patch by Michael Spencer!
llvm-svn: 108342
2010-07-14 18:14:33 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
042523340b
Delete fast-isel's trivial load optimization; it breaks debugging because
...
it can look past points where a debugger might modify user variables.
llvm-svn: 108336
2010-07-14 17:25:37 +00:00
1aef53403f
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
llvm-svn: 108332
2010-07-14 16:02:13 +00:00
7a68cd094b
Rather than using an ifdef on the target to zero out fields,
...
just use memset to zero the entire struct.
llvm-svn: 108330
2010-07-14 14:32:33 +00:00
c4d70125ee
A couple potential optimizations inspired by comment 4 in PR6773.
...
llvm-svn: 108328
2010-07-14 06:58:26 +00:00
a8e8874552
Fix for PR7193 was overly conservative. The only case where sibcall callee
...
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
llvm-svn: 108327
2010-07-14 06:44:01 +00:00
bad47f62f6
Add support for NEON VMVN immediate instructions.
...
llvm-svn: 108324
2010-07-14 06:31:50 +00:00
bd54a53628
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
...
of the value of the immediate.
llvm-svn: 108323
2010-07-14 06:30:44 +00:00
ec0e7b1643
revert r108320, I see the failures now...
...
llvm-svn: 108322
2010-07-14 06:16:35 +00:00
658680b2f5
reapply benjamin's instcombine patch, I don't see anything wrong with it and can't repro any problems with a manual self-host.
...
llvm-svn: 108320
2010-07-14 05:59:13 +00:00
164a0775bb
fix a bug found by a warning I added to clang this morning.
...
llvm-svn: 108309
2010-07-14 01:57:17 +00:00
d542414945
Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.
...
llvm-svn: 108304
2010-07-14 01:22:19 +00:00
103a0dcfe1
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
...
Radar 7373643.
llvm-svn: 108303
2010-07-14 01:22:12 +00:00
1f471435f8
Don't propagate debug locations to instructions for materializing
...
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.
llvm-svn: 108302
2010-07-14 01:07:44 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
...
llvm-svn: 108286
2010-07-13 22:06:38 +00:00
cd7a40f4ec
Print VNInfo flags.
...
llvm-svn: 108277
2010-07-13 21:19:05 +00:00
a3f1901531
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
...
NEON VMOV-immediate instructions. This simplifies some things.
llvm-svn: 108275
2010-07-13 21:16:48 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
...
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
caca5488dc
In inline asm treat indirect 'X' constraint as 'm'.
...
This may not be right in all cases, but it's better
than asserting which it was doing before. PR 7528.
llvm-svn: 108268
2010-07-13 20:17:05 +00:00
76a6b663a3
Added a check that pusha cannot be encoded in 64-bit mode.
...
llvm-svn: 108265
2010-07-13 20:05:41 +00:00
fc4b8b8e80
Add an assertion to make PR7542 fail consistently.
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LiveInterval::overlapsFrom dereferences end() if it is called on an empty
interval.
It would be reasonable to just return false - an empty interval doesn't overlap
anything, but I want to know who is doing it first.
llvm-svn: 108264
2010-07-13 19:56:28 +00:00
afd69cf5b7
Add support for empty named metadata too. This isn't particularly
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useful, but it is nice for consistency.
llvm-svn: 108262
2010-07-13 19:42:44 +00:00
b43455feaf
Fix LiveInterval::overlaps so it doesn't claim touching intervals overlap.
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Also, one binary search is enough.
llvm-svn: 108261
2010-07-13 19:42:20 +00:00
1e0213a758
Add support for empty metadata nodes: !{}.
...
llvm-svn: 108259
2010-07-13 19:33:27 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
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llvm-svn: 108258
2010-07-13 19:27:42 +00:00
58066e337d
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
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llvm-svn: 108256
2010-07-13 19:21:50 +00:00
f43961007c
-enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.
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llvm-svn: 108254
2010-07-13 18:46:14 +00:00
ea282034b6
Grammar.
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llvm-svn: 108252
2010-07-13 18:27:13 +00:00
f88a284579
Handle the case of a tail recursion in which the tail call is followed
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by a return that returns a constant, while elsewhere in the function
another return instruction returns a different constant. This is a
special case of accumulator recursion, so just generalize the existing
logic a bit.
llvm-svn: 108241
2010-07-13 15:41:41 +00:00
03e7e68caa
rotate CallInst operands
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with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)
this ordering is now consistent with InvokeInst
this commit only flips the switch,
functionally it is equivalent to
r101465
I intend to commit several cleanups after a few
days of soak period
llvm-svn: 108240
2010-07-13 15:31:36 +00:00
c1c6f4796e
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
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avoid replicated code.
llvm-svn: 108227
2010-07-13 04:44:34 +00:00
55595fb291
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
dff283e146
Add AVX 256-bit packed logical forms
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llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
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llvm-svn: 108223
2010-07-13 01:53:31 +00:00
77a3c4462f
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
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llvm-svn: 108222
2010-07-13 00:38:47 +00:00
54e620d2c7
Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results,
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they already have one.
This fixes the himenobmtxpa miscompilation on ARM.
The PostRA scheduler got confused by the double memoperand and hoisted a stack
slot load above a store to the same slot.
llvm-svn: 108219
2010-07-13 00:23:30 +00:00
03264efe30
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
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utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
llvm-svn: 108213
2010-07-12 23:41:28 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
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llvm-svn: 108207
2010-07-12 23:04:15 +00:00
91806311c9
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
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llvm-svn: 108204
2010-07-12 22:41:32 +00:00
ab058b83e0
MC/AsmParser: Move ELF specific parser to ELFAsmParser.cpp.
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llvm-svn: 108196
2010-07-12 21:23:32 +00:00
0cb91cfc74
MC/AsmParser: Move Darwin specific parse to DarwinAsmParser.cpp.
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llvm-svn: 108193
2010-07-12 20:51:51 +00:00
51e6d9bbf6
Apply the SSE dependence idiom for SSE unary operations to
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SD instructions too, in addition to SS instructions. And
add a comment about it.
llvm-svn: 108191
2010-07-12 20:46:04 +00:00
a5bf6b6001
MC/AsmParser: Move .section parsing to Darwin specific parser.
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llvm-svn: 108190
2010-07-12 20:42:34 +00:00
aa59cf2686
MC/AsmParser: Move special section directive parsing to Darwin specific parser.
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llvm-svn: 108187
2010-07-12 20:23:36 +00:00
8a2bdc8231
Remove some code that doesn't appear to do anything. All the ARM call
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instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
llvm-svn: 108186
2010-07-12 20:22:45 +00:00
80be44a2ac
MC/AsmParser: Add a basic ELFAsmParser extension.
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llvm-svn: 108185
2010-07-12 20:08:04 +00:00
f9bcaad76d
Add AVX 256-bit MOVMSK forms
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llvm-svn: 108184
2010-07-12 20:06:32 +00:00
101c14c940
MC/AsmParser: Inline AsmParser::CreateSymbol into callers.
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llvm-svn: 108183
2010-07-12 19:52:10 +00:00
d388c93f87
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
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llvm-svn: 108180
2010-07-12 19:37:35 +00:00
63a379dd5c
MC/AsmParser: Move .desc parsing to Darwin specific parser.
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llvm-svn: 108179
2010-07-12 19:22:53 +00:00
b992f1a95b
MC/AsmParser: Move .lsym parsing to Darwin specific parser.
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llvm-svn: 108176
2010-07-12 19:08:25 +00:00
ae9da1481a
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
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llvm-svn: 108174
2010-07-12 18:49:22 +00:00
425b35681f
Check begin!=end, rather than !begin.
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llvm-svn: 108167
2010-07-12 18:12:35 +00:00
c5011088cd
MC/AsmParser: Add a DarwinAsmParser extension.
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- Currently initialization is a bit of a hack, but harmless. We need to rework
various parts of target initialization to clean this up.
llvm-svn: 108165
2010-07-12 18:12:02 +00:00
a18c5a0e5e
Fix a typo and fit in 80 columns. Found by Bob Wilson.
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llvm-svn: 108164
2010-07-12 18:11:17 +00:00
dd41dcf270
MC/AsmParser: Switch a bunch of directive parsing to use accessors.
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llvm-svn: 108163
2010-07-12 18:03:11 +00:00
c128e70ff2
Add a lint check for mismatched return types, inspired by PR6944.
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llvm-svn: 108162
2010-07-12 18:02:04 +00:00
86033407c9
MCAsmParser: Pull some directive handling out into a helper class, and change
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DirectiveMap to be based on MCAsmParserExtension.
llvm-svn: 108161
2010-07-12 17:54:38 +00:00
cc21af1dfb
MC/AsmParser: Switch some directive parsing to use accessor methods.
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llvm-svn: 108160
2010-07-12 17:45:27 +00:00
af3d1de891
MC: Add MCAsmParserExtension, a base class for all the target/object specific
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classes which want to extend the basic asm parser.
llvm-svn: 108158
2010-07-12 17:27:45 +00:00
4be8f2ffad
MC: Move AsmParser::TokError to MCAsmParser().
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llvm-svn: 108155
2010-07-12 17:18:45 +00:00
4042c33cd8
MC: Move getLoc() to MCAsmLexer().
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llvm-svn: 108154
2010-07-12 17:10:00 +00:00
8f36402ac2
Nope, still breaks the release selfhost bots :(
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llvm-svn: 108153
2010-07-12 16:38:48 +00:00
07b695e052
Reapply the "or" half of r108136, which seems to be less problematic.
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llvm-svn: 108152
2010-07-12 16:15:48 +00:00
1b787df129
cache result of operator*
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llvm-svn: 108150
2010-07-12 15:48:26 +00:00
68d7424a65
Don't fast-isel an x87 comparison opcode, as fast-isel doesn't
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support branching on x87 comparisons yet. This fixes PR7624.
llvm-svn: 108149
2010-07-12 15:46:30 +00:00
c719e8ae9e
Revert r108141 again, sigh.
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llvm-svn: 108148
2010-07-12 14:42:04 +00:00
96fedcb136
cache result of operator*
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llvm-svn: 108147
2010-07-12 14:15:58 +00:00
f9c38b5a45
cache result of operator*
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llvm-svn: 108146
2010-07-12 14:15:10 +00:00
88dd73b75e
cache result of operator*
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llvm-svn: 108145
2010-07-12 14:14:03 +00:00
a75ed761a9
cache result of operator*
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llvm-svn: 108144
2010-07-12 14:13:15 +00:00
15445db11b
cache results of operator*
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llvm-svn: 108143
2010-07-12 14:12:11 +00:00
a5fa885d47
cache results of operator*
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llvm-svn: 108142
2010-07-12 14:10:24 +00:00
f578c36035
Reapply 108136 with an ugly pasto fixed.
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llvm-svn: 108141
2010-07-12 13:44:00 +00:00
11743249e6
Move optimization to avoid redundant matching.
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llvm-svn: 108140
2010-07-12 13:34:22 +00:00
9675e759cf
Revert r108136 until I figure out why it broke selfhost.
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llvm-svn: 108139
2010-07-12 12:35:49 +00:00
782f62412f
cache dereferenced iterators
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llvm-svn: 108138
2010-07-12 12:03:02 +00:00
433b975fe2
recommit r108131 (hich has been backed out in r108135) with a fix
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llvm-svn: 108137
2010-07-12 12:02:10 +00:00
35473faa50
instcombine: fold (x & y) | (~x & z) and (x & y) ^ (~x & z) into ((y ^ z) & x) ^ z which is one instruction shorter. (PR6773)
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before:
%and = and i32 %y, %x
%neg = xor i32 %x, -1
%and4 = and i32 %z, %neg
%xor = xor i32 %and4, %and
after:
%xor1 = xor i32 %z, %y
%and2 = and i32 %xor1, %x
%xor = xor i32 %and2, %z
llvm-svn: 108136
2010-07-12 11:54:45 +00:00
f9610827ce
back out r108131 (of TailDuplication.cpp) for now, it causes a buildbot failure
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llvm-svn: 108135
2010-07-12 11:32:39 +00:00
6143704ac5
cache dereferenced iterators
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llvm-svn: 108134
2010-07-12 11:19:24 +00:00
8629f12bb8
cache dereferenced iterators
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llvm-svn: 108133
2010-07-12 10:59:23 +00:00
d993402df3
cache dereferenced iterators
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llvm-svn: 108132
2010-07-12 10:49:54 +00:00
2a464d7308
cache dereferenced iterators
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llvm-svn: 108131
2010-07-12 10:36:48 +00:00
41b4a6b36a
Convert some tab stops into spaces.
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llvm-svn: 108130
2010-07-12 08:16:59 +00:00
57041d81df
Add parentheses around an || to correct the logic. Also silences a GCC warning
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that was actually useful here.
Chris, please double check that this is the correct interpretation. I was
pretty sure, and ran it by Nick as well.
llvm-svn: 108129
2010-07-12 06:47:05 +00:00
d83984f623
Path::isRootDirectory is unimplemented on Unix and not used,
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remove it, fixing PR6909.
llvm-svn: 108125
2010-07-12 04:39:07 +00:00
6635f9838e
Convert getLoadStoreRegOpcode to use a switch.
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llvm-svn: 108123
2010-07-12 03:43:04 +00:00
871c724773
Convert the last use of getPhysicalRegisterRegClass and remove it.
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AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
llvm-svn: 108122
2010-07-12 02:55:34 +00:00
de7201545e
A basic block that only uses RFP registers still needs the FP_REG_KILL marker.
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This fixes PR7375.
llvm-svn: 108120
2010-07-12 02:12:47 +00:00
01c5a15dde
Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that the
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physical register can be allocated in the class of the virtual are sufficient.
I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.
llvm-svn: 108118
2010-07-12 01:45:38 +00:00
25eea4db66
fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector
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is involved.
llvm-svn: 108117
2010-07-12 01:19:22 +00:00
601e390a3b
make the prototypes for CreateMalloc and CreateFree more consistent. Patch
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by Hans Vandierendonck from PR7605
llvm-svn: 108116
2010-07-12 00:57:28 +00:00
e35d70fafa
Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
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getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.
Update getLoadStoreRegOpcode to handle GR32_AD.
llvm-svn: 108115
2010-07-12 00:52:33 +00:00
bbc25ff5cc
if jump threading is able to infer interesting values on both
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the LHS and RHS of an and/or instruction, don't multiply add
known predecessor values. This fixes the crash on testcase
from PR7498
llvm-svn: 108114
2010-07-12 00:47:34 +00:00
fd4a09fc0a
fix PR7429, a crash turning a load from a string into a float.
...
llvm-svn: 108113
2010-07-12 00:22:51 +00:00
cda39c4ee4
improve Path::makeUnique when mkstemp/mktemp are not available
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patch by Lasse Kärkkäinen in PR7404.
llvm-svn: 108110
2010-07-12 00:09:55 +00:00
0b7ae20a35
change machinelicm to use MachineInstr::isSafeToMove. No
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intended functionality change.
The avoidance of hoistiing implicitdef seems wrong though.
llvm-svn: 108109
2010-07-12 00:00:35 +00:00
b6df00c29a
first part of JIT support for address of labels, part of PR7264,
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patch by Yuri!
llvm-svn: 108107
2010-07-11 23:07:28 +00:00
2c52b7997c
introduce WinCOFFObjectWriter, patch by Michael Spencer!
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llvm-svn: 108103
2010-07-11 22:07:02 +00:00
56725be9ef
introduce WinCOFFStreamer.cpp, patch by Michael Spencer!
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llvm-svn: 108102
2010-07-11 22:05:00 +00:00
5d373c2141
If it's safe to speculatively execute load(alloca) the it's safe to execute
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load(gep(alloca)) where the gep is all-zeros. There's more we could do here but
this is a common case.
llvm-svn: 108101
2010-07-11 20:36:29 +00:00
31bd2de24e
fix typo
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llvm-svn: 108100
2010-07-11 19:42:53 +00:00
0961c55161
RISC architectures get their memory operand folding for free.
...
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
llvm-svn: 108099
2010-07-11 19:19:13 +00:00
f6c7d7fb3f
Use target independent COPY instructions for the fake fextend and fround
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operations in x87 code.
llvm-svn: 108098
2010-07-11 18:19:39 +00:00
7c1392a765
Remove redundant branch. Thanks, Anton!
...
llvm-svn: 108097
2010-07-11 17:17:35 +00:00
98ee37d878
Remove obsolete README_SSE note.
...
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.
The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.
The same applies to andps -> pand.
llvm-svn: 108096
2010-07-11 17:13:42 +00:00
c4227f1362
Remove TargetInstrInfo::copyRegToReg entirely.
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Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
llvm-svn: 108095
2010-07-11 17:01:17 +00:00
1da1cfccb1
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
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llvm-svn: 108094
2010-07-11 16:49:10 +00:00
d7c4963f2f
Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.
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The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.
The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.
llvm-svn: 108093
2010-07-11 16:45:17 +00:00
74e5bf85f7
Replace copyRegToReg with copyPhysReg for SystemZ.
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llvm-svn: 108092
2010-07-11 16:40:46 +00:00
4806848799
Avoid SSE instructions in FastIsel when it is not available.
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llvm-svn: 108091
2010-07-11 16:22:13 +00:00
34e0d14ff4
Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
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assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.
llvm-svn: 108088
2010-07-11 08:18:12 +00:00
928b593486
Replace copyRegToReg with copyPhysReg for XCore.
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llvm-svn: 108087
2010-07-11 07:56:13 +00:00
976b7b61fc
Replace copyRegToReg with copyPhysReg for Sparc.
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llvm-svn: 108086
2010-07-11 07:56:09 +00:00
1dba6814c9
Replace copyRegToReg with copyPhysReg for CellSPU.
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llvm-svn: 108084
2010-07-11 07:31:03 +00:00
0d611979a8
Replace copyRegToReg with copyPhysReg for PowerPC.
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llvm-svn: 108083
2010-07-11 07:31:00 +00:00
f889e280b8
Fix PIC16 comments referencing copyRegToReg.
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llvm-svn: 108082
2010-07-11 07:30:57 +00:00
e494d0ff3e
Replace copyRegToReg with copyPhysReg for PIC16.
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llvm-svn: 108081
2010-07-11 06:53:33 +00:00
65306369ae
Replace copyRegToReg with copyPhysReg for MSP430.
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llvm-svn: 108080
2010-07-11 06:53:30 +00:00
37a38f4b28
Replace copyRegToReg with copyPhysReg for MBlaze.
...
llvm-svn: 108079
2010-07-11 06:53:27 +00:00
d7b33002dd
Replace copyRegToReg with copyPhysReg for ARM.
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llvm-svn: 108078
2010-07-11 06:33:54 +00:00
52984e1aef
Replace copyRegToReg with copyPhysReg for Blackfin.
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llvm-svn: 108077
2010-07-11 05:44:34 +00:00
e46f3eb0c4
X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
...
llvm-svn: 108076
2010-07-11 05:44:30 +00:00
8969657f0c
Use COPY in X86FastISel::X86SelectRet.
...
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).
llvm-svn: 108074
2010-07-11 05:17:02 +00:00
51642aea77
Use COPY for fast-isel bitconvert, but don't create cross-class copies.
...
This doesn't change the behavior of SelectBitcast for X86.
llvm-svn: 108073
2010-07-11 05:16:54 +00:00
a76eccf815
Fix va_arg for doubles. With this patch VAARG nodes always contain the
...
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
llvm-svn: 108072
2010-07-11 04:01:49 +00:00
7147ab9e78
Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
...
This assumes that the registers can be copied which is probably a safe
assumption.
llvm-svn: 108070
2010-07-11 03:31:05 +00:00
3bb1267431
Use COPY in FastISel everywhere it is safe and trivial.
...
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.
llvm-svn: 108069
2010-07-11 03:31:00 +00:00
7002c31480
Replace copyRegToReg with copyPhysReg for Mips.
...
llvm-svn: 108066
2010-07-11 01:08:31 +00:00
7198d32fc6
Replace copyRegToReg with copyPhysReg for Alpha.
...
llvm-svn: 108065
2010-07-11 01:08:23 +00:00
60af0681cb
Use COPY in targets
...
llvm-svn: 108063
2010-07-10 22:43:03 +00:00
0c76d6ec21
Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
...
llvm-svn: 108062
2010-07-10 22:42:59 +00:00
ad89613b65
Only collect subreg extracting copies for later coalescing.
...
This also avoids fatal copies from physregs.
llvm-svn: 108061
2010-07-10 22:42:53 +00:00
a64a323564
Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
...
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.
llvm-svn: 108060
2010-07-10 22:42:31 +00:00
82b21c086e
The accumulator tail recursion transform claims to work for any associative
...
operation, but the way it's implemented requires the operation to also be
commutative. So add a check for commutativity (and tweak the corresponding
comments). This makes no difference in practice since every associative
LLVM instruction is also commutative! Here's an example to show the need
for commutativity: the accum_recursion.ll testcase calculates the factorial
function. Before the transformation the result of a call is
((((1*1)*2)*3)...)*x
while afterwards it is
(((1*x)*(x-1))...*2)*1
which clearly requires both associativity and commutativity of * to be equal
to the original.
llvm-svn: 108056
2010-07-10 20:31:42 +00:00
e50d30d586
Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
...
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.
This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.
llvm-svn: 108050
2010-07-10 19:08:25 +00:00
de457896b6
Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.
...
Based on a patch by Rafael Espíndola.
Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.
We support:
FpSET_ST0
INLINEASM
FpSET_ST0
FpSET_ST1
INLINEASM
with and without kills on the arguments. We don't support:
FpSET_ST1
FpSET_ST0
INLINEASM
nor
FpSET_ST1
INLINEASM
Just Don't Do It!
llvm-svn: 108047
2010-07-10 17:42:34 +00:00
fbdba81550
Insert IMPLICIT_DEF instructions at the current insert position, not
...
at the end of the block.
llvm-svn: 108045
2010-07-10 13:55:45 +00:00
d162d85688
Add parentheses yet again to satisfy GCC's warnings.
...
llvm-svn: 108043
2010-07-10 12:06:22 +00:00
d7b5ce3312
Reapply bottom-up fast-isel, with several fixes for x86-32:
...
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
llvm-svn: 108039
2010-07-10 09:00:22 +00:00
be8d9b0bb8
An x86 function returns a floating point value in st(0), and we must make sure
...
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.
This will matter when CopyFromReg gets lowered to a generic COPY instruction.
llvm-svn: 108037
2010-07-10 04:04:25 +00:00
57e72370ae
Update DBG_VALUE to refer appropriate stack slot in case of a spill.
...
llvm-svn: 108023
2010-07-09 21:48:31 +00:00
5e6c2155a3
Declare YMM subregisters in the right way! Thanks Jakob
...
llvm-svn: 108022
2010-07-09 21:46:19 +00:00
2419606bfb
Add AVX 256-bit packed MOVNT variants
...
llvm-svn: 108021
2010-07-09 21:42:42 +00:00
e2614a9979
Remember the *_TC opcodes for load/store
...
llvm-svn: 108020
2010-07-09 21:27:55 +00:00
6bc772eec7
Add AVX 256-bit unpack and interleave
...
llvm-svn: 108017
2010-07-09 21:20:35 +00:00
b5c899d11b
Fix small bug in isMoveInstr -> COPY translation
...
llvm-svn: 108013
2010-07-09 20:55:49 +00:00
7a7b55eb67
Automatically fold COPY instructions into stack load/store.
...
llvm-svn: 108012
2010-07-09 20:43:13 +00:00
51702ec46b
Fix a few tests
...
llvm-svn: 108011
2010-07-09 20:43:09 +00:00
e9fdcaa68a
Remat uncoalescable COPY instrs
...
llvm-svn: 108010
2010-07-09 20:43:05 +00:00
2a5725b1a3
In the presence of variable sized objects, allocate an emergency spill slot.
...
rdar://8131327
llvm-svn: 108008
2010-07-09 20:27:06 +00:00
f831d86311
Clarify what mysterious check means.
...
llvm-svn: 108005
2010-07-09 19:44:12 +00:00
7929c448fc
Fix MachineLICM to actually visit inner loops.
...
llvm-svn: 108001
2010-07-09 18:49:45 +00:00
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
bd953d1805
Change TII::foldMemoryOperand API to require the machine instruction to be
...
inserted in a MBB, and return an already inserted MI.
This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.
The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.
llvm-svn: 107991
2010-07-09 17:29:08 +00:00
9d5ae03404
cache result of operator*
...
llvm-svn: 107990
2010-07-09 16:51:20 +00:00
8e66a42784
remove useless cast and fix typos in comment
...
llvm-svn: 107989
2010-07-09 16:42:04 +00:00
3b740e9085
cache result of operator*
...
llvm-svn: 107988
2010-07-09 16:39:02 +00:00
6586e9b203
--- Reverse-merging r107947 into '.':
...
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 107987
2010-07-09 16:37:18 +00:00
fd8e7d4a0f
cache result of operator*
...
llvm-svn: 107984
2010-07-09 16:31:08 +00:00
e7650c7c29
cache result of operator*
...
llvm-svn: 107983
2010-07-09 16:26:41 +00:00
aa389f5085
cache result of operator*
...
llvm-svn: 107982
2010-07-09 16:22:36 +00:00
04af1e4f65
cache result of operator*
...
llvm-svn: 107981
2010-07-09 16:17:52 +00:00
52617fc462
cache result of operator*
...
llvm-svn: 107980
2010-07-09 16:08:33 +00:00
2c0ab48ac2
cache result of operator*
...
llvm-svn: 107979
2010-07-09 16:01:21 +00:00
070b9a2cc4
cache result of operator*
...
llvm-svn: 107978
2010-07-09 15:53:42 +00:00
d9a0e80213
cache result of operator*
...
llvm-svn: 107977
2010-07-09 15:52:36 +00:00
e82532a1c5
cache result of operator*
...
llvm-svn: 107976
2010-07-09 15:40:10 +00:00
6d8870fc35
cache result of operator*
...
llvm-svn: 107975
2010-07-09 15:25:42 +00:00
329c4d8ed9
cache result of operator*
...
llvm-svn: 107974
2010-07-09 15:25:09 +00:00
0028cc6730
cache result of operator*
...
llvm-svn: 107972
2010-07-09 15:01:36 +00:00
d323f5e161
cache result of operator* (found by inspection)
...
llvm-svn: 107971
2010-07-09 14:48:08 +00:00
b0d56ffc85
cache result of operator*
...
llvm-svn: 107969
2010-07-09 14:36:49 +00:00
4247949ce9
cache result of operator*
...
llvm-svn: 107968
2010-07-09 14:29:14 +00:00
2732561be9
cache result of operator*
...
llvm-svn: 107967
2010-07-09 14:28:41 +00:00
a02f232c1b
cache result of operator*
...
llvm-svn: 107966
2010-07-09 14:18:23 +00:00
f0821f39ee
cache operator*'s result (in multiple functions)
...
llvm-svn: 107965
2010-07-09 14:02:13 +00:00
1d20021d82
do not repeatedly dereference use_iterator
...
llvm-svn: 107963
2010-07-09 13:17:13 +00:00
60a346d0f1
do not repeatedly dereference use_iterator
...
llvm-svn: 107962
2010-07-09 12:23:50 +00:00
d4d9e53b20
Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.
...
This fixes PR7602.
llvm-svn: 107957
2010-07-09 05:56:21 +00:00
cac54d6435
Deal with a few remaining spots that assume physical registers have live intervals.
...
This fixes PR7601.
llvm-svn: 107955
2010-07-09 04:35:38 +00:00
992d25da71
Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
...
fields to use.
llvm-svn: 107952
2010-07-09 01:56:45 +00:00
66b3649030
Fix broken isCopy handling in TrimLiveIntervalToLastUse.
...
llvm-svn: 107950
2010-07-09 01:27:21 +00:00
5165fa1c39
Handle COPY in VirtRegRewriter.
...
llvm-svn: 107949
2010-07-09 01:27:19 +00:00
0a7d155d67
Fix the memoperand offsets in code generated for va_start.
...
llvm-svn: 107948
2010-07-09 01:06:48 +00:00
88c185617c
have the mc lowering process handle a few tail call forms, lowering them to
...
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
llvm-svn: 107946
2010-07-09 00:49:41 +00:00
88a4e6dc0e
Print "dregpair" NEON operands with a space between them, for readability and
...
consistency with other instructions that have lists of register operands.
llvm-svn: 107944
2010-07-09 00:47:20 +00:00
0b5aa1cdd3
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
...
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
llvm-svn: 107943
2010-07-09 00:39:23 +00:00
e6cc0d33bb
Factor out x86 segment override prefix encoding, and also use it for VEX
...
llvm-svn: 107942
2010-07-09 00:38:14 +00:00
21eed476e8
Reenable DAG combining for vector shuffles. It looks like it was temporarily
...
disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
llvm-svn: 107941
2010-07-09 00:38:12 +00:00
061d70ad2c
reject pseudo instructions early in the encoder.
...
llvm-svn: 107939
2010-07-09 00:17:50 +00:00
b652c1a145
Remove trailing whitespaces from file
...
llvm-svn: 107937
2010-07-09 00:07:19 +00:00
f469307c77
Change LEA to have 5 operands for its memory operand, just
...
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
llvm-svn: 107934
2010-07-08 23:46:44 +00:00
d08fb75aaa
Reverting r107918 and r107919. Radar 8063111.
...
llvm-svn: 107930
2010-07-08 23:25:39 +00:00
823e90e12a
Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse"
...
This reverts commit 107921. It broke the clang self host.
llvm-svn: 107926
2010-07-08 22:52:47 +00:00
ec536276f0
add some long-overdue enums to refer to the parts of the 5-operand
...
X86 memory operand.
llvm-svn: 107925
2010-07-08 22:41:28 +00:00
4c6bd6612f
Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function.
...
This fixes PR7596 .
llvm-svn: 107923
2010-07-08 22:39:20 +00:00
a992445ff2
Extension of r107506. Make sure that we don't mark a function as having a call
...
if the inline ASM doesn't need a stack frame.
llvm-svn: 107922
2010-07-08 22:38:02 +00:00
75c465585a
Fix broken isCopy handling in TrimLiveIntervalToLastUse
...
llvm-svn: 107921
2010-07-08 22:30:38 +00:00
ec58a43d81
Remember the VR64 register class
...
llvm-svn: 107920
2010-07-08 22:30:35 +00:00
43d226deea
Fix decl/def debug info for template functions. Radar 8063111.
...
llvm-svn: 107919
2010-07-08 22:28:59 +00:00
9f034c1e5d
Rework segment prefix emission code to handle segments
...
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
1dd82c7dc2
introduce a new X86II::getMemoryOperandNo method, which
...
returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
llvm-svn: 107916
2010-07-08 22:27:06 +00:00
d799ea52cd
Switch SPU calling convention (function arguments)
...
to a Tablegen implementation.
llvm-svn: 107913
2010-07-08 21:15:22 +00:00
ea9207cd7a
Revert some unneeded parts of the change in r107886 for the
...
.weak_def_can_be_hidden directive. Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these. And
when that happens it will be more convenient for it to be a bool than a const
char*.
llvm-svn: 107906
2010-07-08 20:30:44 +00:00
0f54854a1d
Check for FiniteOnlyFPMath as well.
...
llvm-svn: 107904
2010-07-08 20:12:24 +00:00
9c160e1213
Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.
...
llvm-svn: 107903
2010-07-08 20:10:35 +00:00
63a622b768
Teach the x86 floating point stackifier to handle COPY instructions.
...
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.
Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.
llvm-svn: 107899
2010-07-08 19:46:30 +00:00
930f8082c3
Implement X86InstrInfo::copyPhysReg
...
llvm-svn: 107898
2010-07-08 19:46:25 +00:00
181e5af248
The NEONPreAllocPass should never have to assign fixed registers anymore.
...
This pass can go away entirely soon.
llvm-svn: 107892
2010-07-08 17:45:26 +00:00
1eade1a327
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
...
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
llvm-svn: 107890
2010-07-08 17:44:00 +00:00
082d0fd7ad
Added the darwin .weak_def_can_be_hidden directive.
...
llvm-svn: 107886
2010-07-08 17:22:42 +00:00
6c25043493
Clean up a comment.
...
llvm-svn: 107882
2010-07-08 16:54:45 +00:00
c280fc7514
Clean up scavengeRegister() a bit to prefer available regs, which allows
...
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.
llvm-svn: 107880
2010-07-08 16:49:26 +00:00
00264624a9
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
llvm-svn: 107879
2010-07-08 16:40:22 +00:00
a1e883dcf6
Remove references to INSERT_SUBREG after de-SSA.
...
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.
llvm-svn: 107878
2010-07-08 16:40:15 +00:00
0ae3f08c0d
Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
...
llvm-svn: 107868
2010-07-08 12:09:56 +00:00
2321e6a4d4
Teach instcombine to transform
...
(X >s -1) ? C1 : C2 and (X <s 0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.
This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.
for
int sel(int n) {
return n >= 0 ? 60 : 100;
}
we now generate
sarl $31, %edi
andl $40, %edi
leal 60(%rdi), %eax
instead of
testl %edi, %edi
movl $60, %ecx
movl $100, %eax
cmovnsl %ecx, %eax
llvm-svn: 107866
2010-07-08 11:39:10 +00:00
e796253217
A slight reworking of the custom patterns for x86-64 tpoff codegen and
...
correct the testcase for valid assembly.
Needs more tests.
llvm-svn: 107860
2010-07-08 07:36:46 +00:00
be1f7a931e
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
...
llvm-svn: 107856
2010-07-08 06:01:49 +00:00
89a4e25007
Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.
...
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.
Any remaining calls to copyRegToReg wil be replaced by COPY instructions.
llvm-svn: 107854
2010-07-08 05:01:41 +00:00
25f9364cbd
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
...
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
llvm-svn: 107852
2010-07-08 02:08:50 +00:00
e2289285ae
Changes to ARM tail calls, mostly cosmetic.
...
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
e75704369d
Revert 107840 107839 107813 107804 107800 107797 107791.
...
Debug info intrinsics win for now.
llvm-svn: 107850
2010-07-08 01:00:56 +00:00
6533f24370
When processing frame index virtual registers, consider all available registers
...
(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760
llvm-svn: 107847
2010-07-08 00:38:54 +00:00
efa3c824cc
Fix the second half of PR7437: scalarrepl wasn't preserving
...
address spaces when SRoA'ing memcpy's.
llvm-svn: 107846
2010-07-08 00:27:05 +00:00
eb9164dc50
Don't forward-declare registers for static allocas, which we'll
...
prefer to materialize as local constants. This fixes the clang
bootstrap abort.
llvm-svn: 107840
2010-07-07 23:52:58 +00:00
1adc499dda
Fix -fast-isel-abort to check the right instruction.
...
llvm-svn: 107839
2010-07-07 23:47:25 +00:00
9380b81837
use PrintEscapedString to handle attribute section with escapes in it,
...
PR7399. The asm parser already handles this. This is of dubious
utility (see the PR) but the asmprinter was clearly broken here.
llvm-svn: 107834
2010-07-07 23:16:37 +00:00
6213ab789f
fix copies to/from GR8_ABCD_H even more
...
llvm-svn: 107832
2010-07-07 23:04:56 +00:00
73ef80f76f
grammar
...
llvm-svn: 107831
2010-07-07 22:53:35 +00:00
40eda1076a
Handle cases where the post-RA scheduler may move instructions between the
...
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
llvm-svn: 107830
2010-07-07 22:51:22 +00:00
05ea2a4791
finish up support for callw: PR7195
...
llvm-svn: 107826
2010-07-07 22:35:13 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
6c61451011
Add more assembly opcodes for SSE compare instructions
...
llvm-svn: 107823
2010-07-07 22:24:03 +00:00
a37a95ea2f
One MDNode may be used to create regular DIE as well as abstract DIE.
...
Keep track of abstract subprogram DIEs.
llvm-svn: 107822
2010-07-07 22:20:57 +00:00
1c349f18f8
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
...
llvm-svn: 107820
2010-07-07 22:15:37 +00:00
32a600b494
Print undefined/unknown debug value as "undef".
...
llvm-svn: 107818
2010-07-07 21:52:21 +00:00
25d5c1b4f8
Not all custom inserters create new basic blocks. If the inserter
...
didn't create a new block, don't reset the insert position.
llvm-svn: 107813
2010-07-07 21:18:22 +00:00
e4ba2aa0c4
grammar and trailing whitespace
...
llvm-svn: 107811
2010-07-07 21:06:51 +00:00
9a0339fc1f
Rename couple of maps.
...
llvm-svn: 107810
2010-07-07 20:49:57 +00:00
ddaf0099a5
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
...
This fixes PR7540.
llvm-svn: 107809
2010-07-07 20:33:27 +00:00
30265c4f8b
80 cols.
...
llvm-svn: 107807
2010-07-07 20:12:52 +00:00
e7ccc51cc1
Implement bottom-up fast-isel. This has the advantage of not requiring
...
a separate DCE pass over MachineInstrs.
llvm-svn: 107804
2010-07-07 19:20:32 +00:00
2d4d01d0de
Add X86FastISel support for return statements. This entails refactoring
...
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
2010-07-07 18:32:53 +00:00
fd8060335b
Add AVX AES instructions
...
llvm-svn: 107798
2010-07-07 18:24:20 +00:00
b792f844ad
Update the insert position after scheduling, which may change the
...
position when emitting multiple blocks when executing a custom
inserter.
llvm-svn: 107797
2010-07-07 18:22:13 +00:00
637ee5f149
Update comment.
...
llvm-svn: 107796
2010-07-07 18:18:18 +00:00
769201448d
Fix debugging strings.
...
llvm-svn: 107795
2010-07-07 17:28:45 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
e784616fbb
Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will
...
allow target-specific fast-isel code to make use of it directly.
llvm-svn: 107787
2010-07-07 16:01:37 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
ca97c92eb4
add some triple for minix, patch by Kees van Reeuwijk from PR7582
...
llvm-svn: 107785
2010-07-07 15:52:27 +00:00
498e5f899d
Move CallingConvLower.cpp out of the SelectionDAG directory.
...
llvm-svn: 107781
2010-07-07 15:15:27 +00:00
8e1338eea8
Fix more places assuming subregisters have live intervals
...
llvm-svn: 107780
2010-07-07 14:41:22 +00:00
88c547ede9
Add a getFirstNonPHI utility function.
...
llvm-svn: 107778
2010-07-07 14:33:51 +00:00
5b0a8a863f
Minore code simplification.
...
llvm-svn: 107777
2010-07-07 14:30:04 +00:00
00ef93258a
Remove interprocedural-basic-aa and associated code. The AliasAnalysis
...
interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.
Document that AliasAnalysis doesn't support cross-function queries.
llvm-svn: 107776
2010-07-07 14:27:09 +00:00
a22e8148d4
conditionalize by CallInst::ArgOffset
...
llvm-svn: 107767
2010-07-07 10:34:03 +00:00
408bb192de
Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
...
builds to "Release". The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts. The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown). This will bring them
in line with MacOS releases, which ship with assertions disabled. It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.
llvm-svn: 107758
2010-07-07 07:48:00 +00:00
6d122aef97
Add AVX SSE4.2 instructions
...
llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
...
llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
...
llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f0e551d4f4
Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
...
Buildbot breakage.
llvm-svn: 107744
2010-07-07 00:32:25 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
...
they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
e2d3067f6b
Remove references to INSERT_SUBREG after de-SSA
...
llvm-svn: 107732
2010-07-06 23:40:35 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
70ee3ecd33
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
...
INSERT_SUBREG will now only appear in SSA machine instructions.
Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.
llvm-svn: 107726
2010-07-06 23:26:25 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
...
This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
...
llvm-svn: 107701
2010-07-06 21:26:18 +00:00
15fed3bd30
One more case assuming that subregs have live ranges.
...
llvm-svn: 107700
2010-07-06 21:13:03 +00:00
bcf3409107
Fix buildbot breakage where a def is missing.
...
llvm-svn: 107698
2010-07-06 21:06:39 +00:00
b36df17b08
Add fixme.
...
llvm-svn: 107697
2010-07-06 21:05:17 +00:00
a64c0a3d22
Be more forgiving when calculating alias interference for physreg coalescing.
...
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.
This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.
llvm-svn: 107695
2010-07-06 20:31:51 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
dfc8b745a2
Fix to 80-col.
...
llvm-svn: 107684
2010-07-06 18:35:20 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
dde2ba0b60
tighten up this code.
...
llvm-svn: 107670
2010-07-06 15:59:27 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
4e49b59dad
Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
...
which do not depend on SelectionDAG.
llvm-svn: 107666
2010-07-06 15:39:54 +00:00
2b2a1c3c86
Make getMinimalPhysRegClass' comment mention what makes it different
...
from getPhysicalRegisterRegClass.
llvm-svn: 107660
2010-07-06 15:31:55 +00:00
e415230477
Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
...
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').
llvm-svn: 107658
2010-07-06 15:24:56 +00:00
1e33b18e28
Add some more TODO comments.
...
llvm-svn: 107657
2010-07-06 15:23:00 +00:00
f855b39edd
Add a comment.
...
llvm-svn: 107656
2010-07-06 15:21:57 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
dace239949
Detabify this file.
...
llvm-svn: 107637
2010-07-06 03:53:43 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
d5ac287140
Remove some unused/redundant code.
...
llvm-svn: 107622
2010-07-05 18:40:09 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
2c0315a0f3
random tidying
...
llvm-svn: 107612
2010-07-05 05:36:21 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
ac0a210789
Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
...
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
f3aeb2c22c
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
...
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
f844642350
Proper indentation.
...
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
c8f595212f
Minor amendment to switch-lowering improvement.
...
llvm-svn: 107569
2010-07-03 08:43:32 +00:00
836fdbc85b
Note switch-lowering inefficiency.
...
llvm-svn: 107565
2010-07-03 07:38:12 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
128a0197bb
Fix typo.
...
llvm-svn: 107556
2010-07-03 01:09:18 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
...
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
621c85b038
Add AVX SSE4.1 round instructions
...
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
4c82a9e7d0
Detect and handle COPY in many places.
...
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.
llvm-svn: 107547
2010-07-03 00:04:37 +00:00
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
...
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
5e5416056b
80-col fixup.
...
llvm-svn: 107537
2010-07-02 23:17:38 +00:00
676a15bdf5
Add a new target independent COPY instruction and code to lower it.
...
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
llvm-svn: 107529
2010-07-02 22:29:50 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
...
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
3c43248560
Custom inserters (e.g., conditional moves in Thumb1 can introduce
...
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.
rdar://8022442
llvm-svn: 107517
2010-07-02 21:23:37 +00:00
cefe3831b7
MDString is already checked earlier.
...
llvm-svn: 107516
2010-07-02 21:13:23 +00:00
c3525dc0fd
Remove early IT block formation. It's not used.
...
llvm-svn: 107513
2010-07-02 21:07:09 +00:00
0ce84486c3
- Two-address pass should not assume unfolding is always successful.
...
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
llvm-svn: 107509
2010-07-02 20:36:18 +00:00
4d887f7ca7
Propagate the AlignStack bit in InlineAsm's to the
...
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
llvm-svn: 107506
2010-07-02 20:16:09 +00:00
df8429aeb4
Remove invalid assert
...
llvm-svn: 107505
2010-07-02 19:54:47 +00:00
cf6c5c960f
Properly handle debug values during inline spilling.
...
llvm-svn: 107503
2010-07-02 19:54:40 +00:00
9da02a83e9
beautify output
...
llvm-svn: 107500
2010-07-02 19:26:28 +00:00
e537ddbdb4
use ArgOperand API
...
llvm-svn: 107498
2010-07-02 19:08:46 +00:00
832282e061
Don't claim to preserve AliasAnalysis. First, this is doesn't actually
...
have any effect, and second, deleting stores can potentially invalidate
an AliasAnalysis, and there's currently no notification for this.
llvm-svn: 107496
2010-07-02 18:43:05 +00:00
96037187e5
Rematerialize as much as possible before inserting spills and reloads.
...
This allows us to recognize the common case where all uses could be
rematerialized, and no stack slot allocation is necessary.
If some values could be fully rematerialized, remove them from the live range
before allocating a stack slot for the rest.
llvm-svn: 107492
2010-07-02 17:44:57 +00:00
9b7755fbc6
80-column and trailing whitespace cleanup.
...
llvm-svn: 107490
2010-07-02 17:41:59 +00:00
64a4f3f062
grammar tweaks
...
llvm-svn: 107489
2010-07-02 17:38:34 +00:00
771d04b969
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
...
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
llvm-svn: 107487
2010-07-02 17:23:44 +00:00
56de4675b6
use ArgOperand API (found by my previous commit)
...
llvm-svn: 107482
2010-07-02 13:37:16 +00:00
ee8d80d6a3
IndirectBr is not safe to speculatively execute (!)
...
llvm-svn: 107454
2010-07-02 00:35:34 +00:00
93f5920914
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
...
llvm-svn: 107451
2010-07-02 00:10:16 +00:00
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
...
llvm-svn: 107448
2010-07-01 23:10:49 +00:00
504055ce9e
Make the "linker_private" linkage type emit a non-weak symbol to the file. It
...
will still be stripped by the linker when it generates the final image.
llvm-svn: 107440
2010-07-01 22:38:24 +00:00
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
...
llvm-svn: 107438
2010-07-01 22:33:18 +00:00
8a99b730a9
ARM function alignments were off by a power of two. svn 83242 changed
...
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
llvm-svn: 107435
2010-07-01 22:26:26 +00:00
03bcd6ecc8
Implement the "linker_private_weak" linkage type. This will be used for
...
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.
For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
Currently only supported on Darwin platforms.
llvm-svn: 107433
2010-07-01 21:55:59 +00:00
429397529a
Do not require line number entry for undefined local variable.
...
This is a regression caused by r106792 and caught by gdb testsuite.
llvm-svn: 107430
2010-07-01 21:38:08 +00:00
0e980755d3
MC: Fix some stray hunks I didn't intend to commit.
...
llvm-svn: 107428
2010-07-01 20:48:51 +00:00
02877d6e85
MC: Pass the target instance to the AsmParser constructor.
...
llvm-svn: 107426
2010-07-01 20:41:56 +00:00
0aa4365e47
MC: Fix an error message.
...
llvm-svn: 107424
2010-07-01 20:20:01 +00:00
84f90a387d
Remove context sensitivity concerns from interprocedural-basic-aa, and
...
make it more aggressive in cases where both pointers are known to live
in the same function.
llvm-svn: 107420
2010-07-01 20:08:40 +00:00
329d202362
MC: Move COFF enumeration constants to llvm/Support/COFF.h, patch by Michael
...
Spencer!
llvm-svn: 107418
2010-07-01 20:07:24 +00:00
2b434e12cd
Debugging infomration is encoded in llvm IR using metadata. This is designed
...
such a way that debug info for symbols preserved even if symbols are
optimized away by the optimizer.
Add new special pass to remove debug info for such symbols.
llvm-svn: 107416
2010-07-01 19:49:20 +00:00
b9e2e4b762
If a named mdnode is removed then mark module as changed.
...
llvm-svn: 107412
2010-07-01 18:27:46 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
d2965c10a1
Temporarily disable on-demand fast-isel.
...
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
9dc154bcb4
reformulate CallSite::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private
...
llvm-svn: 107390
2010-07-01 10:41:37 +00:00
42b7ee15f5
Use FuncInfo's isExportedInst accessor method instead of
...
doing the work manually.
llvm-svn: 107384
2010-07-01 03:57:05 +00:00
85e02e9340
Rename CreateRegForValue to CreateReg, and change its argument
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from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
2010-07-01 03:55:39 +00:00
4d29fd85f9
Fast isel no longer needs DeadMachineInstrElim to clean up after it.
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llvm-svn: 107381
2010-07-01 03:49:59 +00:00
aef3d140b7
Teach fast-isel to avoid loading a value from memory when it's already
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available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
llvm-svn: 107380
2010-07-01 03:49:38 +00:00
722f5fc567
Enable on-demand fast-isel.
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llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
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to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
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llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
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the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
d432223163
Reapply r106422, splitting the code for materializing a value out of
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SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
2010-07-01 01:59:43 +00:00
9576645a84
Don't use operator[] here, because it's not desirable to insert a default
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value if the search fails.
llvm-svn: 107368
2010-07-01 01:33:21 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
22fa66cf2b
80-col violation.
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llvm-svn: 107361
2010-07-01 01:00:27 +00:00
4721ad855e
Trailing whitespace.
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llvm-svn: 107360
2010-07-01 01:00:22 +00:00
8656a4549a
Add memory operand folding support to InlineSpiller.
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llvm-svn: 107355
2010-07-01 00:13:04 +00:00
Bruno Cardoso Lopes