1f7071a3e4
Fix headers.
...
llvm-svn: 108413
2010-07-15 06:05:18 +00:00
e7e6ca5c57
Use std::vector instead of a hard-coded array. The length of that array could
...
get *very* large, but we only need it to be the size of the number of pregs.
llvm-svn: 108412
2010-07-15 06:04:38 +00:00
d5b390189d
Use std::vector instead of a hard-coded array. The length of that array could
...
get *very* large, but we only need it to be the size of thenumber of pregs.
llvm-svn: 108411
2010-07-15 05:56:32 +00:00
8b3a17e613
Revert r108401; it breaks bootstrap :(
...
llvm-svn: 108407
2010-07-15 05:09:31 +00:00
fd473a746c
Add AssertingVH which makes PR7647 break consistently.
...
llvm-svn: 108401
2010-07-15 04:46:14 +00:00
e4be4308a9
Random note about bswap.
...
llvm-svn: 108396
2010-07-15 02:20:38 +00:00
28fd6785bc
a more graceful fix for test/Other/inline-asm-newline-terminator.ll,
...
follow on to r103765
llvm-svn: 108390
2010-07-15 00:37:34 +00:00
a8b4e3732b
Speculatively revert r108378; may be causing bootstrap failures.
...
llvm-svn: 108389
2010-07-15 00:33:00 +00:00
8b1bb8cfbd
Last COPY conversion.
...
llvm-svn: 108387
2010-07-14 23:58:21 +00:00
0b9aafddc5
Remove restriction on NEON alignment values. Some of the NEON ld/st
...
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.
llvm-svn: 108386
2010-07-14 23:54:43 +00:00
9b449d5a92
Use TargetOpcode::COPY instead of X86-native register copy instructions when
...
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.
llvm-svn: 108385
2010-07-14 23:50:27 +00:00
474e56a2bf
80-col.
...
llvm-svn: 108381
2010-07-14 23:41:32 +00:00
37d91d84af
Add instcombine transforms to optimize tests of multiple bits of the same value into a single larger comparison.
...
llvm-svn: 108378
2010-07-14 23:33:51 +00:00
f10cd5c6cb
Make the order in which variables are described in debug information
...
independent of the order that isel happens to visit the dbg_declare
intrinsics. This fixes a bug in which the formal arguments were
being printed in reverse order, now that fast isel is going bottom up.
llvm-svn: 108369
2010-07-14 23:08:16 +00:00
769aedd523
fix indentation
...
llvm-svn: 108368
2010-07-14 23:04:59 +00:00
92d8998348
Don't pass StringRef by reference.
...
llvm-svn: 108366
2010-07-14 22:38:02 +00:00
c12a6731c5
Properly restore DebugLoc after leaving the local constant area.
...
llvm-svn: 108364
2010-07-14 22:01:31 +00:00
1513217e27
Just use getParent() instead of getModuleFromVal when the value is a Function.
...
llvm-svn: 108358
2010-07-14 21:12:44 +00:00
efb8dbb3f1
Rename WriteConstantInt to WriteConstantInternal, to avoid confusion.
...
llvm-svn: 108357
2010-07-14 20:57:55 +00:00
2cfe91379b
Extend SimplifyCFG's common-destination folding heuristic to allow a single
...
"bonus" instruction to be speculatively executed. Add a heuristic to
ensure we're not tripping up out-of-order execution by checking that this bonus
instruction only uses values that were already guaranteed to be available.
This allows us to eliminate the short circuit in (x&1)&&(x&2).
llvm-svn: 108351
2010-07-14 19:52:16 +00:00
8939ba337d
Factor out metadata parsing into a separate function.
...
llvm-svn: 108343
2010-07-14 18:26:50 +00:00
254858031a
Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,
...
patch by Michael Spencer!
llvm-svn: 108342
2010-07-14 18:14:33 +00:00
a90af1ba38
Improve 64-subtraction of immediates when parts of the immediate can fit
...
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
llvm-svn: 108339
2010-07-14 17:45:16 +00:00
042523340b
Delete fast-isel's trivial load optimization; it breaks debugging because
...
it can look past points where a debugger might modify user variables.
llvm-svn: 108336
2010-07-14 17:25:37 +00:00
1aef53403f
Add missing address register update to t2LDM_RET instruction.
...
Patch by Brian Lucas. PR7636.
llvm-svn: 108332
2010-07-14 16:02:13 +00:00
7a68cd094b
Rather than using an ifdef on the target to zero out fields,
...
just use memset to zero the entire struct.
llvm-svn: 108330
2010-07-14 14:32:33 +00:00
c4d70125ee
A couple potential optimizations inspired by comment 4 in PR6773.
...
llvm-svn: 108328
2010-07-14 06:58:26 +00:00
a8e8874552
Fix for PR7193 was overly conservative. The only case where sibcall callee
...
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.
This fixes PR7610.
llvm-svn: 108327
2010-07-14 06:44:01 +00:00
bad47f62f6
Add support for NEON VMVN immediate instructions.
...
llvm-svn: 108324
2010-07-14 06:31:50 +00:00
bd54a53628
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
...
of the value of the immediate.
llvm-svn: 108323
2010-07-14 06:30:44 +00:00
ec0e7b1643
revert r108320, I see the failures now...
...
llvm-svn: 108322
2010-07-14 06:16:35 +00:00
658680b2f5
reapply benjamin's instcombine patch, I don't see anything wrong with it and can't repro any problems with a manual self-host.
...
llvm-svn: 108320
2010-07-14 05:59:13 +00:00
164a0775bb
fix a bug found by a warning I added to clang this morning.
...
llvm-svn: 108309
2010-07-14 01:57:17 +00:00
d542414945
Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620.
...
llvm-svn: 108304
2010-07-14 01:22:19 +00:00
103a0dcfe1
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
...
Radar 7373643.
llvm-svn: 108303
2010-07-14 01:22:12 +00:00
1f471435f8
Don't propagate debug locations to instructions for materializing
...
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.
llvm-svn: 108302
2010-07-14 01:07:44 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
...
llvm-svn: 108286
2010-07-13 22:06:38 +00:00
cd7a40f4ec
Print VNInfo flags.
...
llvm-svn: 108277
2010-07-13 21:19:05 +00:00
a3f1901531
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
...
NEON VMOV-immediate instructions. This simplifies some things.
llvm-svn: 108275
2010-07-13 21:16:48 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
...
Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
caca5488dc
In inline asm treat indirect 'X' constraint as 'm'.
...
This may not be right in all cases, but it's better
than asserting which it was doing before. PR 7528.
llvm-svn: 108268
2010-07-13 20:17:05 +00:00
76a6b663a3
Added a check that pusha cannot be encoded in 64-bit mode.
...
llvm-svn: 108265
2010-07-13 20:05:41 +00:00
fc4b8b8e80
Add an assertion to make PR7542 fail consistently.
...
LiveInterval::overlapsFrom dereferences end() if it is called on an empty
interval.
It would be reasonable to just return false - an empty interval doesn't overlap
anything, but I want to know who is doing it first.
llvm-svn: 108264
2010-07-13 19:56:28 +00:00
afd69cf5b7
Add support for empty named metadata too. This isn't particularly
...
useful, but it is nice for consistency.
llvm-svn: 108262
2010-07-13 19:42:44 +00:00
b43455feaf
Fix LiveInterval::overlaps so it doesn't claim touching intervals overlap.
...
Also, one binary search is enough.
llvm-svn: 108261
2010-07-13 19:42:20 +00:00
1e0213a758
Add support for empty metadata nodes: !{}.
...
llvm-svn: 108259
2010-07-13 19:33:27 +00:00
0cc4ad983d
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
...
llvm-svn: 108258
2010-07-13 19:27:42 +00:00
58066e337d
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
...
llvm-svn: 108256
2010-07-13 19:21:50 +00:00
f43961007c
-enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.
...
llvm-svn: 108254
2010-07-13 18:46:14 +00:00
ea282034b6
Grammar.
...
llvm-svn: 108252
2010-07-13 18:27:13 +00:00
f88a284579
Handle the case of a tail recursion in which the tail call is followed
...
by a return that returns a constant, while elsewhere in the function
another return instruction returns a different constant. This is a
special case of accumulator recursion, so just generalize the existing
logic a bit.
llvm-svn: 108241
2010-07-13 15:41:41 +00:00
03e7e68caa
rotate CallInst operands
...
with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)
this ordering is now consistent with InvokeInst
this commit only flips the switch,
functionally it is equivalent to
r101465
I intend to commit several cleanups after a few
days of soak period
llvm-svn: 108240
2010-07-13 15:31:36 +00:00
c1c6f4796e
Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
...
avoid replicated code.
llvm-svn: 108227
2010-07-13 04:44:34 +00:00
55595fb291
my work on adding segment registers to LEA missed the
...
disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
dff283e146
Add AVX 256-bit packed logical forms
...
llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
...
llvm-svn: 108223
2010-07-13 01:53:31 +00:00
77a3c4462f
Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions
...
llvm-svn: 108222
2010-07-13 00:38:47 +00:00
54e620d2c7
Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results,
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they already have one.
This fixes the himenobmtxpa miscompilation on ARM.
The PostRA scheduler got confused by the double memoperand and hoisted a stack
slot load above a store to the same slot.
llvm-svn: 108219
2010-07-13 00:23:30 +00:00
03264efe30
Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
...
utility classes can be used from multiple files. This will aid
transitioning to a new refactored x86 SIMD specification.
llvm-svn: 108213
2010-07-12 23:41:28 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
...
llvm-svn: 108207
2010-07-12 23:04:15 +00:00
91806311c9
More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
...
llvm-svn: 108204
2010-07-12 22:41:32 +00:00
ab058b83e0
MC/AsmParser: Move ELF specific parser to ELFAsmParser.cpp.
...
llvm-svn: 108196
2010-07-12 21:23:32 +00:00
0cb91cfc74
MC/AsmParser: Move Darwin specific parse to DarwinAsmParser.cpp.
...
llvm-svn: 108193
2010-07-12 20:51:51 +00:00
51e6d9bbf6
Apply the SSE dependence idiom for SSE unary operations to
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SD instructions too, in addition to SS instructions. And
add a comment about it.
llvm-svn: 108191
2010-07-12 20:46:04 +00:00
a5bf6b6001
MC/AsmParser: Move .section parsing to Darwin specific parser.
...
llvm-svn: 108190
2010-07-12 20:42:34 +00:00
aa59cf2686
MC/AsmParser: Move special section directive parsing to Darwin specific parser.
...
llvm-svn: 108187
2010-07-12 20:23:36 +00:00
8a2bdc8231
Remove some code that doesn't appear to do anything. All the ARM call
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instructions already have implicit defs of LR. The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.
llvm-svn: 108186
2010-07-12 20:22:45 +00:00
80be44a2ac
MC/AsmParser: Add a basic ELFAsmParser extension.
...
llvm-svn: 108185
2010-07-12 20:08:04 +00:00
f9bcaad76d
Add AVX 256-bit MOVMSK forms
...
llvm-svn: 108184
2010-07-12 20:06:32 +00:00
101c14c940
MC/AsmParser: Inline AsmParser::CreateSymbol into callers.
...
llvm-svn: 108183
2010-07-12 19:52:10 +00:00
d388c93f87
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
...
llvm-svn: 108180
2010-07-12 19:37:35 +00:00
63a379dd5c
MC/AsmParser: Move .desc parsing to Darwin specific parser.
...
llvm-svn: 108179
2010-07-12 19:22:53 +00:00
b992f1a95b
MC/AsmParser: Move .lsym parsing to Darwin specific parser.
...
llvm-svn: 108176
2010-07-12 19:08:25 +00:00
ae9da1481a
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
...
llvm-svn: 108174
2010-07-12 18:49:22 +00:00
425b35681f
Check begin!=end, rather than !begin.
...
llvm-svn: 108167
2010-07-12 18:12:35 +00:00
c5011088cd
MC/AsmParser: Add a DarwinAsmParser extension.
...
- Currently initialization is a bit of a hack, but harmless. We need to rework
various parts of target initialization to clean this up.
llvm-svn: 108165
2010-07-12 18:12:02 +00:00
a18c5a0e5e
Fix a typo and fit in 80 columns. Found by Bob Wilson.
...
llvm-svn: 108164
2010-07-12 18:11:17 +00:00
dd41dcf270
MC/AsmParser: Switch a bunch of directive parsing to use accessors.
...
llvm-svn: 108163
2010-07-12 18:03:11 +00:00
c128e70ff2
Add a lint check for mismatched return types, inspired by PR6944.
...
llvm-svn: 108162
2010-07-12 18:02:04 +00:00
86033407c9
MCAsmParser: Pull some directive handling out into a helper class, and change
...
DirectiveMap to be based on MCAsmParserExtension.
llvm-svn: 108161
2010-07-12 17:54:38 +00:00
cc21af1dfb
MC/AsmParser: Switch some directive parsing to use accessor methods.
...
llvm-svn: 108160
2010-07-12 17:45:27 +00:00
af3d1de891
MC: Add MCAsmParserExtension, a base class for all the target/object specific
...
classes which want to extend the basic asm parser.
llvm-svn: 108158
2010-07-12 17:27:45 +00:00
4be8f2ffad
MC: Move AsmParser::TokError to MCAsmParser().
...
llvm-svn: 108155
2010-07-12 17:18:45 +00:00
4042c33cd8
MC: Move getLoc() to MCAsmLexer().
...
llvm-svn: 108154
2010-07-12 17:10:00 +00:00
8f36402ac2
Nope, still breaks the release selfhost bots :(
...
llvm-svn: 108153
2010-07-12 16:38:48 +00:00
07b695e052
Reapply the "or" half of r108136, which seems to be less problematic.
...
llvm-svn: 108152
2010-07-12 16:15:48 +00:00
1b787df129
cache result of operator*
...
llvm-svn: 108150
2010-07-12 15:48:26 +00:00
68d7424a65
Don't fast-isel an x87 comparison opcode, as fast-isel doesn't
...
support branching on x87 comparisons yet. This fixes PR7624.
llvm-svn: 108149
2010-07-12 15:46:30 +00:00
c719e8ae9e
Revert r108141 again, sigh.
...
llvm-svn: 108148
2010-07-12 14:42:04 +00:00
96fedcb136
cache result of operator*
...
llvm-svn: 108147
2010-07-12 14:15:58 +00:00
f9c38b5a45
cache result of operator*
...
llvm-svn: 108146
2010-07-12 14:15:10 +00:00
88dd73b75e
cache result of operator*
...
llvm-svn: 108145
2010-07-12 14:14:03 +00:00
a75ed761a9
cache result of operator*
...
llvm-svn: 108144
2010-07-12 14:13:15 +00:00
15445db11b
cache results of operator*
...
llvm-svn: 108143
2010-07-12 14:12:11 +00:00
a5fa885d47
cache results of operator*
...
llvm-svn: 108142
2010-07-12 14:10:24 +00:00
f578c36035
Reapply 108136 with an ugly pasto fixed.
...
llvm-svn: 108141
2010-07-12 13:44:00 +00:00
11743249e6
Move optimization to avoid redundant matching.
...
llvm-svn: 108140
2010-07-12 13:34:22 +00:00
9675e759cf
Revert r108136 until I figure out why it broke selfhost.
...
llvm-svn: 108139
2010-07-12 12:35:49 +00:00
782f62412f
cache dereferenced iterators
...
llvm-svn: 108138
2010-07-12 12:03:02 +00:00
433b975fe2
recommit r108131 (hich has been backed out in r108135) with a fix
...
llvm-svn: 108137
2010-07-12 12:02:10 +00:00
35473faa50
instcombine: fold (x & y) | (~x & z) and (x & y) ^ (~x & z) into ((y ^ z) & x) ^ z which is one instruction shorter. (PR6773)
...
before:
%and = and i32 %y, %x
%neg = xor i32 %x, -1
%and4 = and i32 %z, %neg
%xor = xor i32 %and4, %and
after:
%xor1 = xor i32 %z, %y
%and2 = and i32 %xor1, %x
%xor = xor i32 %and2, %z
llvm-svn: 108136
2010-07-12 11:54:45 +00:00
f9610827ce
back out r108131 (of TailDuplication.cpp) for now, it causes a buildbot failure
...
llvm-svn: 108135
2010-07-12 11:32:39 +00:00
6143704ac5
cache dereferenced iterators
...
llvm-svn: 108134
2010-07-12 11:19:24 +00:00
8629f12bb8
cache dereferenced iterators
...
llvm-svn: 108133
2010-07-12 10:59:23 +00:00
d993402df3
cache dereferenced iterators
...
llvm-svn: 108132
2010-07-12 10:49:54 +00:00
2a464d7308
cache dereferenced iterators
...
llvm-svn: 108131
2010-07-12 10:36:48 +00:00
41b4a6b36a
Convert some tab stops into spaces.
...
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
57041d81df
Add parentheses around an || to correct the logic. Also silences a GCC warning
...
that was actually useful here.
Chris, please double check that this is the correct interpretation. I was
pretty sure, and ran it by Nick as well.
llvm-svn: 108129
2010-07-12 06:47:05 +00:00
d83984f623
Path::isRootDirectory is unimplemented on Unix and not used,
...
remove it, fixing PR6909.
llvm-svn: 108125
2010-07-12 04:39:07 +00:00
6635f9838e
Convert getLoadStoreRegOpcode to use a switch.
...
llvm-svn: 108123
2010-07-12 03:43:04 +00:00
871c724773
Convert the last use of getPhysicalRegisterRegClass and remove it.
...
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.
With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.
llvm-svn: 108122
2010-07-12 02:55:34 +00:00
de7201545e
A basic block that only uses RFP registers still needs the FP_REG_KILL marker.
...
This fixes PR7375.
llvm-svn: 108120
2010-07-12 02:12:47 +00:00
01c5a15dde
Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that the
...
physical register can be allocated in the class of the virtual are sufficient.
I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.
llvm-svn: 108118
2010-07-12 01:45:38 +00:00
25eea4db66
fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector
...
is involved.
llvm-svn: 108117
2010-07-12 01:19:22 +00:00
601e390a3b
make the prototypes for CreateMalloc and CreateFree more consistent. Patch
...
by Hans Vandierendonck from PR7605
llvm-svn: 108116
2010-07-12 00:57:28 +00:00
e35d70fafa
Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
...
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.
Update getLoadStoreRegOpcode to handle GR32_AD.
llvm-svn: 108115
2010-07-12 00:52:33 +00:00
bbc25ff5cc
if jump threading is able to infer interesting values on both
...
the LHS and RHS of an and/or instruction, don't multiply add
known predecessor values. This fixes the crash on testcase
from PR7498
llvm-svn: 108114
2010-07-12 00:47:34 +00:00
fd4a09fc0a
fix PR7429, a crash turning a load from a string into a float.
...
llvm-svn: 108113
2010-07-12 00:22:51 +00:00
cda39c4ee4
improve Path::makeUnique when mkstemp/mktemp are not available
...
patch by Lasse Kärkkäinen in PR7404.
llvm-svn: 108110
2010-07-12 00:09:55 +00:00
0b7ae20a35
change machinelicm to use MachineInstr::isSafeToMove. No
...
intended functionality change.
The avoidance of hoistiing implicitdef seems wrong though.
llvm-svn: 108109
2010-07-12 00:00:35 +00:00
b6df00c29a
first part of JIT support for address of labels, part of PR7264,
...
patch by Yuri!
llvm-svn: 108107
2010-07-11 23:07:28 +00:00
2c52b7997c
introduce WinCOFFObjectWriter, patch by Michael Spencer!
...
llvm-svn: 108103
2010-07-11 22:07:02 +00:00
56725be9ef
introduce WinCOFFStreamer.cpp, patch by Michael Spencer!
...
llvm-svn: 108102
2010-07-11 22:05:00 +00:00
5d373c2141
If it's safe to speculatively execute load(alloca) the it's safe to execute
...
load(gep(alloca)) where the gep is all-zeros. There's more we could do here but
this is a common case.
llvm-svn: 108101
2010-07-11 20:36:29 +00:00
31bd2de24e
fix typo
...
llvm-svn: 108100
2010-07-11 19:42:53 +00:00
0961c55161
RISC architectures get their memory operand folding for free.
...
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
llvm-svn: 108099
2010-07-11 19:19:13 +00:00
f6c7d7fb3f
Use target independent COPY instructions for the fake fextend and fround
...
operations in x87 code.
llvm-svn: 108098
2010-07-11 18:19:39 +00:00
7c1392a765
Remove redundant branch. Thanks, Anton!
...
llvm-svn: 108097
2010-07-11 17:17:35 +00:00
98ee37d878
Remove obsolete README_SSE note.
...
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.
The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.
The same applies to andps -> pand.
llvm-svn: 108096
2010-07-11 17:13:42 +00:00
c4227f1362
Remove TargetInstrInfo::copyRegToReg entirely.
...
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.
llvm-svn: 108095
2010-07-11 17:01:17 +00:00
1da1cfccb1
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
...
llvm-svn: 108094
2010-07-11 16:49:10 +00:00
d7c4963f2f
Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.
...
The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.
The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.
llvm-svn: 108093
2010-07-11 16:45:17 +00:00
74e5bf85f7
Replace copyRegToReg with copyPhysReg for SystemZ.
...
llvm-svn: 108092
2010-07-11 16:40:46 +00:00
4806848799
Avoid SSE instructions in FastIsel when it is not available.
...
llvm-svn: 108091
2010-07-11 16:22:13 +00:00
34e0d14ff4
Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
...
assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.
llvm-svn: 108088
2010-07-11 08:18:12 +00:00
928b593486
Replace copyRegToReg with copyPhysReg for XCore.
...
llvm-svn: 108087
2010-07-11 07:56:13 +00:00
976b7b61fc
Replace copyRegToReg with copyPhysReg for Sparc.
...
llvm-svn: 108086
2010-07-11 07:56:09 +00:00
1dba6814c9
Replace copyRegToReg with copyPhysReg for CellSPU.
...
llvm-svn: 108084
2010-07-11 07:31:03 +00:00
0d611979a8
Replace copyRegToReg with copyPhysReg for PowerPC.
...
llvm-svn: 108083
2010-07-11 07:31:00 +00:00
f889e280b8
Fix PIC16 comments referencing copyRegToReg.
...
llvm-svn: 108082
2010-07-11 07:30:57 +00:00
e494d0ff3e
Replace copyRegToReg with copyPhysReg for PIC16.
...
llvm-svn: 108081
2010-07-11 06:53:33 +00:00
65306369ae
Replace copyRegToReg with copyPhysReg for MSP430.
...
llvm-svn: 108080
2010-07-11 06:53:30 +00:00
37a38f4b28
Replace copyRegToReg with copyPhysReg for MBlaze.
...
llvm-svn: 108079
2010-07-11 06:53:27 +00:00
d7b33002dd
Replace copyRegToReg with copyPhysReg for ARM.
...
llvm-svn: 108078
2010-07-11 06:33:54 +00:00
52984e1aef
Replace copyRegToReg with copyPhysReg for Blackfin.
...
llvm-svn: 108077
2010-07-11 05:44:34 +00:00
e46f3eb0c4
X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
...
llvm-svn: 108076
2010-07-11 05:44:30 +00:00
8969657f0c
Use COPY in X86FastISel::X86SelectRet.
...
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).
llvm-svn: 108074
2010-07-11 05:17:02 +00:00
51642aea77
Use COPY for fast-isel bitconvert, but don't create cross-class copies.
...
This doesn't change the behavior of SelectBitcast for X86.
llvm-svn: 108073
2010-07-11 05:16:54 +00:00
a76eccf815
Fix va_arg for doubles. With this patch VAARG nodes always contain the
...
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
llvm-svn: 108072
2010-07-11 04:01:49 +00:00
7147ab9e78
Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
...
This assumes that the registers can be copied which is probably a safe
assumption.
llvm-svn: 108070
2010-07-11 03:31:05 +00:00
3bb1267431
Use COPY in FastISel everywhere it is safe and trivial.
...
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.
llvm-svn: 108069
2010-07-11 03:31:00 +00:00
7002c31480
Replace copyRegToReg with copyPhysReg for Mips.
...
llvm-svn: 108066
2010-07-11 01:08:31 +00:00
7198d32fc6
Replace copyRegToReg with copyPhysReg for Alpha.
...
llvm-svn: 108065
2010-07-11 01:08:23 +00:00
60af0681cb
Use COPY in targets
...
llvm-svn: 108063
2010-07-10 22:43:03 +00:00
0c76d6ec21
Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
...
llvm-svn: 108062
2010-07-10 22:42:59 +00:00
ad89613b65
Only collect subreg extracting copies for later coalescing.
...
This also avoids fatal copies from physregs.
llvm-svn: 108061
2010-07-10 22:42:53 +00:00
a64a323564
Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
...
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.
llvm-svn: 108060
2010-07-10 22:42:31 +00:00
82b21c086e
The accumulator tail recursion transform claims to work for any associative
...
operation, but the way it's implemented requires the operation to also be
commutative. So add a check for commutativity (and tweak the corresponding
comments). This makes no difference in practice since every associative
LLVM instruction is also commutative! Here's an example to show the need
for commutativity: the accum_recursion.ll testcase calculates the factorial
function. Before the transformation the result of a call is
((((1*1)*2)*3)...)*x
while afterwards it is
(((1*x)*(x-1))...*2)*1
which clearly requires both associativity and commutativity of * to be equal
to the original.
llvm-svn: 108056
2010-07-10 20:31:42 +00:00
e50d30d586
Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
...
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.
This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.
llvm-svn: 108050
2010-07-10 19:08:25 +00:00
de457896b6
Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.
...
Based on a patch by Rafael Espíndola.
Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.
We support:
FpSET_ST0
INLINEASM
FpSET_ST0
FpSET_ST1
INLINEASM
with and without kills on the arguments. We don't support:
FpSET_ST1
FpSET_ST0
INLINEASM
nor
FpSET_ST1
INLINEASM
Just Don't Do It!
llvm-svn: 108047
2010-07-10 17:42:34 +00:00
fbdba81550
Insert IMPLICIT_DEF instructions at the current insert position, not
...
at the end of the block.
llvm-svn: 108045
2010-07-10 13:55:45 +00:00
d162d85688
Add parentheses yet again to satisfy GCC's warnings.
...
llvm-svn: 108043
2010-07-10 12:06:22 +00:00
d7b5ce3312
Reapply bottom-up fast-isel, with several fixes for x86-32:
...
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
llvm-svn: 108039
2010-07-10 09:00:22 +00:00
be8d9b0bb8
An x86 function returns a floating point value in st(0), and we must make sure
...
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.
This will matter when CopyFromReg gets lowered to a generic COPY instruction.
llvm-svn: 108037
2010-07-10 04:04:25 +00:00
57e72370ae
Update DBG_VALUE to refer appropriate stack slot in case of a spill.
...
llvm-svn: 108023
2010-07-09 21:48:31 +00:00
5e6c2155a3
Declare YMM subregisters in the right way! Thanks Jakob
...
llvm-svn: 108022
2010-07-09 21:46:19 +00:00
2419606bfb
Add AVX 256-bit packed MOVNT variants
...
llvm-svn: 108021
2010-07-09 21:42:42 +00:00
e2614a9979
Remember the *_TC opcodes for load/store
...
llvm-svn: 108020
2010-07-09 21:27:55 +00:00
6bc772eec7
Add AVX 256-bit unpack and interleave
...
llvm-svn: 108017
2010-07-09 21:20:35 +00:00
b5c899d11b
Fix small bug in isMoveInstr -> COPY translation
...
llvm-svn: 108013
2010-07-09 20:55:49 +00:00
7a7b55eb67
Automatically fold COPY instructions into stack load/store.
...
llvm-svn: 108012
2010-07-09 20:43:13 +00:00
51702ec46b
Fix a few tests
...
llvm-svn: 108011
2010-07-09 20:43:09 +00:00
e9fdcaa68a
Remat uncoalescable COPY instrs
...
llvm-svn: 108010
2010-07-09 20:43:05 +00:00
2a5725b1a3
In the presence of variable sized objects, allocate an emergency spill slot.
...
rdar://8131327
llvm-svn: 108008
2010-07-09 20:27:06 +00:00
f831d86311
Clarify what mysterious check means.
...
llvm-svn: 108005
2010-07-09 19:44:12 +00:00
7929c448fc
Fix MachineLICM to actually visit inner loops.
...
llvm-svn: 108001
2010-07-09 18:49:45 +00:00
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
...
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
bd953d1805
Change TII::foldMemoryOperand API to require the machine instruction to be
...
inserted in a MBB, and return an already inserted MI.
This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.
The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.
llvm-svn: 107991
2010-07-09 17:29:08 +00:00
9d5ae03404
cache result of operator*
...
llvm-svn: 107990
2010-07-09 16:51:20 +00:00
8e66a42784
remove useless cast and fix typos in comment
...
llvm-svn: 107989
2010-07-09 16:42:04 +00:00
3b740e9085
cache result of operator*
...
llvm-svn: 107988
2010-07-09 16:39:02 +00:00
6586e9b203
--- Reverse-merging r107947 into '.':
...
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 107987
2010-07-09 16:37:18 +00:00
fd8e7d4a0f
cache result of operator*
...
llvm-svn: 107984
2010-07-09 16:31:08 +00:00
e7650c7c29
cache result of operator*
...
llvm-svn: 107983
2010-07-09 16:26:41 +00:00
aa389f5085
cache result of operator*
...
llvm-svn: 107982
2010-07-09 16:22:36 +00:00
04af1e4f65
cache result of operator*
...
llvm-svn: 107981
2010-07-09 16:17:52 +00:00
52617fc462
cache result of operator*
...
llvm-svn: 107980
2010-07-09 16:08:33 +00:00
2c0ab48ac2
cache result of operator*
...
llvm-svn: 107979
2010-07-09 16:01:21 +00:00
070b9a2cc4
cache result of operator*
...
llvm-svn: 107978
2010-07-09 15:53:42 +00:00
d9a0e80213
cache result of operator*
...
llvm-svn: 107977
2010-07-09 15:52:36 +00:00
e82532a1c5
cache result of operator*
...
llvm-svn: 107976
2010-07-09 15:40:10 +00:00
6d8870fc35
cache result of operator*
...
llvm-svn: 107975
2010-07-09 15:25:42 +00:00
329c4d8ed9
cache result of operator*
...
llvm-svn: 107974
2010-07-09 15:25:09 +00:00
0028cc6730
cache result of operator*
...
llvm-svn: 107972
2010-07-09 15:01:36 +00:00
d323f5e161
cache result of operator* (found by inspection)
...
llvm-svn: 107971
2010-07-09 14:48:08 +00:00
b0d56ffc85
cache result of operator*
...
llvm-svn: 107969
2010-07-09 14:36:49 +00:00
4247949ce9
cache result of operator*
...
llvm-svn: 107968
2010-07-09 14:29:14 +00:00
2732561be9
cache result of operator*
...
llvm-svn: 107967
2010-07-09 14:28:41 +00:00
a02f232c1b
cache result of operator*
...
llvm-svn: 107966
2010-07-09 14:18:23 +00:00
f0821f39ee
cache operator*'s result (in multiple functions)
...
llvm-svn: 107965
2010-07-09 14:02:13 +00:00
1d20021d82
do not repeatedly dereference use_iterator
...
llvm-svn: 107963
2010-07-09 13:17:13 +00:00
60a346d0f1
do not repeatedly dereference use_iterator
...
llvm-svn: 107962
2010-07-09 12:23:50 +00:00
d4d9e53b20
Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.
...
This fixes PR7602.
llvm-svn: 107957
2010-07-09 05:56:21 +00:00
cac54d6435
Deal with a few remaining spots that assume physical registers have live intervals.
...
This fixes PR7601.
llvm-svn: 107955
2010-07-09 04:35:38 +00:00
992d25da71
Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
...
fields to use.
llvm-svn: 107952
2010-07-09 01:56:45 +00:00
66b3649030
Fix broken isCopy handling in TrimLiveIntervalToLastUse.
...
llvm-svn: 107950
2010-07-09 01:27:21 +00:00
5165fa1c39
Handle COPY in VirtRegRewriter.
...
llvm-svn: 107949
2010-07-09 01:27:19 +00:00
0a7d155d67
Fix the memoperand offsets in code generated for va_start.
...
llvm-svn: 107948
2010-07-09 01:06:48 +00:00
88c185617c
have the mc lowering process handle a few tail call forms, lowering them to
...
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
llvm-svn: 107946
2010-07-09 00:49:41 +00:00
88a4e6dc0e
Print "dregpair" NEON operands with a space between them, for readability and
...
consistency with other instructions that have lists of register operands.
llvm-svn: 107944
2010-07-09 00:47:20 +00:00
0b5aa1cdd3
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
...
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
llvm-svn: 107943
2010-07-09 00:39:23 +00:00
e6cc0d33bb
Factor out x86 segment override prefix encoding, and also use it for VEX
...
llvm-svn: 107942
2010-07-09 00:38:14 +00:00
21eed476e8
Reenable DAG combining for vector shuffles. It looks like it was temporarily
...
disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
llvm-svn: 107941
2010-07-09 00:38:12 +00:00
061d70ad2c
reject pseudo instructions early in the encoder.
...
llvm-svn: 107939
2010-07-09 00:17:50 +00:00
b652c1a145
Remove trailing whitespaces from file
...
llvm-svn: 107937
2010-07-09 00:07:19 +00:00
f469307c77
Change LEA to have 5 operands for its memory operand, just
...
like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
llvm-svn: 107934
2010-07-08 23:46:44 +00:00
d08fb75aaa
Reverting r107918 and r107919. Radar 8063111.
...
llvm-svn: 107930
2010-07-08 23:25:39 +00:00
823e90e12a
Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse"
...
This reverts commit 107921. It broke the clang self host.
llvm-svn: 107926
2010-07-08 22:52:47 +00:00
ec536276f0
add some long-overdue enums to refer to the parts of the 5-operand
...
X86 memory operand.
llvm-svn: 107925
2010-07-08 22:41:28 +00:00
4c6bd6612f
Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function.
...
This fixes PR7596 .
llvm-svn: 107923
2010-07-08 22:39:20 +00:00
a992445ff2
Extension of r107506. Make sure that we don't mark a function as having a call
...
if the inline ASM doesn't need a stack frame.
llvm-svn: 107922
2010-07-08 22:38:02 +00:00
75c465585a
Fix broken isCopy handling in TrimLiveIntervalToLastUse
...
llvm-svn: 107921
2010-07-08 22:30:38 +00:00
ec58a43d81
Remember the VR64 register class
...
llvm-svn: 107920
2010-07-08 22:30:35 +00:00
43d226deea
Fix decl/def debug info for template functions. Radar 8063111.
...
llvm-svn: 107919
2010-07-08 22:28:59 +00:00
9f034c1e5d
Rework segment prefix emission code to handle segments
...
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
1dd82c7dc2
introduce a new X86II::getMemoryOperandNo method, which
...
returns the start of the memory operand for an instruction.
Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.
llvm-svn: 107916
2010-07-08 22:27:06 +00:00
d799ea52cd
Switch SPU calling convention (function arguments)
...
to a Tablegen implementation.
llvm-svn: 107913
2010-07-08 21:15:22 +00:00
ea9207cd7a
Revert some unneeded parts of the change in r107886 for the
...
.weak_def_can_be_hidden directive. Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these. And
when that happens it will be more convenient for it to be a bool than a const
char*.
llvm-svn: 107906
2010-07-08 20:30:44 +00:00
0f54854a1d
Check for FiniteOnlyFPMath as well.
...
llvm-svn: 107904
2010-07-08 20:12:24 +00:00
9c160e1213
Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.
...
llvm-svn: 107903
2010-07-08 20:10:35 +00:00
63a622b768
Teach the x86 floating point stackifier to handle COPY instructions.
...
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.
Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.
llvm-svn: 107899
2010-07-08 19:46:30 +00:00
930f8082c3
Implement X86InstrInfo::copyPhysReg
...
llvm-svn: 107898
2010-07-08 19:46:25 +00:00
181e5af248
The NEONPreAllocPass should never have to assign fixed registers anymore.
...
This pass can go away entirely soon.
llvm-svn: 107892
2010-07-08 17:45:26 +00:00
1eade1a327
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
...
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
llvm-svn: 107890
2010-07-08 17:44:00 +00:00
082d0fd7ad
Added the darwin .weak_def_can_be_hidden directive.
...
llvm-svn: 107886
2010-07-08 17:22:42 +00:00
6c25043493
Clean up a comment.
...
llvm-svn: 107882
2010-07-08 16:54:45 +00:00
c280fc7514
Clean up scavengeRegister() a bit to prefer available regs, which allows
...
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.
llvm-svn: 107880
2010-07-08 16:49:26 +00:00
00264624a9
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
...
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
llvm-svn: 107879
2010-07-08 16:40:22 +00:00
a1e883dcf6
Remove references to INSERT_SUBREG after de-SSA.
...
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.
llvm-svn: 107878
2010-07-08 16:40:15 +00:00
0ae3f08c0d
Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
...
llvm-svn: 107868
2010-07-08 12:09:56 +00:00
2321e6a4d4
Teach instcombine to transform
...
(X >s -1) ? C1 : C2 and (X <s 0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.
This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.
for
int sel(int n) {
return n >= 0 ? 60 : 100;
}
we now generate
sarl $31, %edi
andl $40, %edi
leal 60(%rdi), %eax
instead of
testl %edi, %edi
movl $60, %ecx
movl $100, %eax
cmovnsl %ecx, %eax
llvm-svn: 107866
2010-07-08 11:39:10 +00:00
e796253217
A slight reworking of the custom patterns for x86-64 tpoff codegen and
...
correct the testcase for valid assembly.
Needs more tests.
llvm-svn: 107860
2010-07-08 07:36:46 +00:00
be1f7a931e
r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
...
llvm-svn: 107856
2010-07-08 06:01:49 +00:00
89a4e25007
Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.
...
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.
Any remaining calls to copyRegToReg wil be replaced by COPY instructions.
llvm-svn: 107854
2010-07-08 05:01:41 +00:00
25f9364cbd
Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
...
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.
e.g.
vldr.32 s0, [r1]
vldr.32 s1, [r0]
vcmpe.f32 s1, s0
vmrs apsr_nzcv, fpscr
beq LBB0_2
=>
ldr r1, [r1]
ldr r0, [r0]
cmp r0, r1
beq LBB0_2
More complicated cases will be implemented in subsequent patches.
llvm-svn: 107852
2010-07-08 02:08:50 +00:00
e2289285ae
Changes to ARM tail calls, mostly cosmetic.
...
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.
llvm-svn: 107851
2010-07-08 01:18:23 +00:00
e75704369d
Revert 107840 107839 107813 107804 107800 107797 107791.
...
Debug info intrinsics win for now.
llvm-svn: 107850
2010-07-08 01:00:56 +00:00
6533f24370
When processing frame index virtual registers, consider all available registers
...
(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760
llvm-svn: 107847
2010-07-08 00:38:54 +00:00
efa3c824cc
Fix the second half of PR7437: scalarrepl wasn't preserving
...
address spaces when SRoA'ing memcpy's.
llvm-svn: 107846
2010-07-08 00:27:05 +00:00
eb9164dc50
Don't forward-declare registers for static allocas, which we'll
...
prefer to materialize as local constants. This fixes the clang
bootstrap abort.
llvm-svn: 107840
2010-07-07 23:52:58 +00:00
1adc499dda
Fix -fast-isel-abort to check the right instruction.
...
llvm-svn: 107839
2010-07-07 23:47:25 +00:00
9380b81837
use PrintEscapedString to handle attribute section with escapes in it,
...
PR7399. The asm parser already handles this. This is of dubious
utility (see the PR) but the asmprinter was clearly broken here.
llvm-svn: 107834
2010-07-07 23:16:37 +00:00
6213ab789f
fix copies to/from GR8_ABCD_H even more
...
llvm-svn: 107832
2010-07-07 23:04:56 +00:00
73ef80f76f
grammar
...
llvm-svn: 107831
2010-07-07 22:53:35 +00:00
40eda1076a
Handle cases where the post-RA scheduler may move instructions between the
...
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682
llvm-svn: 107830
2010-07-07 22:51:22 +00:00
05ea2a4791
finish up support for callw: PR7195
...
llvm-svn: 107826
2010-07-07 22:35:13 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
6c61451011
Add more assembly opcodes for SSE compare instructions
...
llvm-svn: 107823
2010-07-07 22:24:03 +00:00
a37a95ea2f
One MDNode may be used to create regular DIE as well as abstract DIE.
...
Keep track of abstract subprogram DIEs.
llvm-svn: 107822
2010-07-07 22:20:57 +00:00
1c349f18f8
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
...
llvm-svn: 107820
2010-07-07 22:15:37 +00:00
32a600b494
Print undefined/unknown debug value as "undef".
...
llvm-svn: 107818
2010-07-07 21:52:21 +00:00
25d5c1b4f8
Not all custom inserters create new basic blocks. If the inserter
...
didn't create a new block, don't reset the insert position.
llvm-svn: 107813
2010-07-07 21:18:22 +00:00
e4ba2aa0c4
grammar and trailing whitespace
...
llvm-svn: 107811
2010-07-07 21:06:51 +00:00
9a0339fc1f
Rename couple of maps.
...
llvm-svn: 107810
2010-07-07 20:49:57 +00:00
ddaf0099a5
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
...
This fixes PR7540.
llvm-svn: 107809
2010-07-07 20:33:27 +00:00
30265c4f8b
80 cols.
...
llvm-svn: 107807
2010-07-07 20:12:52 +00:00
e7ccc51cc1
Implement bottom-up fast-isel. This has the advantage of not requiring
...
a separate DCE pass over MachineInstrs.
llvm-svn: 107804
2010-07-07 19:20:32 +00:00
2d4d01d0de
Add X86FastISel support for return statements. This entails refactoring
...
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
2010-07-07 18:32:53 +00:00
fd8060335b
Add AVX AES instructions
...
llvm-svn: 107798
2010-07-07 18:24:20 +00:00
b792f844ad
Update the insert position after scheduling, which may change the
...
position when emitting multiple blocks when executing a custom
inserter.
llvm-svn: 107797
2010-07-07 18:22:13 +00:00
637ee5f149
Update comment.
...
llvm-svn: 107796
2010-07-07 18:18:18 +00:00
769201448d
Fix debugging strings.
...
llvm-svn: 107795
2010-07-07 17:28:45 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
e784616fbb
Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will
...
allow target-specific fast-isel code to make use of it directly.
llvm-svn: 107787
2010-07-07 16:01:37 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
ca97c92eb4
add some triple for minix, patch by Kees van Reeuwijk from PR7582
...
llvm-svn: 107785
2010-07-07 15:52:27 +00:00
498e5f899d
Move CallingConvLower.cpp out of the SelectionDAG directory.
...
llvm-svn: 107781
2010-07-07 15:15:27 +00:00
8e1338eea8
Fix more places assuming subregisters have live intervals
...
llvm-svn: 107780
2010-07-07 14:41:22 +00:00
88c547ede9
Add a getFirstNonPHI utility function.
...
llvm-svn: 107778
2010-07-07 14:33:51 +00:00
5b0a8a863f
Minore code simplification.
...
llvm-svn: 107777
2010-07-07 14:30:04 +00:00
00ef93258a
Remove interprocedural-basic-aa and associated code. The AliasAnalysis
...
interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.
Document that AliasAnalysis doesn't support cross-function queries.
llvm-svn: 107776
2010-07-07 14:27:09 +00:00
a22e8148d4
conditionalize by CallInst::ArgOffset
...
llvm-svn: 107767
2010-07-07 10:34:03 +00:00
408bb192de
Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
...
builds to "Release". The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts. The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown). This will bring them
in line with MacOS releases, which ship with assertions disabled. It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.
llvm-svn: 107758
2010-07-07 07:48:00 +00:00
6d122aef97
Add AVX SSE4.2 instructions
...
llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
...
llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
...
llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f0e551d4f4
Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
...
Buildbot breakage.
llvm-svn: 107744
2010-07-07 00:32:25 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
...
they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
e2d3067f6b
Remove references to INSERT_SUBREG after de-SSA
...
llvm-svn: 107732
2010-07-06 23:40:35 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
70ee3ecd33
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
...
INSERT_SUBREG will now only appear in SSA machine instructions.
Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.
llvm-svn: 107726
2010-07-06 23:26:25 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
...
This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
...
llvm-svn: 107701
2010-07-06 21:26:18 +00:00
15fed3bd30
One more case assuming that subregs have live ranges.
...
llvm-svn: 107700
2010-07-06 21:13:03 +00:00
bcf3409107
Fix buildbot breakage where a def is missing.
...
llvm-svn: 107698
2010-07-06 21:06:39 +00:00
b36df17b08
Add fixme.
...
llvm-svn: 107697
2010-07-06 21:05:17 +00:00
a64c0a3d22
Be more forgiving when calculating alias interference for physreg coalescing.
...
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.
This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.
llvm-svn: 107695
2010-07-06 20:31:51 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
dfc8b745a2
Fix to 80-col.
...
llvm-svn: 107684
2010-07-06 18:35:20 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
dde2ba0b60
tighten up this code.
...
llvm-svn: 107670
2010-07-06 15:59:27 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
4e49b59dad
Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
...
which do not depend on SelectionDAG.
llvm-svn: 107666
2010-07-06 15:39:54 +00:00
2b2a1c3c86
Make getMinimalPhysRegClass' comment mention what makes it different
...
from getPhysicalRegisterRegClass.
llvm-svn: 107660
2010-07-06 15:31:55 +00:00
e415230477
Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
...
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').
llvm-svn: 107658
2010-07-06 15:24:56 +00:00
1e33b18e28
Add some more TODO comments.
...
llvm-svn: 107657
2010-07-06 15:23:00 +00:00
f855b39edd
Add a comment.
...
llvm-svn: 107656
2010-07-06 15:21:57 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
dace239949
Detabify this file.
...
llvm-svn: 107637
2010-07-06 03:53:43 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
d5ac287140
Remove some unused/redundant code.
...
llvm-svn: 107622
2010-07-05 18:40:09 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
2c0315a0f3
random tidying
...
llvm-svn: 107612
2010-07-05 05:36:21 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
ac0a210789
Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
...
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
f3aeb2c22c
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
...
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
f844642350
Proper indentation.
...
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
c8f595212f
Minor amendment to switch-lowering improvement.
...
llvm-svn: 107569
2010-07-03 08:43:32 +00:00
836fdbc85b
Note switch-lowering inefficiency.
...
llvm-svn: 107565
2010-07-03 07:38:12 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
128a0197bb
Fix typo.
...
llvm-svn: 107556
2010-07-03 01:09:18 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
...
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
621c85b038
Add AVX SSE4.1 round instructions
...
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
4c82a9e7d0
Detect and handle COPY in many places.
...
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.
llvm-svn: 107547
2010-07-03 00:04:37 +00:00
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
...
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
5e5416056b
80-col fixup.
...
llvm-svn: 107537
2010-07-02 23:17:38 +00:00
676a15bdf5
Add a new target independent COPY instruction and code to lower it.
...
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
llvm-svn: 107529
2010-07-02 22:29:50 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
...
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
3c43248560
Custom inserters (e.g., conditional moves in Thumb1 can introduce
...
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.
rdar://8022442
llvm-svn: 107517
2010-07-02 21:23:37 +00:00
cefe3831b7
MDString is already checked earlier.
...
llvm-svn: 107516
2010-07-02 21:13:23 +00:00
c3525dc0fd
Remove early IT block formation. It's not used.
...
llvm-svn: 107513
2010-07-02 21:07:09 +00:00
0ce84486c3
- Two-address pass should not assume unfolding is always successful.
...
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
llvm-svn: 107509
2010-07-02 20:36:18 +00:00
4d887f7ca7
Propagate the AlignStack bit in InlineAsm's to the
...
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
llvm-svn: 107506
2010-07-02 20:16:09 +00:00
df8429aeb4
Remove invalid assert
...
llvm-svn: 107505
2010-07-02 19:54:47 +00:00
cf6c5c960f
Properly handle debug values during inline spilling.
...
llvm-svn: 107503
2010-07-02 19:54:40 +00:00
9da02a83e9
beautify output
...
llvm-svn: 107500
2010-07-02 19:26:28 +00:00
e537ddbdb4
use ArgOperand API
...
llvm-svn: 107498
2010-07-02 19:08:46 +00:00
832282e061
Don't claim to preserve AliasAnalysis. First, this is doesn't actually
...
have any effect, and second, deleting stores can potentially invalidate
an AliasAnalysis, and there's currently no notification for this.
llvm-svn: 107496
2010-07-02 18:43:05 +00:00
96037187e5
Rematerialize as much as possible before inserting spills and reloads.
...
This allows us to recognize the common case where all uses could be
rematerialized, and no stack slot allocation is necessary.
If some values could be fully rematerialized, remove them from the live range
before allocating a stack slot for the rest.
llvm-svn: 107492
2010-07-02 17:44:57 +00:00
9b7755fbc6
80-column and trailing whitespace cleanup.
...
llvm-svn: 107490
2010-07-02 17:41:59 +00:00
64a4f3f062
grammar tweaks
...
llvm-svn: 107489
2010-07-02 17:38:34 +00:00
771d04b969
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
...
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
llvm-svn: 107487
2010-07-02 17:23:44 +00:00
56de4675b6
use ArgOperand API (found by my previous commit)
...
llvm-svn: 107482
2010-07-02 13:37:16 +00:00
ee8d80d6a3
IndirectBr is not safe to speculatively execute (!)
...
llvm-svn: 107454
2010-07-02 00:35:34 +00:00
93f5920914
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
...
llvm-svn: 107451
2010-07-02 00:10:16 +00:00
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
...
llvm-svn: 107448
2010-07-01 23:10:49 +00:00
504055ce9e
Make the "linker_private" linkage type emit a non-weak symbol to the file. It
...
will still be stripped by the linker when it generates the final image.
llvm-svn: 107440
2010-07-01 22:38:24 +00:00
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
...
llvm-svn: 107438
2010-07-01 22:33:18 +00:00
8a99b730a9
ARM function alignments were off by a power of two. svn 83242 changed
...
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
llvm-svn: 107435
2010-07-01 22:26:26 +00:00
03bcd6ecc8
Implement the "linker_private_weak" linkage type. This will be used for
...
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.
For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
Currently only supported on Darwin platforms.
llvm-svn: 107433
2010-07-01 21:55:59 +00:00
429397529a
Do not require line number entry for undefined local variable.
...
This is a regression caused by r106792 and caught by gdb testsuite.
llvm-svn: 107430
2010-07-01 21:38:08 +00:00
0e980755d3
MC: Fix some stray hunks I didn't intend to commit.
...
llvm-svn: 107428
2010-07-01 20:48:51 +00:00
02877d6e85
MC: Pass the target instance to the AsmParser constructor.
...
llvm-svn: 107426
2010-07-01 20:41:56 +00:00
0aa4365e47
MC: Fix an error message.
...
llvm-svn: 107424
2010-07-01 20:20:01 +00:00
84f90a387d
Remove context sensitivity concerns from interprocedural-basic-aa, and
...
make it more aggressive in cases where both pointers are known to live
in the same function.
llvm-svn: 107420
2010-07-01 20:08:40 +00:00
329d202362
MC: Move COFF enumeration constants to llvm/Support/COFF.h, patch by Michael
...
Spencer!
llvm-svn: 107418
2010-07-01 20:07:24 +00:00
2b434e12cd
Debugging infomration is encoded in llvm IR using metadata. This is designed
...
such a way that debug info for symbols preserved even if symbols are
optimized away by the optimizer.
Add new special pass to remove debug info for such symbols.
llvm-svn: 107416
2010-07-01 19:49:20 +00:00
b9e2e4b762
If a named mdnode is removed then mark module as changed.
...
llvm-svn: 107412
2010-07-01 18:27:46 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
d2965c10a1
Temporarily disable on-demand fast-isel.
...
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
9dc154bcb4
reformulate CallSite::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private
...
llvm-svn: 107390
2010-07-01 10:41:37 +00:00
42b7ee15f5
Use FuncInfo's isExportedInst accessor method instead of
...
doing the work manually.
llvm-svn: 107384
2010-07-01 03:57:05 +00:00
85e02e9340
Rename CreateRegForValue to CreateReg, and change its argument
...
from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
2010-07-01 03:55:39 +00:00
4d29fd85f9
Fast isel no longer needs DeadMachineInstrElim to clean up after it.
...
llvm-svn: 107381
2010-07-01 03:49:59 +00:00
aef3d140b7
Teach fast-isel to avoid loading a value from memory when it's already
...
available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
llvm-svn: 107380
2010-07-01 03:49:38 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
...
llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
d432223163
Reapply r106422, splitting the code for materializing a value out of
...
SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
2010-07-01 01:59:43 +00:00
9576645a84
Don't use operator[] here, because it's not desirable to insert a default
...
value if the search fails.
llvm-svn: 107368
2010-07-01 01:33:21 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
22fa66cf2b
80-col violation.
...
llvm-svn: 107361
2010-07-01 01:00:27 +00:00
4721ad855e
Trailing whitespace.
...
llvm-svn: 107360
2010-07-01 01:00:22 +00:00
8656a4549a
Add memory operand folding support to InlineSpiller.
...
llvm-svn: 107355
2010-07-01 00:13:04 +00:00
bde96ad23e
Add support for rematerialization to InlineSpiller.
...
llvm-svn: 107351
2010-06-30 23:03:52 +00:00
e0dfb98ea0
Use the catch-all selectors we already found when converting them to use the
...
correct catch-all value. This saves having to iterate through all of the
selectors in the program again.
llvm-svn: 107345
2010-06-30 22:49:53 +00:00
e74c78d539
lowerinvoke needs to handle aggregate function args like sjlj eh does.
...
llvm-svn: 107335
2010-06-30 22:22:59 +00:00
e8c97a7cd7
Handle array and vector typed parameters in sjljehprepare like we do
...
structs. rdar://8145832
llvm-svn: 107332
2010-06-30 22:20:38 +00:00
db735cbbab
Remove all debug info related named mdnodes.
...
llvm-svn: 107323
2010-06-30 21:29:00 +00:00
caf9b3ab7d
grammar tweak in comment.
...
llvm-svn: 107321
2010-06-30 21:27:56 +00:00
f638f4ff84
In ScalarEvolution::forgetValue, eliminate any SCEVUnknown
...
entries associated with the value being erased in the
folding set map. These entries used to be harmless, because
a SCEVUnknown doesn't store any information about its Value*,
so having a new Value allocated at the old Value's address
wasn't a problem. But now that ScalarEvolution is storing more
information about values, this is no longer safe.
llvm-svn: 107316
2010-06-30 20:21:12 +00:00
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
...
llvm-svn: 107308
2010-06-30 18:49:10 +00:00
59e1cae377
Some fool committed without testing (or even building) first.
...
llvm-svn: 107307
2010-06-30 18:41:20 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
...
llvm-svn: 107306
2010-06-30 18:38:10 +00:00
c39d3497c8
Remember to track spill slot uses in VirtRegMap when inserting loads and stores.
...
LocalRewriter::runOnMachineFunction uses this information to mark dead spill
slots.
This means that InlineSpiller now also works for functions that spill.
llvm-svn: 107302
2010-06-30 18:19:08 +00:00
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
...
llvm-svn: 107300
2010-06-30 18:06:01 +00:00
c0cca7fdda
Revert the part of r107257 which introduced new logic for using
...
nsw and nuw flags from IR Instructions. On further consideration,
this isn't valid.
llvm-svn: 107298
2010-06-30 17:27:11 +00:00
945a347478
Remove an unused variable. The call to getRoot has side-effects, so
...
this could break something (but doesn't seem to).
llvm-svn: 107295
2010-06-30 17:22:28 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
...
llvm-svn: 107293
2010-06-30 17:03:03 +00:00
7b90966d4a
Rather than giving SmallPtrSetImpl a member field SmallArray which is magically
...
replaced by a bigger array in SmallPtrSet (by overridding it), instead just use a
pointer to the start of the storage, and have SmallPtrSet pass in the value to use.
This has the disadvantage that SmallPtrSet becomes bigger by one pointer. It has
the advantage that it no longer uses tricky C++ rules, and is clearly correct while
I'm not sure the previous version was. This was inspired by g++-4.6 pointing out
that SmallPtrSetImpl was writing off the end of SmallArray, which it was. Since
SmallArray is replaced with a bigger array in SmallPtrSet, the write was still to
valid memory. But it was writing off the end of the declared array type - sounds
kind of dubious to me, like it sounded dubious to g++-4.6. Maybe g++-4.6 is wrong
and this construct is perfectly valid and correctly compiled by all compilers, but
I think it is better to avoid the whole can of worms by avoiding this construct.
llvm-svn: 107285
2010-06-30 15:02:37 +00:00
647d9c9797
use ArgOperand API
...
llvm-svn: 107282
2010-06-30 13:45:50 +00:00
12ca3d9fac
use ArgOperand API
...
llvm-svn: 107280
2010-06-30 13:03:37 +00:00
f69acfe133
use ArgOperand API
...
llvm-svn: 107279
2010-06-30 12:55:46 +00:00
74470192d7
use ArgOperand API
...
llvm-svn: 107278
2010-06-30 12:42:43 +00:00
d50572802e
use ArgOperand API
...
llvm-svn: 107277
2010-06-30 12:40:35 +00:00
3390e746fa
use CallSite::arg_end instead of CallInst::op_end
...
llvm-svn: 107276
2010-06-30 12:39:23 +00:00
3abd881bea
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107275
2010-06-30 12:38:26 +00:00
743b3fd196
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107273
2010-06-30 09:19:23 +00:00
f628ecd15f
use getNumArgOperands instead of getNumOperands
...
llvm-svn: 107272
2010-06-30 09:17:53 +00:00
fe252e6fa0
use getArgOperand instead of getOperand
...
llvm-svn: 107271
2010-06-30 09:16:16 +00:00
8ae3095286
use getArgOperand instead of getOperand
...
llvm-svn: 107270
2010-06-30 09:15:28 +00:00
e9acc46f65
use getArgOperand instead of getOperand
...
llvm-svn: 107269
2010-06-30 09:14:26 +00:00
16206132b6
Improve ScalarEvolution's nsw and nuw preservation.
...
llvm-svn: 107257
2010-06-30 07:16:37 +00:00
9396b42ca4
When computing a new ConservativeResult, intersect it with
...
the old one instead of replacing it, to be more precise.
llvm-svn: 107256
2010-06-30 06:58:35 +00:00
0865966440
Rework scev-aa's basic computation so that it doesn't depend
...
on ScalarEvolution successfully folding and preserving
range information for both A-B and B-A. Now, if it gets
either one, it's sufficient.
llvm-svn: 107249
2010-06-30 06:12:16 +00:00
37f145c55b
Simplify.
...
llvm-svn: 107248
2010-06-30 06:09:46 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
...
llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
...
llvm-svn: 107245
2010-06-30 03:47:56 +00:00
5364655e02
Remove trailing whitespace, no functionality changes.
...
llvm-svn: 107244
2010-06-30 03:40:54 +00:00
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
...
llvm-svn: 107243
2010-06-30 03:29:36 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
...
llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
...
llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
c5b3109bec
Do not construct DIE for already processed MDNode.
...
llvm-svn: 107237
2010-06-30 01:40:11 +00:00
b3b89c3bc0
Use skipInstruction() as a simpler way of iterating over instructions using SrcReg
...
llvm-svn: 107234
2010-06-30 00:30:36 +00:00
08baf59da1
Use clEnumValN macro to work around keyword clash
...
llvm-svn: 107233
2010-06-30 00:24:51 +00:00
648df7bf64
Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree.
...
llvm-svn: 107228
2010-06-30 00:11:08 +00:00
f888911932
Begin implementation of an inline spiller.
...
InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.
This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.
llvm-svn: 107227
2010-06-29 23:58:39 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
...
llvm-svn: 107225
2010-06-29 23:47:49 +00:00
ae36b1ed42
Fix ScalarEvolution's tripcount computation for chains of loops
...
where each loop's induction variable's start value is the exit
value of a preceding loop.
llvm-svn: 107224
2010-06-29 23:43:06 +00:00
3632171750
Revert r107205 and r107207.
...
llvm-svn: 107215
2010-06-29 22:34:52 +00:00
be30551600
Print InlinedAt location.
...
llvm-svn: 107214
2010-06-29 22:29:15 +00:00
e34471bb31
Add another bswap idiom that isn't matched.
...
llvm-svn: 107213
2010-06-29 22:22:22 +00:00
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
...
llvm-svn: 107211
2010-06-29 22:12:16 +00:00
c728518bfe
Print InlinedAt location.
...
llvm-svn: 107208
2010-06-29 21:51:32 +00:00
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
...
llvm-svn: 107206
2010-06-29 21:25:12 +00:00
1767723dbe
Introducing the "linker_weak" linkage type. This will be used for Objective-C
...
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
llvm-svn: 107205
2010-06-29 21:24:00 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
...
Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
24bc1b5b2f
Do not hardcode DW_AT_stmt_list value.
...
Inspired by Artur Pietrek.
llvm-svn: 107202
2010-06-29 20:17:53 +00:00
be157b0ea8
Add support for encoding VDUP (ARM core register) instructions.
...
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
dadea5b178
Fix the handling of partial redefines in the fast register allocator.
...
A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.
This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.
llvm-svn: 107193
2010-06-29 19:15:30 +00:00
d91d5bfc95
Fix a register scavenger crash when dealing with undefined subregs.
...
The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.
llvm-svn: 107189
2010-06-29 18:42:49 +00:00
a4575f5b31
Add AVX non-temporal stores
...
llvm-svn: 107178
2010-06-29 18:22:01 +00:00
1be9e7c0b6
Fix whitespace style.
...
llvm-svn: 107175
2010-06-29 18:12:34 +00:00
049f4ffab1
Move non-temporal movs to their own section
...
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
ab0819e10d
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
llvm-svn: 107167
2010-06-29 17:34:07 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
...
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
5bee07ec68
skip dbg_value instructions
...
llvm-svn: 107154
2010-06-29 16:55:24 +00:00
83b993a977
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
...
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
llvm-svn: 107147
2010-06-29 16:25:11 +00:00
eab748d409
use ArgOperand API
...
llvm-svn: 107145
2010-06-29 16:17:26 +00:00
17f1ca8793
Return Changed. This required setting Changed if dbg metadata
...
is stripped off. Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.
llvm-svn: 107142
2010-06-29 14:52:10 +00:00
83d1dd637a
It seems clear that this should return Changed.
...
llvm-svn: 107141
2010-06-29 14:49:35 +00:00
38a7d7cbc3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
...
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
llvm-svn: 107140
2010-06-29 14:02:34 +00:00
d34bb4e9b0
getMachineBasicBlockAddress returns a uintptr_t - don't truncate
...
to unsigned only to extend back to a pointer sized value on the
next line.
llvm-svn: 107139
2010-06-29 13:34:20 +00:00
a85a90773c
The variable ValueSize is set to 1 on both code paths, and then
...
ignored! Remove it.
llvm-svn: 107138
2010-06-29 13:30:08 +00:00
1245e4c07d
The variable "Value" is carefully set to Layout.getSymbolAddress,
...
but then not actually used - maybe a bug? Remove the variable.
llvm-svn: 107137
2010-06-29 13:26:33 +00:00
5667a08468
Remove unused calls to Lexer.getLoc and the pointless variable HasFillExpr.
...
llvm-svn: 107136
2010-06-29 13:24:40 +00:00
193bb1ee6a
Remove pointless variable LastDef.
...
llvm-svn: 107135
2010-06-29 13:23:22 +00:00
257eba4df7
Remove unused variable Loc and pointless variables unified_syntax
...
and thumb_mode.
llvm-svn: 107133
2010-06-29 13:04:35 +00:00
e73d64c2cf
use ArgOperand APIs
...
llvm-svn: 107132
2010-06-29 13:03:46 +00:00
78ad27ca2b
Remove an unused and a pointless variable.
...
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
67bfa9d109
Remove pointless and unused variables.
...
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
eec74583ca
encode operand initializations (at fixed index)
...
in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.
llvm-svn: 107129
2010-06-29 11:41:38 +00:00
67aa21d7b5
Remove a pointless variable.
...
llvm-svn: 107128
2010-06-29 11:39:45 +00:00
6d28e73acc
Remove initialized but otherwise unused variables.
...
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
80b7bc042a
Use a more obvious way to avoid compiling functions which are only used when XDEBUG is enabled.
...
llvm-svn: 107125
2010-06-29 10:03:11 +00:00
b1adb88d05
Jump through some silly hoops to make GCC accept that a function may not always
...
be called.
llvm-svn: 107124
2010-06-29 06:46:00 +00:00
b59dd8f10a
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
...
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
0c30739cbb
Change if-cvt options to something that actually as useable.
...
llvm-svn: 107121
2010-06-29 05:37:59 +00:00
907673c48d
When processing loops for scheduling latencies (used for live outs on loop
...
back-edges), make sure not to include dbg_value instructions in the count.
Closing in on the end of rdar://7797940
llvm-svn: 107119
2010-06-29 04:48:13 +00:00
90db61d638
Just as its not safe to blindly transfer the nsw bit from an add
...
instruction to an add scev, it's not safe to blindly transfer the
inbounds flag from a gep instruction to an nsw on the scev for the
gep.
llvm-svn: 107117
2010-06-29 01:41:41 +00:00
de736a6494
Refactoring of arithmetic instruction classes with unary operator
...
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
c1eccbc468
When no memoperands are present, assume unaligned, volatile.
...
llvm-svn: 107114
2010-06-29 01:13:07 +00:00
1e5da550e5
Reapply my if-conversion cleanup from svn r106939 with fixes.
...
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 00:55:23 +00:00
0824affeff
Add an Intraprocedural form of BasicAliasAnalysis, which aims to
...
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.
llvm-svn: 107109
2010-06-29 00:50:39 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
...
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
3d12ff797b
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
llvm-svn: 107107
2010-06-29 00:26:13 +00:00
269a89fd3a
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
...
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
llvm-svn: 107097
2010-06-28 23:40:25 +00:00
4469a892b4
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
llvm-svn: 107086
2010-06-28 22:23:17 +00:00
1de21ec498
Use DW_FORM_addr for DW_AT_entry_pc.
...
llvm-svn: 107085
2010-06-28 22:22:47 +00:00
17feb07c53
In asm's, output operands with matching input constraints
...
have to be registers, per gcc documentation. This affects
the logic for determining what "g" should lower to. PR 7393.
A couple of existing testcases are affected.
llvm-svn: 107079
2010-06-28 22:09:45 +00:00
e233dda2e2
Added the darwin .secure_log_unique and .secure_log_reset directives.
...
llvm-svn: 107077
2010-06-28 21:45:58 +00:00
e697a6f24f
Constant fold x == undef to undef.
...
llvm-svn: 107074
2010-06-28 21:30:07 +00:00
f31c004666
tidy up style. no functional change.
...
llvm-svn: 107073
2010-06-28 21:29:17 +00:00
7c34ece501
Fix Value::stripPointerCasts and BasicAA to avoid trouble on
...
code in unreachable blocks, which have have use-def cycles.
This fixes PR7514.
llvm-svn: 107071
2010-06-28 21:16:52 +00:00
544317dfda
Refactor encoding function for NEON 1-register with modified immediate format.
...
llvm-svn: 107070
2010-06-28 21:16:30 +00:00
584387d5e3
Support Thumb mode encoding of NEON instructions.
...
llvm-svn: 107068
2010-06-28 21:12:19 +00:00
0a5bb081cc
Reduce indentation via early exit. NFC.
...
llvm-svn: 107067
2010-06-28 21:08:32 +00:00
d10b2af260
Include inlined function in list of processed subprograms.
...
llvm-svn: 107065
2010-06-28 20:53:04 +00:00
ee6e29aa72
new, no longer brain-dead, r106907
...
llvm-svn: 107060
2010-06-28 20:26:00 +00:00
ffd628ec0a
After physreg coalescing, physical registers might not have live ranges where
...
you would expect.
Don't assert on that case, just give up.
This fixes PR7513.
llvm-svn: 107046
2010-06-28 19:39:57 +00:00
0d94d7af78
Add more special treatment for inline asm in RegAllocFast.
...
When an instruction has tied operands and physreg defines, we must take extra
care that the tied operands conflict with neither physreg defs nor uses.
The special treatment is given to inline asm and instructions with tied operands
/ early clobbers and physreg defines.
This fixes PR7509.
llvm-svn: 107043
2010-06-28 18:34:34 +00:00
7f103a2653
Fix thinko.
...
llvm-svn: 107042
2010-06-28 18:33:48 +00:00
51f2908328
Pull in the libCrashReporterClient.a information with a warning comment.
...
Remove library check and regenerate configure.
llvm-svn: 107028
2010-06-28 18:25:51 +00:00
f3b2db68c6
Preserve deleted function's local variables' debug info.
...
Radar 8122864.
llvm-svn: 107027
2010-06-28 18:25:03 +00:00
5b1370ee80
use ArgOperand API
...
llvm-svn: 107017
2010-06-28 16:50:57 +00:00
e23efeef10
use ArgOperand API
...
llvm-svn: 107016
2010-06-28 16:45:00 +00:00
18c5bae727
employ CallInst::ArgOffset (for now)
...
llvm-svn: 107015
2010-06-28 16:43:57 +00:00
cd09869dfc
simplify: we have solid argument iterator range
...
llvm-svn: 107014
2010-06-28 16:40:52 +00:00
875a296011
Generalize AAEval so that it can be used both per-function and
...
interprocedurally. Note that as of this writing, existing alias
analysis passes are not prepared to be used interprocedurally.
llvm-svn: 107013
2010-06-28 16:01:37 +00:00
b8c058cbb0
Revert r106907, "make sure to handle dbg_value instructions in the middle of the
...
block, not...", it caused a bunch of nightly test regressions.
llvm-svn: 107009
2010-06-28 15:47:17 +00:00
2dd4307e45
use setArgOperand
...
llvm-svn: 107004
2010-06-28 12:31:35 +00:00
ec60adf161
use CallInst::ArgOffset
...
llvm-svn: 107003
2010-06-28 12:30:07 +00:00
2de43a7c5c
use ArgOperand API and CallInst::ArgOffset
...
llvm-svn: 107002
2010-06-28 12:29:20 +00:00
4300fc77ae
use cached value
...
llvm-svn: 107000
2010-06-28 11:20:42 +00:00
fb6f22f010
Remove dead code.
...
llvm-svn: 106990
2010-06-28 05:59:13 +00:00
f7869a4b81
Use named MDNode, llvm.dbg.sp, to collect subprogram info. This will be used to emit local variable's debug info of deleted functions.
...
llvm-svn: 106989
2010-06-28 05:53:08 +00:00
7ea5fc0794
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
...
llvm-svn: 106988
2010-06-28 04:27:01 +00:00
81170d23de
Do not forget last element, function, while creating Subprogram definition MDNode from subprogram declare MDNode.
...
llvm-svn: 106985
2010-06-27 21:04:31 +00:00
25a843fcd2
minor cleanup to SROA: when lowering type unsafe accesses to
...
large integers, the first inserted value would always create
an 'or X, 0'. Even though this is trivially zapped by
instcombine, don't bother creating this pointless instruction.
llvm-svn: 106979
2010-06-27 07:58:26 +00:00
2041abd958
When splitting a VAARG, remember its alignment.
...
This produces terrible but correct code.
llvm-svn: 106952
2010-06-26 18:22:20 +00:00
418e64a385
Revert my if-conversion cleanup since it caused a bunch of nightly test
...
regressions.
--- Reverse-merging r106939 into '.':
U test/CodeGen/Thumb2/thumb2-ifcvt3.ll
U lib/CodeGen/IfConversion.cpp
llvm-svn: 106951
2010-06-26 17:47:06 +00:00
3a5cb69cb8
Fix PR7328: when turning a tail recursion into a loop, need to preserve
...
the returned value after the tail call if it differs from other return
values. The optimal thing to do would be to introduce a phi node for
the return value, but for the moment just fix the miscompile.
llvm-svn: 106947
2010-06-26 12:53:31 +00:00
7d4038dd88
use ArgOperand API
...
llvm-svn: 106946
2010-06-26 12:17:21 +00:00
c2ac8c4261
use ArgOperand API
...
llvm-svn: 106945
2010-06-26 12:09:10 +00:00
83205af3fa
use ArgOperand API
...
llvm-svn: 106944
2010-06-26 11:51:52 +00:00
a000002428
VNInfos don't need to be destructed anymore.
...
llvm-svn: 106943
2010-06-26 11:30:59 +00:00
e9afee2910
resort to ArgOperand API
...
llvm-svn: 106942
2010-06-26 09:35:09 +00:00
8cfa7713e9
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
...
llvm-svn: 106940
2010-06-26 04:36:50 +00:00
c72da6bb56
Clean up some problems with extra CFG edges being introduced during
...
if-conversion. The RemoveExtraEdges function doesn't work for blocks that
end with unanalyzable branches, so in those cases, the "extra" edges must
be explicitly removed. The CopyAndPredicateBlock and MergeBlocks methods
can also avoid copying successor edges due to branches that have already
been removed. The latter case is especially helpful when MergeBlocks is
called for handling "diamond" if-conversions, where otherwise you can end
up with some weird intermediate states in the CFG. Unfortunately I've
been unable to find cases where this cleanup actually makes a significant
difference in the code. There is one test where we manage to remove an
empty block at the end of a function. Radar 6911268.
llvm-svn: 106939
2010-06-26 04:27:33 +00:00
0248da9db4
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
b71233f34d
It's now possible to run code placement pass for ARM.
...
llvm-svn: 106935
2010-06-26 01:52:05 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
...
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
...
llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
...
"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
...
llvm-svn: 106917
2010-06-25 23:47:23 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
...
Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
acbdf53db4
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
llvm-svn: 106908
2010-06-25 23:14:54 +00:00
c34befc78f
make sure to handle dbg_value instructions in the middle of the block, not
...
just at the head, when doing diamond if-conversion. rdar://7797940
llvm-svn: 106907
2010-06-25 23:05:46 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
...
llvm-svn: 106906
2010-06-25 23:04:29 +00:00
55d738e2e1
Don't track kills in VNInfo. Use interval ends instead.
...
The VNInfo.kills vector was almost unused except for all the code keeping it
updated. The few places using it were easily rewritten to check for interval
ends instead.
The two new methods LiveInterval::killedAt and killedInRange are replacements.
This brings us down to 3 independent data structures tracking kills.
llvm-svn: 106905
2010-06-25 22:53:05 +00:00
02b184de5b
Change if-conversion block size limit checks to add some flexibility.
...
llvm-svn: 106901
2010-06-25 22:42:03 +00:00
2530ca0647
Add support for encoding 3-register NEON instructions, and fix
...
emitNEON2RegInstruction's handling of 2-address operands.
llvm-svn: 106900
2010-06-25 22:40:46 +00:00
fb9712bdae
In GenerateReassociations, don't bother thinking about individual
...
SCEVUnknown values which are loop-variant, as LSR can't do anything
interesting with these values in any case. This fixes very slow compile
times on loops which have large numbers of such values.
llvm-svn: 106897
2010-06-25 22:32:18 +00:00
a34d9b6d84
Add several AVX MOV flavors
...
Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
5c0f85c7dd
Collect debug info for optimized variables of inlined functions.
...
llvm-svn: 106895
2010-06-25 22:07:34 +00:00
8a6deefec6
80 column and typo fix
...
llvm-svn: 106894
2010-06-25 22:02:28 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
e70c8b150b
Add support for encoding 2-register NEON instructions.
...
llvm-svn: 106891
2010-06-25 21:17:19 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
...
llvm-svn: 106886
2010-06-25 21:05:35 +00:00
574f68f815
Fix indentation.
...
llvm-svn: 106881
2010-06-25 20:54:44 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
...
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
ef7acd9a24
We should remove the live range from the destination register only if *all* defs
...
are dead, not just the def of this register. I.e., a register could be dead, but
it's subreg isn't.
Testcase to follow with a subsequent patch.
llvm-svn: 106878
2010-06-25 20:42:55 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
...
llvm-svn: 106877
2010-06-25 20:29:27 +00:00
62d1403a03
More SSE refactoring, this time with different types of MOVs
...
llvm-svn: 106876
2010-06-25 20:22:12 +00:00
89dd42af31
Eliminate a redundant FoldingSet lookup.
...
llvm-svn: 106872
2010-06-25 18:47:08 +00:00
ba3ece6f27
IT instructions are considered to be scheduling hazards, but are scheduled
...
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
llvm-svn: 106871
2010-06-25 18:43:14 +00:00
e76c0b13b9
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
...
llvm-svn: 106867
2010-06-25 18:06:22 +00:00
2ac3b9cbd4
Cosmetic.
...
llvm-svn: 106865
2010-06-25 17:41:07 +00:00
58e6c2eded
Rewrite MemoryBuffer::getSTDIN to use read(2) and a SmallVector buffer.
...
llvm-svn: 106856
2010-06-25 16:07:18 +00:00
2dc70bea54
Remove variables which are assigned to but for which the value
...
is not used. Spotted by gcc-4.6.
llvm-svn: 106854
2010-06-25 14:48:39 +00:00
948dd57945
Bring back the empty vector workaround I removed in r106839. Looks like MSVC needs it.
...
llvm-svn: 106841
2010-06-25 12:51:01 +00:00
ce2a92220f
Tweak MemoryBuffer to allocate the class itself, the name and possibly the
...
buffer in the same chunk of memory.
2 less mallocs for every uninitialized MemoryBuffer and 1 less malloc for every
MemoryBuffer pointing to a memory range translate into 20% less mallocs on
clang -cc1 -Eonly Cocoa_h.m.
llvm-svn: 106839
2010-06-25 11:50:40 +00:00
b890fc8023
use ArgOperand accessors
...
and CallInst for getting hold
of the intrinsic's arguments
simplify along the way (at least for me this is much more legible now)
Bill, Baldrick or Anton, please review\!
llvm-svn: 106838
2010-06-25 11:25:30 +00:00
7dd3afdff3
use ArgOperand API (the simple part)
...
llvm-svn: 106837
2010-06-25 09:44:37 +00:00
eba0be7dc9
use ArgOperand API
...
llvm-svn: 106836
2010-06-25 09:38:13 +00:00
41b81ee2fb
use ArgOperand API
...
llvm-svn: 106835
2010-06-25 09:36:23 +00:00
ed9ae7bf21
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106833
2010-06-25 09:03:52 +00:00
b5874dea6e
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106829
2010-06-25 08:48:19 +00:00
e4eed709d4
use ArgOperand API
...
llvm-svn: 106828
2010-06-25 08:24:59 +00:00
f6207e0a80
prune an include
...
llvm-svn: 106827
2010-06-25 08:16:50 +00:00
e3ba486c9f
use ArgOperand API (one more hunk I could split)
...
llvm-svn: 106825
2010-06-25 07:58:41 +00:00
5f3e656a1b
use ArgOperand API (some hunks I could split)
...
llvm-svn: 106824
2010-06-25 07:57:14 +00:00
07e9284c75
use ArgOperand API; tighten type of handleFreeWithNonTrivialDependency to be able to use isFreeCall whithout a cast or new overload
...
llvm-svn: 106823
2010-06-25 07:40:32 +00:00
07aead2f8d
Add missing ARM and Thumb data layout info for vector types.
...
Radar 8128745.
llvm-svn: 106820
2010-06-25 04:41:08 +00:00
eadbf9732f
Reduce indentation.
...
llvm-svn: 106819
2010-06-25 04:12:31 +00:00
e9eaaa91d8
Fix a case where an earlyclobber operand of an asm
...
is reused as an input. PR 4118. Testcase is too big,
as usual with bugs in this area, but there's one in
the PR.
llvm-svn: 106816
2010-06-25 00:49:43 +00:00
cbdcce6478
Add some AVX convert instructions
...
llvm-svn: 106815
2010-06-25 00:39:30 +00:00
889ab7d158
Make sure all eliminated kills are removed from VNInfo lists.
...
This fixes PR7479 and PR7485. The test cases from those PRs are big, so not
included. However, PR7485 comes from self hosting on FreeBSD, so we will surely
hear about any regression.
llvm-svn: 106811
2010-06-24 23:57:35 +00:00
5f0bf64c0c
Add some comments.
...
llvm-svn: 106809
2010-06-24 23:41:59 +00:00
447735aa98
Refactoring of SSE convert intrinsics
...
llvm-svn: 106808
2010-06-24 23:37:07 +00:00
9a2f0473b2
Teach EmitLiveInCopies to omit copies for unused virtual registers,
...
and to clean up unused incoming physregs from the live-in list.
llvm-svn: 106805
2010-06-24 22:23:02 +00:00
78827d1952
Refactoring of SSE conversion instructions
...
llvm-svn: 106804
2010-06-24 22:22:21 +00:00
6b6b605917
Refactor SSE cmp intrinsics and declare the same for AVX
...
llvm-svn: 106796
2010-06-24 22:04:40 +00:00
2d3c490026
It's possible that a flag is added to the SDNode that points back to the
...
original SDNode. This is badness. Also, this function allows one SDNode to point
multiple flags to another SDNode. Badness as well.
llvm-svn: 106793
2010-06-24 22:00:37 +00:00
c657c621b7
DBG_VALUE machine instruction pointing to undefined register for a variable justify a separate scope if the variable is inlined function's argument.
...
Radar 8122864.
llvm-svn: 106792
2010-06-24 21:51:19 +00:00
2b87d44c5d
Don't return a std::vector in the Spiller interface, but take a reference to a
...
vector instead. This avoids needless copying and allocation.
Add documentation.
llvm-svn: 106788
2010-06-24 20:54:29 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
...
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
9b659142a6
Remove the now unused LiveIntervals::getVNInfoSourceReg().
...
This method was always a bit too simplistic for the real world. It didn't really
deal with subregisters and such.
llvm-svn: 106781
2010-06-24 20:18:15 +00:00
487ed997d0
Teach AdjustCopiesBackFrom to also use CoalescerPair to identify compatible copies.
...
llvm-svn: 106780
2010-06-24 20:16:00 +00:00
5ad5226c58
Disallow matching "i" constraint to symbol addresses when
...
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
llvm-svn: 106779
2010-06-24 20:14:51 +00:00
7f894d8fdc
Remove the -fast-spill option.
...
This code path has never really been used, and we are going to be handling
spilling through the Spiller interface in the future.
llvm-svn: 106777
2010-06-24 19:56:08 +00:00
c26e2f4b70
Oops. IT block formation pass needs to be run at any optimization level.
...
llvm-svn: 106775
2010-06-24 19:10:14 +00:00
3f0e992af1
Loosen up the requirements in the Horrible Hack(tm) to include all selectors
...
which don't have a catch-all associated with them not just clean-ups. This fixes
the SingleSource/Benchmarks/Shootout-C++/except.cpp testcase that broke because
of my change r105902.
llvm-svn: 106772
2010-06-24 18:49:10 +00:00
246c41d93e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
...
llvm-svn: 106770
2010-06-24 18:20:04 +00:00
45230239e4
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
This second attempt fixes some crashes that only occurred Linux.
llvm-svn: 106769
2010-06-24 18:15:01 +00:00
4143e9deeb
Add an exports file for the Hello example plugin.
...
llvm-svn: 106768
2010-06-24 17:36:51 +00:00
a612d7c012
Print the LSBs of a SlotIndex symbolically using letters referring to the
...
[L]oad, [u]se, [d]ef, or [S]tore slots.
This makes it easier to see if two indices refer to the same instruction,
avoiding mental mod 4 calculations.
llvm-svn: 106766
2010-06-24 17:31:07 +00:00
8a84cd57ae
Simplify this code; switch lowering shouldn't produce cases
...
which trivially fold away.
llvm-svn: 106765
2010-06-24 17:08:31 +00:00
963b1c142e
A few minor micro-optimizations.
...
llvm-svn: 106764
2010-06-24 16:57:52 +00:00
47ddf76d89
Teach getExactSDiv to evaluate x/1 to x up front, as it's a common
...
enough special case, and it theoretically allows more folding because
it works even when x is unanalyzable.
llvm-svn: 106763
2010-06-24 16:51:25 +00:00
279e55fb2e
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
...
form so they can be narrowed to 16-bit instructions.
llvm-svn: 106762
2010-06-24 16:50:20 +00:00
5235cc2c25
Don't try to preserve pointer types in SCEVConstants; the old code
...
was over-complicated.
llvm-svn: 106760
2010-06-24 16:47:03 +00:00
ab5422200b
Fix copy+pasto issues in isMulSExtable.
...
llvm-svn: 106759
2010-06-24 16:45:11 +00:00
3ace9f4e3d
Make the trunc code consistent with the zext and sext code in its
...
handling of pointer types.
llvm-svn: 106757
2010-06-24 16:33:38 +00:00
b377e2828d
Add overloads for getFile and getFileOrSTDIN which take a const char *
...
instead of a StringRef, avoiding the need to copy the string in the
common case.
llvm-svn: 106754
2010-06-24 16:25:50 +00:00
3b2b46a700
Be more strict about subreg-to-subreg copies in CoalescerPair.
...
Also keep track of the original DstREg before subregister adjustments.
llvm-svn: 106753
2010-06-24 16:19:28 +00:00
7ccec09252
use ArgOperand API
...
llvm-svn: 106752
2010-06-24 16:11:44 +00:00
53ccab7d1c
Verify that VNI kills are pointing to existing instructions.
...
In this case it is essential that the kill is real because the spiller will
decide to omit a spill if it thinks there is a later kill.
llvm-svn: 106751
2010-06-24 15:56:59 +00:00
a6d75e2cf7
use (even more, still) ArgOperand API
...
llvm-svn: 106750
2010-06-24 15:51:11 +00:00
463f26b4be
Eliminate the other half of the BRCOND optimization, and update
...
as many tests as possible.
llvm-svn: 106749
2010-06-24 15:24:03 +00:00
df6b33e778
Eliminate the first have of the optimization which eliminates BRCOND
...
when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.
I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.
llvm-svn: 106748
2010-06-24 15:04:11 +00:00
218f5541b2
use ArgOperand API and CallSite for arg range; add necessary casts and perform some cosmetics
...
llvm-svn: 106747
2010-06-24 14:42:01 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
...
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
5aafdf1e43
use ArgOperand API and CallSite for arg range
...
llvm-svn: 106745
2010-06-24 14:13:36 +00:00
0a136c9b53
use (even more) ArgOperand API
...
llvm-svn: 106744
2010-06-24 13:54:33 +00:00
590d95ed18
use ArgOperand API
...
llvm-svn: 106743
2010-06-24 13:42:49 +00:00
589a0b950a
use ArgOperand API
...
llvm-svn: 106740
2010-06-24 12:58:35 +00:00
7943017490
use ArgOperand API
...
llvm-svn: 106737
2010-06-24 12:35:13 +00:00
75f6943c95
use ArgOperand API, also tighten the type of visitFree to make this work out smoothly
...
llvm-svn: 106736
2010-06-24 12:21:15 +00:00
91f9589057
use ArgOperand API; introduce downcasted pointers into scope to facilitate this
...
llvm-svn: 106734
2010-06-24 12:03:56 +00:00
e2f482ca0b
use ArgOperand API
...
llvm-svn: 106731
2010-06-24 10:42:46 +00:00
2d958d4db5
use ArgOperand API
...
llvm-svn: 106730
2010-06-24 10:17:17 +00:00
5bcaa55761
use callsite to obtain all arguments
...
llvm-svn: 106729
2010-06-24 10:04:07 +00:00
42f620cc55
use callsite to obtain all arguments
...
llvm-svn: 106728
2010-06-24 09:56:43 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
...
rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
c4e84309c4
more cleanups
...
llvm-svn: 106724
2010-06-24 07:18:14 +00:00
056fd06c5f
reduce indentation
...
llvm-svn: 106723
2010-06-24 07:16:25 +00:00
cfed96a410
fix breakage from r98938 by correctly marking msp430 calls as variadic.
...
Patch by Ben Ransford!
llvm-svn: 106722
2010-06-24 06:46:50 +00:00
c3e291c560
Fix a bug in the code which determines when it's safe to use the
...
bt instruction, which was exposed by r106263.
llvm-svn: 106718
2010-06-24 02:07:59 +00:00
fa6ce139a9
Add a couple more quick comments.
...
llvm-svn: 106717
2010-06-24 02:07:57 +00:00
0695e09b09
Optimize the "bit test" code path for switch lowering in the
...
case where the bit mask has exactly one bit.
llvm-svn: 106716
2010-06-24 02:06:24 +00:00
dbb58d2974
Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
...
Whiny buildbots.
llvm-svn: 106710
2010-06-24 00:52:22 +00:00
0f60709f0e
use getNumArgOperands
...
llvm-svn: 106709
2010-06-24 00:48:48 +00:00
4a39b84a9d
use ArgOperand API
...
llvm-svn: 106707
2010-06-24 00:44:01 +00:00
0dc3c2d37e
Use ValueMap instead of DenseMap.
...
The ValueMapper used by various cloning utility maps MDNodes also.
llvm-svn: 106706
2010-06-24 00:33:28 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
...
llvm-svn: 106705
2010-06-24 00:32:06 +00:00
6af02a6f69
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
...
llvm-svn: 106702
2010-06-24 00:15:50 +00:00
f38e6720cc
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
llvm-svn: 106701
2010-06-24 00:12:39 +00:00
d8dedee96d
Use available typedef for " DenseMap<const Value*, Value*>".
...
llvm-svn: 106699
2010-06-24 00:00:42 +00:00
b8f11de105
Cosmetic change.
...
Do not use "ValueMap" as a name for a local variable or an argument.
llvm-svn: 106698
2010-06-23 23:55:51 +00:00
1abbde3103
use ArgOperand accessors
...
llvm-svn: 106697
2010-06-23 23:38:07 +00:00
f470747a36
We are missing opportunites to use ldm. Take code like this:
...
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
llvm-svn: 106693
2010-06-23 23:00:16 +00:00
253c6bf366
use the new isFreeCall API and ArgOperand accessors
...
llvm-svn: 106692
2010-06-23 22:48:06 +00:00
5f5a864539
minor enhancement to llvm::isFreeCall API: return CallInst; no functional change
...
llvm-svn: 106686
2010-06-23 21:51:12 +00:00
ad7884ad98
use ArgOperand getters
...
llvm-svn: 106685
2010-06-23 21:41:47 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
...
llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
...
llvm-svn: 106678
2010-06-23 21:10:57 +00:00
5fed9b7c6c
Update according to feedback.
...
llvm-svn: 106677
2010-06-23 20:49:35 +00:00
360d6fe299
Add AVX SHUF{PS,PD}{rr,rm} instructions
...
llvm-svn: 106672
2010-06-23 20:07:15 +00:00
337e8db712
Add support for the x86 instructions "pusha" and "popa".
...
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
d24c66b4a3
Do not do tail calls to external symbols. If the
...
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
llvm-svn: 106662
2010-06-23 18:52:34 +00:00
a136521a17
MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
...
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.
llvm-svn: 106643
2010-06-23 18:16:24 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
6f71039fa4
The generic DAG combiner can now fold atomic fences when needed, so switch
...
to using that.
llvm-svn: 106633
2010-06-23 16:25:07 +00:00
a8ea498171
When using libcall expansions for the atomic intrinsics, the explicit
...
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
llvm-svn: 106631
2010-06-23 16:08:49 +00:00
b58c08b0ba
Some targets don't require the fencing MEMBARRIER instructions surrounding
...
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
llvm-svn: 106630
2010-06-23 16:07:42 +00:00
731ea71f59
Add a few VNInfo data structure checks.
...
llvm-svn: 106627
2010-06-23 15:34:36 +00:00
4d18165f82
use ArgOperand accessors
...
llvm-svn: 106626
2010-06-23 13:56:57 +00:00
c9a9251844
use ArgOperand accessors
...
llvm-svn: 106623
2010-06-23 13:09:06 +00:00
e54065394e
use helper to neatly access arguments
...
llvm-svn: 106622
2010-06-23 08:45:32 +00:00
3d6e2c6335
Update uses, defs, and comments for darwin tls patterns.
...
llvm-svn: 106621
2010-06-23 08:01:49 +00:00
ef5a4383ad
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
...
Conflicts:
lib/CodeGen/MachineSink.cpp
llvm-svn: 106614
2010-06-23 00:48:25 +00:00
7f85520644
Get the addend correct for i386 pic.
...
Thanks Daniel!
llvm-svn: 106608
2010-06-22 23:51:47 +00:00
75c6b0bb1f
Replace ScalarEvolution's private copy of getLoopPredecessor
...
with LoopInfo's public copy.
llvm-svn: 106603
2010-06-22 23:43:28 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
9ad629367d
Revert 106592 for now. It causes clang-selfhost build failure.
...
llvm-svn: 106598
2010-06-22 23:29:55 +00:00
1081f1a0f5
Fix OptimizeMax to handle an odd case where one of the max operands
...
is another max which folds. This fixes PR7454.
llvm-svn: 106594
2010-06-22 23:07:13 +00:00
535aa8ea91
Reapply support for AVX unpack and interleave instructions, with
...
testcases this time.
llvm-svn: 106593
2010-06-22 23:02:38 +00:00
87f75f75be
If a metadata operand is seeded in value map and the metadata should also be seeded in value map. This is not limited to function local metadata.
...
Failure to seed metdata in such cases causes troubles when in a cloned module, metadata from a new module refers to values in old module. Usually this results in mysterious bugpoint crashes. For example,
Checking to see if we can delete global inits: Unknown constant!
UNREACHABLE executed at /d/g/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:904!
llvm-svn: 106592
2010-06-22 22:53:21 +00:00
e43c6487da
While cloning a module, clone metadata attached with instructions.
...
llvm-svn: 106591
2010-06-22 22:50:42 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
...
llvm-svn: 106588
2010-06-22 22:38:56 +00:00
8ce69cd95a
Fix the formatting of the switch statement and add a missing break.
...
llvm-svn: 106586
2010-06-22 22:16:17 +00:00
1023f6bd98
Also convert SUBREG_TO_REG to a KILL when relevant, like the other subreg
...
instructions.
This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.
llvm-svn: 106583
2010-06-22 22:11:07 +00:00
c5d712232d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
...
Radar 8031193.
llvm-svn: 106582
2010-06-22 22:04:24 +00:00
e9c1bb6cb1
Look for and use a different darwin crash reporter library.
...
llvm-svn: 106576
2010-06-22 21:01:04 +00:00
6c275bc5a2
fix typo
...
llvm-svn: 106574
2010-06-22 20:52:02 +00:00
c89d2aad4c
use high-level accessors
...
llvm-svn: 106573
2010-06-22 20:40:38 +00:00
b575cf69f4
warmup ritual: use high-level argument accessors
...
llvm-svn: 106563
2010-06-22 19:46:37 +00:00
e3fbbd19ed
Clone named metadata while cloning a module.
...
Reapply Bob's patch.
llvm-svn: 106560
2010-06-22 18:52:38 +00:00
3af915f84b
Reorganize logical and arithmetic SSE 1 & 2 instructions
...
llvm-svn: 106557
2010-06-22 18:17:40 +00:00
b91af24d3e
Reorganize SSE instructions, making easier to see oportunities for refactoring
...
llvm-svn: 106556
2010-06-22 18:09:32 +00:00
3570f81b1e
Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks out
...
into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.
llvm-svn: 106555
2010-06-22 17:25:57 +00:00
9c47dac677
Remove the SimpleJoin optimization from SimpleRegisterCoalescing.
...
Measurements show that it does not speed up coalescing, so there is no reason
the keep the added complexity around.
Also clean out some unused methods and static functions.
llvm-svn: 106548
2010-06-22 16:13:57 +00:00
d2d1ae105d
Use pre-increment instead of post-increment when the result is not used.
...
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
2ceaa71bdb
Add an explicit keyword.
...
llvm-svn: 106538
2010-06-22 13:53:29 +00:00
f820bd327d
Allow "exhaustive" trip count evaluation on phi nodes with all
...
constant operands.
llvm-svn: 106537
2010-06-22 13:15:46 +00:00
f040dec68a
Revert 106528. It is causing self host failures.
...
llvm-svn: 106529
2010-06-22 06:14:09 +00:00
b195eb4acf
Do not rely on DenseMap slot which can be easily invalidated when DenseMap grows.
...
llvm-svn: 106528
2010-06-22 05:16:56 +00:00
6c1fc79cab
Revert my change to clone named metadata. Buildbots are complaining.
...
--- Reverse-merging r106508 into '.':
U lib/Transforms/Utils/CloneModule.cpp
llvm-svn: 106521
2010-06-22 02:08:51 +00:00
2370e2fe0f
When unfolding a load, avoid assuming which instruction that
...
kill and dead flags will end up on.
llvm-svn: 106520
2010-06-22 02:07:21 +00:00
b6e058da18
Use single interface, using twine, to get named metadata.
...
getNamedMetadata().
llvm-svn: 106518
2010-06-22 01:19:38 +00:00
37bb617f8a
Tail merging pass shall not break up IT blocks. rdar://8115404
...
llvm-svn: 106517
2010-06-22 01:18:16 +00:00
cbc6fd8493
Discard special LLVM prefix from linkage name.
...
llvm-svn: 106516
2010-06-22 01:06:05 +00:00
ad51735794
Do not rely on Twine temporaries to survive.
...
llvm-svn: 106515
2010-06-22 01:01:58 +00:00
60bb7c42a7
make sure to initialize indent_level
...
llvm-svn: 106513
2010-06-22 00:40:26 +00:00
851e478e6b
Fix the new load-unfolding code to update LiveVariable's dead flags,
...
in addition to the kill flags.
llvm-svn: 106512
2010-06-22 00:32:04 +00:00
5f9575c1cd
Include named metadata when cloning a module.
...
llvm-svn: 106508
2010-06-22 00:11:03 +00:00
64960f55fe
add some support for blockaddress. This isn't really enough to be useful,
...
but it will cover uses of blockaddress that are actually in a function.
llvm-svn: 106502
2010-06-21 23:19:36 +00:00
bb45b964f8
eliminate a mutable global variable, use raw_ostream::indent instead of
...
rolling our own.
llvm-svn: 106501
2010-06-21 23:14:47 +00:00
a0b8c90870
un-indent a huge amount of code out of an anonymous namespace.
...
llvm-svn: 106500
2010-06-21 23:12:56 +00:00
b7dadb0e95
revert r106482
...
llvm-svn: 106499
2010-06-21 22:59:03 +00:00
3c1b3c61e9
Teach two-address lowering how to unfold a load to open up commuting
...
opportunities. For example, this lets it emit this:
movq (%rax), %rcx
addq %rdx, %rcx
instead of this:
movq %rdx, %rcx
addq (%rax), %rcx
in the case where %rdx has subsequent uses. It's the same number
of instructions, and usually the same encoding size on x86, but
it appears faster, and in general, it may allow better scheduling
for the load.
llvm-svn: 106493
2010-06-21 22:17:20 +00:00
510d9a3404
change parameter name to avoid confusion with global definition
...
llvm-svn: 106486
2010-06-21 21:28:07 +00:00
72df24037e
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
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Radar 8104310.
llvm-svn: 106484
2010-06-21 21:27:34 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
374b2195f6
Add unpack and interleave AVX instructions, encoding tests cooming soon
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llvm-svn: 106482
2010-06-21 21:21:48 +00:00
1fb4de8ec5
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
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llvm-svn: 106481
2010-06-21 21:21:14 +00:00
79d2075e4a
"This is just a cosmetic change in MCAsmStreamer.cpp/EmitSymbolAttribute: all attributes have now a \t before and after, as done for '.type'.
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This makes the output look consistent, as well as help some third party assemblers expecting the attributes to be in the second column."
Patch by Arnaud de Grandmaison!
llvm-svn: 106469
2010-06-21 20:35:01 +00:00
6dd51a2bb6
Remove isTwoAddress from SystemZ.
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llvm-svn: 106467
2010-06-21 20:25:57 +00:00
d7a7356be6
Remove isTwoAddress from Sparc.
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llvm-svn: 106466
2010-06-21 20:22:35 +00:00
c7927f2013
Remove isTwoAddress from Mips.
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llvm-svn: 106465
2010-06-21 20:19:21 +00:00
fb008dfa05
Remove isTwoAddress from Blackfin.
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llvm-svn: 106457
2010-06-21 20:13:37 +00:00
fa1b54d26e
Remove isTwoAddress from MSP430.
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llvm-svn: 106455
2010-06-21 20:07:30 +00:00
dd41bba517
Use A.append(...) instead of A.insert(A.end(), ...) when A is a
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SmallVector, and other SmallVector simplifications.
llvm-svn: 106452
2010-06-21 19:47:52 +00:00
0ca648d758
Make 80-column.
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llvm-svn: 106448
2010-06-21 18:56:55 +00:00
98392f69e3
Remove isTwoAddress from PIC16.
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llvm-svn: 106447
2010-06-21 18:55:01 +00:00
2401271217
Remove isTwoAddress from XCore.
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llvm-svn: 106446
2010-06-21 18:51:38 +00:00
e159407231
Remove isTwoAddress from Alpha.
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llvm-svn: 106445
2010-06-21 18:48:55 +00:00
ffdee30e90
Move several non-performance-critical member functinos out of line.
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llvm-svn: 106444
2010-06-21 18:46:45 +00:00
e80de80270
Do not directly use function names to construct new name for named metadata.
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"llvm.dbg.lv.~A" is not a valid name.
llvm-svn: 106438
2010-06-21 18:36:58 +00:00
29a894dd64
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
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llvm-svn: 106437
2010-06-21 18:36:04 +00:00
20de4258f8
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
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llvm-svn: 106436
2010-06-21 18:22:54 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
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handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
bf572c7cea
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
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Based on a patch by Patrick Marlier!
llvm-svn: 106433
2010-06-21 18:21:27 +00:00
97c8a6a928
early exit for dbg_value instructions
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llvm-svn: 106430
2010-06-21 17:49:23 +00:00
74b5e3e0ae
remove some dead variables reported by clang++
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llvm-svn: 106428
2010-06-21 17:20:18 +00:00
bbc29ea821
Revert r106422, which is breaking the non-fast-isel path.
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llvm-svn: 106423
2010-06-21 16:02:28 +00:00
f64fdd69d0
More changes for non-top-down fast-isel.
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Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.
llvm-svn: 106422
2010-06-21 15:13:54 +00:00
0ab5a02579
Mark the SPU 'lr' instruction to never have side effects.
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This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
2010-06-21 15:08:16 +00:00
d7f50c118a
Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
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llvm-svn: 106419
2010-06-21 14:42:19 +00:00
f91aff5f13
Do one lookup instead of two.
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llvm-svn: 106415
2010-06-21 14:21:47 +00:00
7c58cf75fa
Generalize this to look in the regular ValueMap in addition to
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the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.
llvm-svn: 106414
2010-06-21 14:17:46 +00:00
1cae86f704
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
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I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
llvm-svn: 106413
2010-06-21 13:31:32 +00:00
6f58190f6f
Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
...
used to choke llc with the attached test.
llvm-svn: 106411
2010-06-21 10:17:36 +00:00
c596baa56d
wip
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llvm-svn: 106408
2010-06-21 02:17:34 +00:00
dcc7b6dcb6
Fix warning in no-asserts build.
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llvm-svn: 106405
2010-06-20 20:27:42 +00:00
884a8fe5fa
Fix a crash caused by dereference of MBB.end(). rdar://8110842
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llvm-svn: 106399
2010-06-20 00:54:38 +00:00
c515ab1eb2
Restore a call to rememberInstruction which was accidentally dropped
...
in refactoring.
llvm-svn: 106398
2010-06-19 22:50:35 +00:00
32655906e4
Add a TODO comment.
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llvm-svn: 106397
2010-06-19 21:30:18 +00:00
51d00092b6
Include the use kind along with the expression in the key of the
...
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.
More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.
llvm-svn: 106396
2010-06-19 21:29:59 +00:00
297fb8b9fc
Don't include things in anonymous namespaces that don't need it.
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llvm-svn: 106395
2010-06-19 21:21:39 +00:00
bf5c3d42ba
Use calloc instead of new/memset, it is more efficient when the set is very large.
...
llvm-svn: 106390
2010-06-19 17:00:31 +00:00
866971ed3d
Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid
...
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.
llvm-svn: 106389
2010-06-19 14:17:24 +00:00
d277246137
Factor out duplicated code for reusing and inserting casts into
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a helper function.
llvm-svn: 106388
2010-06-19 13:25:23 +00:00
4581434c27
Tidy.
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llvm-svn: 106383
2010-06-19 05:33:57 +00:00
6d12973143
Remove a fixme comment that is no longer relevant.
...
llvm-svn: 106382
2010-06-19 05:32:41 +00:00
0ae08935f6
Fix error message to match function name.
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llvm-svn: 106381
2010-06-19 05:32:09 +00:00
b86a3abcc7
Refactoring of regular logical packed instructions to prepare for AVX ones.
...
llvm-svn: 106375
2010-06-19 04:09:22 +00:00
8737b7d73d
Refactor aliased packed logical instructions, also add
...
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
llvm-svn: 106374
2010-06-19 02:44:01 +00:00
7079bf815d
Ignore dbg_value's.
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llvm-svn: 106373
2010-06-19 02:36:21 +00:00
a588049ce9
Move new sse 1 & 2 generic classes to a more appropriate place
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llvm-svn: 106372
2010-06-19 01:32:46 +00:00
2787efd961
Remove unnecessary arguments
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llvm-svn: 106371
2010-06-19 01:22:34 +00:00
00ada89f95
Add AVX packed intrinsics for MIN, MAX
...
llvm-svn: 106370
2010-06-19 01:17:05 +00:00
f3c01f3ef6
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
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llvm-svn: 106368
2010-06-19 01:01:32 +00:00
42105b2976
Finish ripping isTwoAddress out of X86. Some mindless formatting
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and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
llvm-svn: 106367
2010-06-19 00:37:40 +00:00
1e205f6b1c
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
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llvm-svn: 106366
2010-06-19 00:37:31 +00:00
c60cecd88b
rip out dead code.
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llvm-svn: 106365
2010-06-19 00:34:14 +00:00
e808a78ac1
fix rdar://7873482 by teaching the instruction encoder to emit
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segment prefixes. Daniel wrote most of this patch.
llvm-svn: 106364
2010-06-19 00:34:00 +00:00
e5fcd333da
Indentation and remove dead code.
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llvm-svn: 106362
2010-06-19 00:11:54 +00:00
1888f11887
Clean up: remove now unnecessary Constraints
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llvm-svn: 106361
2010-06-19 00:09:27 +00:00
5fc43eb186
Silence compiler warnings.
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llvm-svn: 106360
2010-06-19 00:02:06 +00:00
502c4fe61c
more refactoring! yay! big win over the intrinsics
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llvm-svn: 106359
2010-06-19 00:00:22 +00:00
6bdbdb5544
Remove isTwoAddress from here too.
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llvm-svn: 106358
2010-06-18 23:56:07 +00:00
66d2d57d9b
Fix typo, SSE1 should be used by XS, not SSE2
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llvm-svn: 106357
2010-06-18 23:53:27 +00:00
3577c1b811
Remove isTwoAddress from 64-bit files.
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llvm-svn: 106356
2010-06-18 23:51:21 +00:00
119824ed4d
Move ARM if-conversion before post-ra scheduling.
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llvm-svn: 106355
2010-06-18 23:32:07 +00:00
8693650422
Teach regular and fast isel to set dead flags on unused implicit defs
...
on calls and similar instructions.
llvm-svn: 106353
2010-06-18 23:28:01 +00:00
2bfad417a1
Apply some refactor to packed instructions
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llvm-svn: 106349
2010-06-18 23:13:35 +00:00
4f0781c9b3
Update cmake list.
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llvm-svn: 106348
2010-06-18 23:12:10 +00:00
285935939d
Thumb2 hazard recognizer.
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llvm-svn: 106347
2010-06-18 23:11:35 +00:00
678927e0b1
Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up
...
the inserted INSERT_SUBREGs after us.
llvm-svn: 106345
2010-06-18 23:10:20 +00:00
2d51c7c592
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
2010-06-18 23:09:54 +00:00
a57c2885cf
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
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llvm-svn: 106342
2010-06-18 23:03:10 +00:00
6860bb7796
Enable Expand handling of atomics for subtargets that can't do them inline.
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llvm-svn: 106336
2010-06-18 22:35:32 +00:00
07f4fa8198
TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
...
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.
Fix it in LiveVariableAnalysis by adding the <undef> flag.
llvm-svn: 106333
2010-06-18 22:29:44 +00:00
cf9e8a987f
Fix an inverted condition.
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llvm-svn: 106330
2010-06-18 22:17:13 +00:00
871439abd2
Use the new 'defm' class inheritance in SSE
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llvm-svn: 106327
2010-06-18 22:10:11 +00:00
f5d62535a5
Fix cross initialization compilation error.
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llvm-svn: 106324
2010-06-18 22:01:37 +00:00
c0e0d85b18
Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.
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llvm-svn: 106323
2010-06-18 21:52:57 +00:00
d64dfc1568
Add Expand-to-libcall support for additional atomics. This covers the usual
...
entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.
This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.
llvm-svn: 106321
2010-06-18 21:43:38 +00:00
a92e41a50a
Rewrite chained if's as switches and replace assertions with llvm_unreachable
...
(as suggested in radar 8104405).
llvm-svn: 106318
2010-06-18 21:32:42 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
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llvm-svn: 106314
2010-06-18 21:07:47 +00:00
22a212f97c
When using ADDri to get the address of a stack object, 255 is a conservative
...
limit on the offset that can be materialized without using the register
scavenger.
llvm-svn: 106312
2010-06-18 20:59:25 +00:00
a46d607545
Make this comment less specific.
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llvm-svn: 106311
2010-06-18 20:45:41 +00:00
af4903d6ee
Fix X86FastISel's address-mode folding to stay within the
...
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.
llvm-svn: 106310
2010-06-18 20:44:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
...
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
24ceda8eb0
Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
...
optimizations. There is still some nondeterminism remaining.
llvm-svn: 106306
2010-06-18 19:54:20 +00:00
4c807fca97
Reapply 105540, 105542, and 105548, and revert r105732.
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llvm-svn: 106304
2010-06-18 19:26:04 +00:00
45073042eb
Reapply 105546.
...
llvm-svn: 106302
2010-06-18 19:12:32 +00:00
9136d9fbf8
Reapply 105544.
...
llvm-svn: 106301
2010-06-18 19:09:27 +00:00
c1570dda5c
Enable tail calls on ARM by default, with some
...
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
llvm-svn: 106299
2010-06-18 19:00:18 +00:00
e5457c275d
Don't leak RegClass2VRegMap, which is now a new[] array instead of a
...
std::vector.
llvm-svn: 106298
2010-06-18 18:54:05 +00:00
Bill Wendling