35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
...
llvm-svn: 107701
2010-07-06 21:26:18 +00:00
15fed3bd30
One more case assuming that subregs have live ranges.
...
llvm-svn: 107700
2010-07-06 21:13:03 +00:00
bcf3409107
Fix buildbot breakage where a def is missing.
...
llvm-svn: 107698
2010-07-06 21:06:39 +00:00
b36df17b08
Add fixme.
...
llvm-svn: 107697
2010-07-06 21:05:17 +00:00
a64c0a3d22
Be more forgiving when calculating alias interference for physreg coalescing.
...
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.
This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.
llvm-svn: 107695
2010-07-06 20:31:51 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
dfc8b745a2
Fix to 80-col.
...
llvm-svn: 107684
2010-07-06 18:35:20 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
dde2ba0b60
tighten up this code.
...
llvm-svn: 107670
2010-07-06 15:59:27 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
4e49b59dad
Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
...
which do not depend on SelectionDAG.
llvm-svn: 107666
2010-07-06 15:39:54 +00:00
2b2a1c3c86
Make getMinimalPhysRegClass' comment mention what makes it different
...
from getPhysicalRegisterRegClass.
llvm-svn: 107660
2010-07-06 15:31:55 +00:00
e415230477
Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
...
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').
llvm-svn: 107658
2010-07-06 15:24:56 +00:00
1e33b18e28
Add some more TODO comments.
...
llvm-svn: 107657
2010-07-06 15:23:00 +00:00
f855b39edd
Add a comment.
...
llvm-svn: 107656
2010-07-06 15:21:57 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
dace239949
Detabify this file.
...
llvm-svn: 107637
2010-07-06 03:53:43 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
d5ac287140
Remove some unused/redundant code.
...
llvm-svn: 107622
2010-07-05 18:40:09 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
2c0315a0f3
random tidying
...
llvm-svn: 107612
2010-07-05 05:36:21 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
ac0a210789
Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
...
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
f3aeb2c22c
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
...
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
f844642350
Proper indentation.
...
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
c8f595212f
Minor amendment to switch-lowering improvement.
...
llvm-svn: 107569
2010-07-03 08:43:32 +00:00
836fdbc85b
Note switch-lowering inefficiency.
...
llvm-svn: 107565
2010-07-03 07:38:12 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
128a0197bb
Fix typo.
...
llvm-svn: 107556
2010-07-03 01:09:18 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
...
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
...
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
621c85b038
Add AVX SSE4.1 round instructions
...
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
4c82a9e7d0
Detect and handle COPY in many places.
...
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.
llvm-svn: 107547
2010-07-03 00:04:37 +00:00
5b59c1bf1f
Simple refactoring of SSE4.1 instructions, making room for the AVX forms
...
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
5e5416056b
80-col fixup.
...
llvm-svn: 107537
2010-07-02 23:17:38 +00:00
676a15bdf5
Add a new target independent COPY instruction and code to lower it.
...
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.
COPY is lowered to native register copies by LowerSubregs.
llvm-svn: 107529
2010-07-02 22:29:50 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
...
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
3c43248560
Custom inserters (e.g., conditional moves in Thumb1 can introduce
...
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.
rdar://8022442
llvm-svn: 107517
2010-07-02 21:23:37 +00:00
cefe3831b7
MDString is already checked earlier.
...
llvm-svn: 107516
2010-07-02 21:13:23 +00:00
c3525dc0fd
Remove early IT block formation. It's not used.
...
llvm-svn: 107513
2010-07-02 21:07:09 +00:00
0ce84486c3
- Two-address pass should not assume unfolding is always successful.
...
- X86 unfolding should check if the instructions being unfolded has memoperands.
If there is no memoperands, then it must assume conservative alignment. If this
would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
etc. should not unfold the instruction.
llvm-svn: 107509
2010-07-02 20:36:18 +00:00
4d887f7ca7
Propagate the AlignStack bit in InlineAsm's to the
...
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
llvm-svn: 107506
2010-07-02 20:16:09 +00:00
df8429aeb4
Remove invalid assert
...
llvm-svn: 107505
2010-07-02 19:54:47 +00:00
cf6c5c960f
Properly handle debug values during inline spilling.
...
llvm-svn: 107503
2010-07-02 19:54:40 +00:00
9da02a83e9
beautify output
...
llvm-svn: 107500
2010-07-02 19:26:28 +00:00
e537ddbdb4
use ArgOperand API
...
llvm-svn: 107498
2010-07-02 19:08:46 +00:00
832282e061
Don't claim to preserve AliasAnalysis. First, this is doesn't actually
...
have any effect, and second, deleting stores can potentially invalidate
an AliasAnalysis, and there's currently no notification for this.
llvm-svn: 107496
2010-07-02 18:43:05 +00:00
96037187e5
Rematerialize as much as possible before inserting spills and reloads.
...
This allows us to recognize the common case where all uses could be
rematerialized, and no stack slot allocation is necessary.
If some values could be fully rematerialized, remove them from the live range
before allocating a stack slot for the rest.
llvm-svn: 107492
2010-07-02 17:44:57 +00:00
9b7755fbc6
80-column and trailing whitespace cleanup.
...
llvm-svn: 107490
2010-07-02 17:41:59 +00:00
64a4f3f062
grammar tweaks
...
llvm-svn: 107489
2010-07-02 17:38:34 +00:00
771d04b969
Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
...
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.
llvm-svn: 107487
2010-07-02 17:23:44 +00:00
56de4675b6
use ArgOperand API (found by my previous commit)
...
llvm-svn: 107482
2010-07-02 13:37:16 +00:00
ee8d80d6a3
IndirectBr is not safe to speculatively execute (!)
...
llvm-svn: 107454
2010-07-02 00:35:34 +00:00
93f5920914
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
...
llvm-svn: 107451
2010-07-02 00:10:16 +00:00
4ca8ddaceb
Shrink down SSE3 code by more multiclass refactoring
...
llvm-svn: 107448
2010-07-01 23:10:49 +00:00
504055ce9e
Make the "linker_private" linkage type emit a non-weak symbol to the file. It
...
will still be stripped by the linker when it generates the final image.
llvm-svn: 107440
2010-07-01 22:38:24 +00:00
0a17241a0d
Shrink down SSE3 code by some multiclass refactoring - 1st part
...
llvm-svn: 107438
2010-07-01 22:33:18 +00:00
8a99b730a9
ARM function alignments were off by a power of two. svn 83242 changed
...
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer. The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.
llvm-svn: 107435
2010-07-01 22:26:26 +00:00
03bcd6ecc8
Implement the "linker_private_weak" linkage type. This will be used for
...
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.
For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
Currently only supported on Darwin platforms.
llvm-svn: 107433
2010-07-01 21:55:59 +00:00
429397529a
Do not require line number entry for undefined local variable.
...
This is a regression caused by r106792 and caught by gdb testsuite.
llvm-svn: 107430
2010-07-01 21:38:08 +00:00
0e980755d3
MC: Fix some stray hunks I didn't intend to commit.
...
llvm-svn: 107428
2010-07-01 20:48:51 +00:00
02877d6e85
MC: Pass the target instance to the AsmParser constructor.
...
llvm-svn: 107426
2010-07-01 20:41:56 +00:00
0aa4365e47
MC: Fix an error message.
...
llvm-svn: 107424
2010-07-01 20:20:01 +00:00
84f90a387d
Remove context sensitivity concerns from interprocedural-basic-aa, and
...
make it more aggressive in cases where both pointers are known to live
in the same function.
llvm-svn: 107420
2010-07-01 20:08:40 +00:00
329d202362
MC: Move COFF enumeration constants to llvm/Support/COFF.h, patch by Michael
...
Spencer!
llvm-svn: 107418
2010-07-01 20:07:24 +00:00
2b434e12cd
Debugging infomration is encoded in llvm IR using metadata. This is designed
...
such a way that debug info for symbols preserved even if symbols are
optimized away by the optimizer.
Add new special pass to remove debug info for such symbols.
llvm-svn: 107416
2010-07-01 19:49:20 +00:00
b9e2e4b762
If a named mdnode is removed then mark module as changed.
...
llvm-svn: 107412
2010-07-01 18:27:46 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
...
Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
...
llvm-svn: 107404
2010-07-01 17:08:18 +00:00
d2965c10a1
Temporarily disable on-demand fast-isel.
...
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
9dc154bcb4
reformulate CallSite::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private
...
llvm-svn: 107390
2010-07-01 10:41:37 +00:00
42b7ee15f5
Use FuncInfo's isExportedInst accessor method instead of
...
doing the work manually.
llvm-svn: 107384
2010-07-01 03:57:05 +00:00
85e02e9340
Rename CreateRegForValue to CreateReg, and change its argument
...
from a Value to a Type, because it doesn't actually care about
the Value.
llvm-svn: 107383
2010-07-01 03:55:39 +00:00
4d29fd85f9
Fast isel no longer needs DeadMachineInstrElim to clean up after it.
...
llvm-svn: 107381
2010-07-01 03:49:59 +00:00
aef3d140b7
Teach fast-isel to avoid loading a value from memory when it's already
...
available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.
llvm-svn: 107380
2010-07-01 03:49:38 +00:00
722f5fc567
Enable on-demand fast-isel.
...
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
207624edb0
Fix X86FastISel's add folding to actually work, and not fall back
...
to SelectionDAG.
llvm-svn: 107376
2010-07-01 02:58:21 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
...
llvm-svn: 107375
2010-07-01 02:33:39 +00:00
7937d5606d
Teach X86FastISel to fold constant offsets and scaled indices in
...
the same address.
llvm-svn: 107373
2010-07-01 02:27:15 +00:00
d432223163
Reapply r106422, splitting the code for materializing a value out of
...
SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.
llvm-svn: 107371
2010-07-01 01:59:43 +00:00
9576645a84
Don't use operator[] here, because it's not desirable to insert a default
...
value if the search fails.
llvm-svn: 107368
2010-07-01 01:33:21 +00:00
05166740eb
- Add AVX SSE2 Move doubleword and quadword instructions.
...
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
22fa66cf2b
80-col violation.
...
llvm-svn: 107361
2010-07-01 01:00:27 +00:00
4721ad855e
Trailing whitespace.
...
llvm-svn: 107360
2010-07-01 01:00:22 +00:00
8656a4549a
Add memory operand folding support to InlineSpiller.
...
llvm-svn: 107355
2010-07-01 00:13:04 +00:00
bde96ad23e
Add support for rematerialization to InlineSpiller.
...
llvm-svn: 107351
2010-06-30 23:03:52 +00:00
e0dfb98ea0
Use the catch-all selectors we already found when converting them to use the
...
correct catch-all value. This saves having to iterate through all of the
selectors in the program again.
llvm-svn: 107345
2010-06-30 22:49:53 +00:00
e74c78d539
lowerinvoke needs to handle aggregate function args like sjlj eh does.
...
llvm-svn: 107335
2010-06-30 22:22:59 +00:00
e8c97a7cd7
Handle array and vector typed parameters in sjljehprepare like we do
...
structs. rdar://8145832
llvm-svn: 107332
2010-06-30 22:20:38 +00:00
db735cbbab
Remove all debug info related named mdnodes.
...
llvm-svn: 107323
2010-06-30 21:29:00 +00:00
caf9b3ab7d
grammar tweak in comment.
...
llvm-svn: 107321
2010-06-30 21:27:56 +00:00
f638f4ff84
In ScalarEvolution::forgetValue, eliminate any SCEVUnknown
...
entries associated with the value being erased in the
folding set map. These entries used to be harmless, because
a SCEVUnknown doesn't store any information about its Value*,
so having a new Value allocated at the old Value's address
wasn't a problem. But now that ScalarEvolution is storing more
information about values, this is no longer safe.
llvm-svn: 107316
2010-06-30 20:21:12 +00:00
d0eacf715f
Move MOVD/MODQ code around, creating sections for each of them
...
llvm-svn: 107308
2010-06-30 18:49:10 +00:00
59e1cae377
Some fool committed without testing (or even building) first.
...
llvm-svn: 107307
2010-06-30 18:41:20 +00:00
cbcebe2950
Add AVX SSE2 mask creation and conditional store instructions
...
llvm-svn: 107306
2010-06-30 18:38:10 +00:00
c39d3497c8
Remember to track spill slot uses in VirtRegMap when inserting loads and stores.
...
LocalRewriter::runOnMachineFunction uses this information to mark dead spill
slots.
This means that InlineSpiller now also works for functions that spill.
llvm-svn: 107302
2010-06-30 18:19:08 +00:00
5c768e4915
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable
...
llvm-svn: 107300
2010-06-30 18:06:01 +00:00
c0cca7fdda
Revert the part of r107257 which introduced new logic for using
...
nsw and nuw flags from IR Instructions. On further consideration,
this isn't valid.
llvm-svn: 107298
2010-06-30 17:27:11 +00:00
945a347478
Remove an unused variable. The call to getRoot has side-effects, so
...
this could break something (but doesn't seem to).
llvm-svn: 107295
2010-06-30 17:22:28 +00:00
d079c91683
Add AVX SSE2 packed integer extract/insert instructions
...
llvm-svn: 107293
2010-06-30 17:03:03 +00:00
7b90966d4a
Rather than giving SmallPtrSetImpl a member field SmallArray which is magically
...
replaced by a bigger array in SmallPtrSet (by overridding it), instead just use a
pointer to the start of the storage, and have SmallPtrSet pass in the value to use.
This has the disadvantage that SmallPtrSet becomes bigger by one pointer. It has
the advantage that it no longer uses tricky C++ rules, and is clearly correct while
I'm not sure the previous version was. This was inspired by g++-4.6 pointing out
that SmallPtrSetImpl was writing off the end of SmallArray, which it was. Since
SmallArray is replaced with a bigger array in SmallPtrSet, the write was still to
valid memory. But it was writing off the end of the declared array type - sounds
kind of dubious to me, like it sounded dubious to g++-4.6. Maybe g++-4.6 is wrong
and this construct is perfectly valid and correctly compiled by all compilers, but
I think it is better to avoid the whole can of worms by avoiding this construct.
llvm-svn: 107285
2010-06-30 15:02:37 +00:00
647d9c9797
use ArgOperand API
...
llvm-svn: 107282
2010-06-30 13:45:50 +00:00
12ca3d9fac
use ArgOperand API
...
llvm-svn: 107280
2010-06-30 13:03:37 +00:00
f69acfe133
use ArgOperand API
...
llvm-svn: 107279
2010-06-30 12:55:46 +00:00
74470192d7
use ArgOperand API
...
llvm-svn: 107278
2010-06-30 12:42:43 +00:00
d50572802e
use ArgOperand API
...
llvm-svn: 107277
2010-06-30 12:40:35 +00:00
3390e746fa
use CallSite::arg_end instead of CallInst::op_end
...
llvm-svn: 107276
2010-06-30 12:39:23 +00:00
3abd881bea
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107275
2010-06-30 12:38:26 +00:00
743b3fd196
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand
...
llvm-svn: 107273
2010-06-30 09:19:23 +00:00
f628ecd15f
use getNumArgOperands instead of getNumOperands
...
llvm-svn: 107272
2010-06-30 09:17:53 +00:00
fe252e6fa0
use getArgOperand instead of getOperand
...
llvm-svn: 107271
2010-06-30 09:16:16 +00:00
8ae3095286
use getArgOperand instead of getOperand
...
llvm-svn: 107270
2010-06-30 09:15:28 +00:00
e9acc46f65
use getArgOperand instead of getOperand
...
llvm-svn: 107269
2010-06-30 09:14:26 +00:00
16206132b6
Improve ScalarEvolution's nsw and nuw preservation.
...
llvm-svn: 107257
2010-06-30 07:16:37 +00:00
9396b42ca4
When computing a new ConservativeResult, intersect it with
...
the old one instead of replacing it, to be more precise.
llvm-svn: 107256
2010-06-30 06:58:35 +00:00
0865966440
Rework scev-aa's basic computation so that it doesn't depend
...
on ScalarEvolution successfully folding and preserving
range information for both A-B and B-A. Now, if it gets
either one, it's sufficient.
llvm-svn: 107249
2010-06-30 06:12:16 +00:00
37f145c55b
Simplify.
...
llvm-svn: 107248
2010-06-30 06:09:46 +00:00
e82689fea2
Add AVX SSE2 integer unpack instructions
...
llvm-svn: 107246
2010-06-30 04:06:39 +00:00
ec0115c9b7
Add AVX SSE2 packed integer shuffle instructions
...
llvm-svn: 107245
2010-06-30 03:47:56 +00:00
5364655e02
Remove trailing whitespace, no functionality changes.
...
llvm-svn: 107244
2010-06-30 03:40:54 +00:00
51ceead19c
Small refactoring of SSE2 packed integer shuffle instructions
...
llvm-svn: 107243
2010-06-30 03:29:36 +00:00
be792feb8b
Add AVX SSE2 pack with saturation integer instructions
...
llvm-svn: 107241
2010-06-30 02:30:25 +00:00
2686ea4555
Add AVX SSE2 integer packed compare instructions
...
llvm-svn: 107240
2010-06-30 02:21:09 +00:00
2e2caefff9
- Add AVX form of all SSE2 logical instructions
...
- Add VEX encoding bits to x86 MRM0r-MRM7r
llvm-svn: 107238
2010-06-30 01:58:37 +00:00
c5b3109bec
Do not construct DIE for already processed MDNode.
...
llvm-svn: 107237
2010-06-30 01:40:11 +00:00
b3b89c3bc0
Use skipInstruction() as a simpler way of iterating over instructions using SrcReg
...
llvm-svn: 107234
2010-06-30 00:30:36 +00:00
08baf59da1
Use clEnumValN macro to work around keyword clash
...
llvm-svn: 107233
2010-06-30 00:24:51 +00:00
648df7bf64
Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree.
...
llvm-svn: 107228
2010-06-30 00:11:08 +00:00
f888911932
Begin implementation of an inline spiller.
...
InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.
This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.
llvm-svn: 107227
2010-06-29 23:58:39 +00:00
3f71ddfaad
Add *several* AVX integer packed binop instructions
...
llvm-svn: 107225
2010-06-29 23:47:49 +00:00
ae36b1ed42
Fix ScalarEvolution's tripcount computation for chains of loops
...
where each loop's induction variable's start value is the exit
value of a preceding loop.
llvm-svn: 107224
2010-06-29 23:43:06 +00:00
3632171750
Revert r107205 and r107207.
...
llvm-svn: 107215
2010-06-29 22:34:52 +00:00
be30551600
Print InlinedAt location.
...
llvm-svn: 107214
2010-06-29 22:29:15 +00:00
e34471bb31
Add another bswap idiom that isn't matched.
...
llvm-svn: 107213
2010-06-29 22:22:22 +00:00
7fee95a38e
Move SSE2 Packed Integer instructions around, and create specific sections for each of them
...
llvm-svn: 107211
2010-06-29 22:12:16 +00:00
c728518bfe
Print InlinedAt location.
...
llvm-svn: 107208
2010-06-29 21:51:32 +00:00
ba21eb8054
Add AVX Move Aligned/Unaligned packed integers
...
llvm-svn: 107206
2010-06-29 21:25:12 +00:00
1767723dbe
Introducing the "linker_weak" linkage type. This will be used for Objective-C
...
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:
.globl l_objc_msgSend_fixup_alloc
.weak_definition l_objc_msgSend_fixup_alloc
.section __DATA, __objc_msgrefs, coalesced
.align 3
l_objc_msgSend_fixup_alloc:
.quad _objc_msgSend_fixup
.quad L_OBJC_METH_VAR_NAME_1
This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".
llvm-svn: 107205
2010-06-29 21:24:00 +00:00
30689a3a7f
Add AVX ld/st XCSR register.
...
Add VEX encoding bits for MRMXm x86 form
llvm-svn: 107204
2010-06-29 20:35:48 +00:00
24bc1b5b2f
Do not hardcode DW_AT_stmt_list value.
...
Inspired by Artur Pietrek.
llvm-svn: 107202
2010-06-29 20:17:53 +00:00
be157b0ea8
Add support for encoding VDUP (ARM core register) instructions.
...
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
dadea5b178
Fix the handling of partial redefines in the fast register allocator.
...
A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.
This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.
llvm-svn: 107193
2010-06-29 19:15:30 +00:00
d91d5bfc95
Fix a register scavenger crash when dealing with undefined subregs.
...
The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.
llvm-svn: 107189
2010-06-29 18:42:49 +00:00
a4575f5b31
Add AVX non-temporal stores
...
llvm-svn: 107178
2010-06-29 18:22:01 +00:00
1be9e7c0b6
Fix whitespace style.
...
llvm-svn: 107175
2010-06-29 18:12:34 +00:00
049f4ffab1
Move non-temporal movs to their own section
...
llvm-svn: 107168
2010-06-29 17:42:37 +00:00
ab0819e10d
Add support for encoding NEON VMOV (from core register to scalar) instructions.
...
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.
llvm-svn: 107167
2010-06-29 17:34:07 +00:00
21a9433e9e
Add sqrt, rsqrt and rcp AVX instructions
...
llvm-svn: 107166
2010-06-29 17:26:30 +00:00
5bee07ec68
skip dbg_value instructions
...
llvm-svn: 107154
2010-06-29 16:55:24 +00:00
83b993a977
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
...
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
llvm-svn: 107147
2010-06-29 16:25:11 +00:00
eab748d409
use ArgOperand API
...
llvm-svn: 107145
2010-06-29 16:17:26 +00:00
17f1ca8793
Return Changed. This required setting Changed if dbg metadata
...
is stripped off. Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.
llvm-svn: 107142
2010-06-29 14:52:10 +00:00
83d1dd637a
It seems clear that this should return Changed.
...
llvm-svn: 107141
2010-06-29 14:49:35 +00:00
38a7d7cbc3
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
...
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
llvm-svn: 107140
2010-06-29 14:02:34 +00:00
d34bb4e9b0
getMachineBasicBlockAddress returns a uintptr_t - don't truncate
...
to unsigned only to extend back to a pointer sized value on the
next line.
llvm-svn: 107139
2010-06-29 13:34:20 +00:00
a85a90773c
The variable ValueSize is set to 1 on both code paths, and then
...
ignored! Remove it.
llvm-svn: 107138
2010-06-29 13:30:08 +00:00
1245e4c07d
The variable "Value" is carefully set to Layout.getSymbolAddress,
...
but then not actually used - maybe a bug? Remove the variable.
llvm-svn: 107137
2010-06-29 13:26:33 +00:00
5667a08468
Remove unused calls to Lexer.getLoc and the pointless variable HasFillExpr.
...
llvm-svn: 107136
2010-06-29 13:24:40 +00:00
193bb1ee6a
Remove pointless variable LastDef.
...
llvm-svn: 107135
2010-06-29 13:23:22 +00:00
257eba4df7
Remove unused variable Loc and pointless variables unified_syntax
...
and thumb_mode.
llvm-svn: 107133
2010-06-29 13:04:35 +00:00
e73d64c2cf
use ArgOperand APIs
...
llvm-svn: 107132
2010-06-29 13:03:46 +00:00
78ad27ca2b
Remove an unused and a pointless variable.
...
llvm-svn: 107131
2010-06-29 13:00:29 +00:00
67bfa9d109
Remove pointless and unused variables.
...
llvm-svn: 107130
2010-06-29 12:48:49 +00:00
eec74583ca
encode operand initializations (at fixed index)
...
in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.
llvm-svn: 107129
2010-06-29 11:41:38 +00:00
67aa21d7b5
Remove a pointless variable.
...
llvm-svn: 107128
2010-06-29 11:39:45 +00:00
6d28e73acc
Remove initialized but otherwise unused variables.
...
llvm-svn: 107127
2010-06-29 11:22:26 +00:00
80b7bc042a
Use a more obvious way to avoid compiling functions which are only used when XDEBUG is enabled.
...
llvm-svn: 107125
2010-06-29 10:03:11 +00:00
b1adb88d05
Jump through some silly hoops to make GCC accept that a function may not always
...
be called.
llvm-svn: 107124
2010-06-29 06:46:00 +00:00
b59dd8f10a
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
...
llvm-svn: 107122
2010-06-29 05:38:36 +00:00
0c30739cbb
Change if-cvt options to something that actually as useable.
...
llvm-svn: 107121
2010-06-29 05:37:59 +00:00
907673c48d
When processing loops for scheduling latencies (used for live outs on loop
...
back-edges), make sure not to include dbg_value instructions in the count.
Closing in on the end of rdar://7797940
llvm-svn: 107119
2010-06-29 04:48:13 +00:00
90db61d638
Just as its not safe to blindly transfer the nsw bit from an add
...
instruction to an add scev, it's not safe to blindly transfer the
inbounds flag from a gep instruction to an nsw on the scev for the
gep.
llvm-svn: 107117
2010-06-29 01:41:41 +00:00
de736a6494
Refactoring of arithmetic instruction classes with unary operator
...
llvm-svn: 107116
2010-06-29 01:33:09 +00:00
c1eccbc468
When no memoperands are present, assume unaligned, volatile.
...
llvm-svn: 107114
2010-06-29 01:13:07 +00:00
1e5da550e5
Reapply my if-conversion cleanup from svn r106939 with fixes.
...
There are 2 changes relative to the previous version of the patch:
1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch. Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).
The change relative to the previous patch is:
@@ -1036,10 +1036,6 @@
IterIfcvt = false;
}
- // RemoveExtraEdges won't work if the block has an unanalyzable branch,
- // which is typically the case for IfConvertSimple, so explicitly remove
- // CvtBBI as a successor.
- BBI.BB->removeSuccessor(CvtBBI->BB);
RemoveExtraEdges(BBI);
// Update block info. BB can be iteratively if-converted.
2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised. The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond. I added the following change to check for
that:
@@ -1276,7 +1276,18 @@
// tail, add a unconditional branch to it.
if (TailBB) {
BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
- if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+ bool CanMergeTail = !TailBBI.HasFallThrough;
+ // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+ // check if there are any other predecessors besides those.
+ unsigned NumPreds = TailBB->pred_size();
+ if (NumPreds > 1)
+ CanMergeTail = false;
+ else if (NumPreds == 1 && CanMergeTail) {
+ MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+ if (*PI != BBI1->BB && *PI != BBI2->BB)
+ CanMergeTail = false;
+ }
+ if (CanMergeTail) {
MergeBlocks(BBI, TailBBI);
TailBBI.IsDone = true;
} else {
With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.
llvm-svn: 107110
2010-06-29 00:55:23 +00:00
0824affeff
Add an Intraprocedural form of BasicAliasAnalysis, which aims to
...
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.
llvm-svn: 107109
2010-06-29 00:50:39 +00:00
d6a091a4d4
Described the missing AVX forms of SSE2 convert instructions
...
llvm-svn: 107108
2010-06-29 00:36:02 +00:00
3d12ff797b
Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
...
the same as ARM except that the condition code field is always set to ARMCC::AL.
llvm-svn: 107107
2010-06-29 00:26:13 +00:00
269a89fd3a
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
...
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
llvm-svn: 107097
2010-06-28 23:40:25 +00:00
4469a892b4
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
...
of the Subtarget.
llvm-svn: 107086
2010-06-28 22:23:17 +00:00
1de21ec498
Use DW_FORM_addr for DW_AT_entry_pc.
...
llvm-svn: 107085
2010-06-28 22:22:47 +00:00
17feb07c53
In asm's, output operands with matching input constraints
...
have to be registers, per gcc documentation. This affects
the logic for determining what "g" should lower to. PR 7393.
A couple of existing testcases are affected.
llvm-svn: 107079
2010-06-28 22:09:45 +00:00
e233dda2e2
Added the darwin .secure_log_unique and .secure_log_reset directives.
...
llvm-svn: 107077
2010-06-28 21:45:58 +00:00
e697a6f24f
Constant fold x == undef to undef.
...
llvm-svn: 107074
2010-06-28 21:30:07 +00:00
f31c004666
tidy up style. no functional change.
...
llvm-svn: 107073
2010-06-28 21:29:17 +00:00
7c34ece501
Fix Value::stripPointerCasts and BasicAA to avoid trouble on
...
code in unreachable blocks, which have have use-def cycles.
This fixes PR7514.
llvm-svn: 107071
2010-06-28 21:16:52 +00:00
544317dfda
Refactor encoding function for NEON 1-register with modified immediate format.
...
llvm-svn: 107070
2010-06-28 21:16:30 +00:00
584387d5e3
Support Thumb mode encoding of NEON instructions.
...
llvm-svn: 107068
2010-06-28 21:12:19 +00:00
0a5bb081cc
Reduce indentation via early exit. NFC.
...
llvm-svn: 107067
2010-06-28 21:08:32 +00:00
d10b2af260
Include inlined function in list of processed subprograms.
...
llvm-svn: 107065
2010-06-28 20:53:04 +00:00
ee6e29aa72
new, no longer brain-dead, r106907
...
llvm-svn: 107060
2010-06-28 20:26:00 +00:00
ffd628ec0a
After physreg coalescing, physical registers might not have live ranges where
...
you would expect.
Don't assert on that case, just give up.
This fixes PR7513.
llvm-svn: 107046
2010-06-28 19:39:57 +00:00
0d94d7af78
Add more special treatment for inline asm in RegAllocFast.
...
When an instruction has tied operands and physreg defines, we must take extra
care that the tied operands conflict with neither physreg defs nor uses.
The special treatment is given to inline asm and instructions with tied operands
/ early clobbers and physreg defines.
This fixes PR7509.
llvm-svn: 107043
2010-06-28 18:34:34 +00:00
7f103a2653
Fix thinko.
...
llvm-svn: 107042
2010-06-28 18:33:48 +00:00
51f2908328
Pull in the libCrashReporterClient.a information with a warning comment.
...
Remove library check and regenerate configure.
llvm-svn: 107028
2010-06-28 18:25:51 +00:00
f3b2db68c6
Preserve deleted function's local variables' debug info.
...
Radar 8122864.
llvm-svn: 107027
2010-06-28 18:25:03 +00:00
5b1370ee80
use ArgOperand API
...
llvm-svn: 107017
2010-06-28 16:50:57 +00:00
e23efeef10
use ArgOperand API
...
llvm-svn: 107016
2010-06-28 16:45:00 +00:00
18c5bae727
employ CallInst::ArgOffset (for now)
...
llvm-svn: 107015
2010-06-28 16:43:57 +00:00
cd09869dfc
simplify: we have solid argument iterator range
...
llvm-svn: 107014
2010-06-28 16:40:52 +00:00
875a296011
Generalize AAEval so that it can be used both per-function and
...
interprocedurally. Note that as of this writing, existing alias
analysis passes are not prepared to be used interprocedurally.
llvm-svn: 107013
2010-06-28 16:01:37 +00:00
b8c058cbb0
Revert r106907, "make sure to handle dbg_value instructions in the middle of the
...
block, not...", it caused a bunch of nightly test regressions.
llvm-svn: 107009
2010-06-28 15:47:17 +00:00
2dd4307e45
use setArgOperand
...
llvm-svn: 107004
2010-06-28 12:31:35 +00:00
ec60adf161
use CallInst::ArgOffset
...
llvm-svn: 107003
2010-06-28 12:30:07 +00:00
2de43a7c5c
use ArgOperand API and CallInst::ArgOffset
...
llvm-svn: 107002
2010-06-28 12:29:20 +00:00
4300fc77ae
use cached value
...
llvm-svn: 107000
2010-06-28 11:20:42 +00:00
fb6f22f010
Remove dead code.
...
llvm-svn: 106990
2010-06-28 05:59:13 +00:00
f7869a4b81
Use named MDNode, llvm.dbg.sp, to collect subprogram info. This will be used to emit local variable's debug info of deleted functions.
...
llvm-svn: 106989
2010-06-28 05:53:08 +00:00
7ea5fc0794
minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.
...
llvm-svn: 106988
2010-06-28 04:27:01 +00:00
81170d23de
Do not forget last element, function, while creating Subprogram definition MDNode from subprogram declare MDNode.
...
llvm-svn: 106985
2010-06-27 21:04:31 +00:00
25a843fcd2
minor cleanup to SROA: when lowering type unsafe accesses to
...
large integers, the first inserted value would always create
an 'or X, 0'. Even though this is trivially zapped by
instcombine, don't bother creating this pointless instruction.
llvm-svn: 106979
2010-06-27 07:58:26 +00:00
2041abd958
When splitting a VAARG, remember its alignment.
...
This produces terrible but correct code.
llvm-svn: 106952
2010-06-26 18:22:20 +00:00
418e64a385
Revert my if-conversion cleanup since it caused a bunch of nightly test
...
regressions.
--- Reverse-merging r106939 into '.':
U test/CodeGen/Thumb2/thumb2-ifcvt3.ll
U lib/CodeGen/IfConversion.cpp
llvm-svn: 106951
2010-06-26 17:47:06 +00:00
3a5cb69cb8
Fix PR7328: when turning a tail recursion into a loop, need to preserve
...
the returned value after the tail call if it differs from other return
values. The optimal thing to do would be to introduce a phi node for
the return value, but for the moment just fix the miscompile.
llvm-svn: 106947
2010-06-26 12:53:31 +00:00
7d4038dd88
use ArgOperand API
...
llvm-svn: 106946
2010-06-26 12:17:21 +00:00
c2ac8c4261
use ArgOperand API
...
llvm-svn: 106945
2010-06-26 12:09:10 +00:00
83205af3fa
use ArgOperand API
...
llvm-svn: 106944
2010-06-26 11:51:52 +00:00
a000002428
VNInfos don't need to be destructed anymore.
...
llvm-svn: 106943
2010-06-26 11:30:59 +00:00
e9afee2910
resort to ArgOperand API
...
llvm-svn: 106942
2010-06-26 09:35:09 +00:00
8cfa7713e9
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
...
llvm-svn: 106940
2010-06-26 04:36:50 +00:00
c72da6bb56
Clean up some problems with extra CFG edges being introduced during
...
if-conversion. The RemoveExtraEdges function doesn't work for blocks that
end with unanalyzable branches, so in those cases, the "extra" edges must
be explicitly removed. The CopyAndPredicateBlock and MergeBlocks methods
can also avoid copying successor edges due to branches that have already
been removed. The latter case is especially helpful when MergeBlocks is
called for handling "diamond" if-conversions, where otherwise you can end
up with some weird intermediate states in the CFG. Unfortunately I've
been unable to find cases where this cleanup actually makes a significant
difference in the code. There is one test where we manage to remove an
empty block at the end of a function. Radar 6911268.
llvm-svn: 106939
2010-06-26 04:27:33 +00:00
0248da9db4
Add support for encoding NEON VMOV (from scalar to core register) instructions.
...
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
b71233f34d
It's now possible to run code placement pass for ARM.
...
llvm-svn: 106935
2010-06-26 01:52:05 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
...
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
...
llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
...
"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
...
llvm-svn: 106917
2010-06-25 23:47:23 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
...
Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
83651094ad
Reapply r106896:
...
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
acbdf53db4
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
llvm-svn: 106908
2010-06-25 23:14:54 +00:00
c34befc78f
make sure to handle dbg_value instructions in the middle of the block, not
...
just at the head, when doing diamond if-conversion. rdar://7797940
llvm-svn: 106907
2010-06-25 23:05:46 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
...
llvm-svn: 106906
2010-06-25 23:04:29 +00:00
55d738e2e1
Don't track kills in VNInfo. Use interval ends instead.
...
The VNInfo.kills vector was almost unused except for all the code keeping it
updated. The few places using it were easily rewritten to check for interval
ends instead.
The two new methods LiveInterval::killedAt and killedInRange are replacements.
This brings us down to 3 independent data structures tracking kills.
llvm-svn: 106905
2010-06-25 22:53:05 +00:00
02b184de5b
Change if-conversion block size limit checks to add some flexibility.
...
llvm-svn: 106901
2010-06-25 22:42:03 +00:00
2530ca0647
Add support for encoding 3-register NEON instructions, and fix
...
emitNEON2RegInstruction's handling of 2-address operands.
llvm-svn: 106900
2010-06-25 22:40:46 +00:00
fb9712bdae
In GenerateReassociations, don't bother thinking about individual
...
SCEVUnknown values which are loop-variant, as LSR can't do anything
interesting with these values in any case. This fixes very slow compile
times on loops which have large numbers of such values.
llvm-svn: 106897
2010-06-25 22:32:18 +00:00
a34d9b6d84
Add several AVX MOV flavors
...
Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
5c0f85c7dd
Collect debug info for optimized variables of inlined functions.
...
llvm-svn: 106895
2010-06-25 22:07:34 +00:00
8a6deefec6
80 column and typo fix
...
llvm-svn: 106894
2010-06-25 22:02:28 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
...
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
e70c8b150b
Add support for encoding 2-register NEON instructions.
...
llvm-svn: 106891
2010-06-25 21:17:19 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
...
llvm-svn: 106886
2010-06-25 21:05:35 +00:00
574f68f815
Fix indentation.
...
llvm-svn: 106881
2010-06-25 20:54:44 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
...
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
ef7acd9a24
We should remove the live range from the destination register only if *all* defs
...
are dead, not just the def of this register. I.e., a register could be dead, but
it's subreg isn't.
Testcase to follow with a subsequent patch.
llvm-svn: 106878
2010-06-25 20:42:55 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
...
llvm-svn: 106877
2010-06-25 20:29:27 +00:00
62d1403a03
More SSE refactoring, this time with different types of MOVs
...
llvm-svn: 106876
2010-06-25 20:22:12 +00:00
89dd42af31
Eliminate a redundant FoldingSet lookup.
...
llvm-svn: 106872
2010-06-25 18:47:08 +00:00
ba3ece6f27
IT instructions are considered to be scheduling hazards, but are scheduled
...
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
llvm-svn: 106871
2010-06-25 18:43:14 +00:00
e76c0b13b9
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
...
llvm-svn: 106867
2010-06-25 18:06:22 +00:00
2ac3b9cbd4
Cosmetic.
...
llvm-svn: 106865
2010-06-25 17:41:07 +00:00
58e6c2eded
Rewrite MemoryBuffer::getSTDIN to use read(2) and a SmallVector buffer.
...
llvm-svn: 106856
2010-06-25 16:07:18 +00:00
2dc70bea54
Remove variables which are assigned to but for which the value
...
is not used. Spotted by gcc-4.6.
llvm-svn: 106854
2010-06-25 14:48:39 +00:00
948dd57945
Bring back the empty vector workaround I removed in r106839. Looks like MSVC needs it.
...
llvm-svn: 106841
2010-06-25 12:51:01 +00:00
ce2a92220f
Tweak MemoryBuffer to allocate the class itself, the name and possibly the
...
buffer in the same chunk of memory.
2 less mallocs for every uninitialized MemoryBuffer and 1 less malloc for every
MemoryBuffer pointing to a memory range translate into 20% less mallocs on
clang -cc1 -Eonly Cocoa_h.m.
llvm-svn: 106839
2010-06-25 11:50:40 +00:00
b890fc8023
use ArgOperand accessors
...
and CallInst for getting hold
of the intrinsic's arguments
simplify along the way (at least for me this is much more legible now)
Bill, Baldrick or Anton, please review\!
llvm-svn: 106838
2010-06-25 11:25:30 +00:00
7dd3afdff3
use ArgOperand API (the simple part)
...
llvm-svn: 106837
2010-06-25 09:44:37 +00:00
eba0be7dc9
use ArgOperand API
...
llvm-svn: 106836
2010-06-25 09:38:13 +00:00
41b81ee2fb
use ArgOperand API
...
llvm-svn: 106835
2010-06-25 09:36:23 +00:00
ed9ae7bf21
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106833
2010-06-25 09:03:52 +00:00
b5874dea6e
use ArgOperand API and CallSite to access arguments of CallInst
...
llvm-svn: 106829
2010-06-25 08:48:19 +00:00
e4eed709d4
use ArgOperand API
...
llvm-svn: 106828
2010-06-25 08:24:59 +00:00
f6207e0a80
prune an include
...
llvm-svn: 106827
2010-06-25 08:16:50 +00:00
e3ba486c9f
use ArgOperand API (one more hunk I could split)
...
llvm-svn: 106825
2010-06-25 07:58:41 +00:00
5f3e656a1b
use ArgOperand API (some hunks I could split)
...
llvm-svn: 106824
2010-06-25 07:57:14 +00:00
07e9284c75
use ArgOperand API; tighten type of handleFreeWithNonTrivialDependency to be able to use isFreeCall whithout a cast or new overload
...
llvm-svn: 106823
2010-06-25 07:40:32 +00:00
07aead2f8d
Add missing ARM and Thumb data layout info for vector types.
...
Radar 8128745.
llvm-svn: 106820
2010-06-25 04:41:08 +00:00
eadbf9732f
Reduce indentation.
...
llvm-svn: 106819
2010-06-25 04:12:31 +00:00
e9eaaa91d8
Fix a case where an earlyclobber operand of an asm
...
is reused as an input. PR 4118. Testcase is too big,
as usual with bugs in this area, but there's one in
the PR.
llvm-svn: 106816
2010-06-25 00:49:43 +00:00
cbdcce6478
Add some AVX convert instructions
...
llvm-svn: 106815
2010-06-25 00:39:30 +00:00
889ab7d158
Make sure all eliminated kills are removed from VNInfo lists.
...
This fixes PR7479 and PR7485. The test cases from those PRs are big, so not
included. However, PR7485 comes from self hosting on FreeBSD, so we will surely
hear about any regression.
llvm-svn: 106811
2010-06-24 23:57:35 +00:00
5f0bf64c0c
Add some comments.
...
llvm-svn: 106809
2010-06-24 23:41:59 +00:00
447735aa98
Refactoring of SSE convert intrinsics
...
llvm-svn: 106808
2010-06-24 23:37:07 +00:00
9a2f0473b2
Teach EmitLiveInCopies to omit copies for unused virtual registers,
...
and to clean up unused incoming physregs from the live-in list.
llvm-svn: 106805
2010-06-24 22:23:02 +00:00
78827d1952
Refactoring of SSE conversion instructions
...
llvm-svn: 106804
2010-06-24 22:22:21 +00:00
6b6b605917
Refactor SSE cmp intrinsics and declare the same for AVX
...
llvm-svn: 106796
2010-06-24 22:04:40 +00:00
2d3c490026
It's possible that a flag is added to the SDNode that points back to the
...
original SDNode. This is badness. Also, this function allows one SDNode to point
multiple flags to another SDNode. Badness as well.
llvm-svn: 106793
2010-06-24 22:00:37 +00:00
c657c621b7
DBG_VALUE machine instruction pointing to undefined register for a variable justify a separate scope if the variable is inlined function's argument.
...
Radar 8122864.
llvm-svn: 106792
2010-06-24 21:51:19 +00:00
2b87d44c5d
Don't return a std::vector in the Spiller interface, but take a reference to a
...
vector instead. This avoids needless copying and allocation.
Add documentation.
llvm-svn: 106788
2010-06-24 20:54:29 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
...
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
9b659142a6
Remove the now unused LiveIntervals::getVNInfoSourceReg().
...
This method was always a bit too simplistic for the real world. It didn't really
deal with subregisters and such.
llvm-svn: 106781
2010-06-24 20:18:15 +00:00
487ed997d0
Teach AdjustCopiesBackFrom to also use CoalescerPair to identify compatible copies.
...
llvm-svn: 106780
2010-06-24 20:16:00 +00:00
5ad5226c58
Disallow matching "i" constraint to symbol addresses when
...
address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
llvm-svn: 106779
2010-06-24 20:14:51 +00:00
7f894d8fdc
Remove the -fast-spill option.
...
This code path has never really been used, and we are going to be handling
spilling through the Spiller interface in the future.
llvm-svn: 106777
2010-06-24 19:56:08 +00:00
c26e2f4b70
Oops. IT block formation pass needs to be run at any optimization level.
...
llvm-svn: 106775
2010-06-24 19:10:14 +00:00
3f0e992af1
Loosen up the requirements in the Horrible Hack(tm) to include all selectors
...
which don't have a catch-all associated with them not just clean-ups. This fixes
the SingleSource/Benchmarks/Shootout-C++/except.cpp testcase that broke because
of my change r105902.
llvm-svn: 106772
2010-06-24 18:49:10 +00:00
246c41d93e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
...
llvm-svn: 106770
2010-06-24 18:20:04 +00:00
45230239e4
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
This second attempt fixes some crashes that only occurred Linux.
llvm-svn: 106769
2010-06-24 18:15:01 +00:00
4143e9deeb
Add an exports file for the Hello example plugin.
...
llvm-svn: 106768
2010-06-24 17:36:51 +00:00
a612d7c012
Print the LSBs of a SlotIndex symbolically using letters referring to the
...
[L]oad, [u]se, [d]ef, or [S]tore slots.
This makes it easier to see if two indices refer to the same instruction,
avoiding mental mod 4 calculations.
llvm-svn: 106766
2010-06-24 17:31:07 +00:00
8a84cd57ae
Simplify this code; switch lowering shouldn't produce cases
...
which trivially fold away.
llvm-svn: 106765
2010-06-24 17:08:31 +00:00
963b1c142e
A few minor micro-optimizations.
...
llvm-svn: 106764
2010-06-24 16:57:52 +00:00
47ddf76d89
Teach getExactSDiv to evaluate x/1 to x up front, as it's a common
...
enough special case, and it theoretically allows more folding because
it works even when x is unanalyzable.
llvm-svn: 106763
2010-06-24 16:51:25 +00:00
279e55fb2e
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
...
form so they can be narrowed to 16-bit instructions.
llvm-svn: 106762
2010-06-24 16:50:20 +00:00
5235cc2c25
Don't try to preserve pointer types in SCEVConstants; the old code
...
was over-complicated.
llvm-svn: 106760
2010-06-24 16:47:03 +00:00
ab5422200b
Fix copy+pasto issues in isMulSExtable.
...
llvm-svn: 106759
2010-06-24 16:45:11 +00:00
3ace9f4e3d
Make the trunc code consistent with the zext and sext code in its
...
handling of pointer types.
llvm-svn: 106757
2010-06-24 16:33:38 +00:00
b377e2828d
Add overloads for getFile and getFileOrSTDIN which take a const char *
...
instead of a StringRef, avoiding the need to copy the string in the
common case.
llvm-svn: 106754
2010-06-24 16:25:50 +00:00
3b2b46a700
Be more strict about subreg-to-subreg copies in CoalescerPair.
...
Also keep track of the original DstREg before subregister adjustments.
llvm-svn: 106753
2010-06-24 16:19:28 +00:00
7ccec09252
use ArgOperand API
...
llvm-svn: 106752
2010-06-24 16:11:44 +00:00
53ccab7d1c
Verify that VNI kills are pointing to existing instructions.
...
In this case it is essential that the kill is real because the spiller will
decide to omit a spill if it thinks there is a later kill.
llvm-svn: 106751
2010-06-24 15:56:59 +00:00
a6d75e2cf7
use (even more, still) ArgOperand API
...
llvm-svn: 106750
2010-06-24 15:51:11 +00:00
463f26b4be
Eliminate the other half of the BRCOND optimization, and update
...
as many tests as possible.
llvm-svn: 106749
2010-06-24 15:24:03 +00:00
df6b33e778
Eliminate the first have of the optimization which eliminates BRCOND
...
when the condition is constant. This optimization shouldn't be
necessary, because codegen shouldn't be able to find dead control
paths that the IR-level optimizer can't find. And it's undesirable,
because it encourages bugpoint to leave "br i1 false" branches
in its output. And it wasn't updating the CFG.
I updated all the tests I could, but some tests are too reduced
and I wasn't able to meaningfully preserve them.
llvm-svn: 106748
2010-06-24 15:04:11 +00:00
218f5541b2
use ArgOperand API and CallSite for arg range; add necessary casts and perform some cosmetics
...
llvm-svn: 106747
2010-06-24 14:42:01 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
...
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
5aafdf1e43
use ArgOperand API and CallSite for arg range
...
llvm-svn: 106745
2010-06-24 14:13:36 +00:00
0a136c9b53
use (even more) ArgOperand API
...
llvm-svn: 106744
2010-06-24 13:54:33 +00:00
590d95ed18
use ArgOperand API
...
llvm-svn: 106743
2010-06-24 13:42:49 +00:00
589a0b950a
use ArgOperand API
...
llvm-svn: 106740
2010-06-24 12:58:35 +00:00
7943017490
use ArgOperand API
...
llvm-svn: 106737
2010-06-24 12:35:13 +00:00
75f6943c95
use ArgOperand API, also tighten the type of visitFree to make this work out smoothly
...
llvm-svn: 106736
2010-06-24 12:21:15 +00:00
91f9589057
use ArgOperand API; introduce downcasted pointers into scope to facilitate this
...
llvm-svn: 106734
2010-06-24 12:03:56 +00:00
e2f482ca0b
use ArgOperand API
...
llvm-svn: 106731
2010-06-24 10:42:46 +00:00
2d958d4db5
use ArgOperand API
...
llvm-svn: 106730
2010-06-24 10:17:17 +00:00
5bcaa55761
use callsite to obtain all arguments
...
llvm-svn: 106729
2010-06-24 10:04:07 +00:00
42f620cc55
use callsite to obtain all arguments
...
llvm-svn: 106728
2010-06-24 09:56:43 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
...
rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
c4e84309c4
more cleanups
...
llvm-svn: 106724
2010-06-24 07:18:14 +00:00
056fd06c5f
reduce indentation
...
llvm-svn: 106723
2010-06-24 07:16:25 +00:00
cfed96a410
fix breakage from r98938 by correctly marking msp430 calls as variadic.
...
Patch by Ben Ransford!
llvm-svn: 106722
2010-06-24 06:46:50 +00:00
c3e291c560
Fix a bug in the code which determines when it's safe to use the
...
bt instruction, which was exposed by r106263.
llvm-svn: 106718
2010-06-24 02:07:59 +00:00
fa6ce139a9
Add a couple more quick comments.
...
llvm-svn: 106717
2010-06-24 02:07:57 +00:00
0695e09b09
Optimize the "bit test" code path for switch lowering in the
...
case where the bit mask has exactly one bit.
llvm-svn: 106716
2010-06-24 02:06:24 +00:00
dbb58d2974
Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."
...
Whiny buildbots.
llvm-svn: 106710
2010-06-24 00:52:22 +00:00
0f60709f0e
use getNumArgOperands
...
llvm-svn: 106709
2010-06-24 00:48:48 +00:00
4a39b84a9d
use ArgOperand API
...
llvm-svn: 106707
2010-06-24 00:44:01 +00:00
0dc3c2d37e
Use ValueMap instead of DenseMap.
...
The ValueMapper used by various cloning utility maps MDNodes also.
llvm-svn: 106706
2010-06-24 00:33:28 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
...
llvm-svn: 106705
2010-06-24 00:32:06 +00:00
6af02a6f69
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
...
llvm-svn: 106702
2010-06-24 00:15:50 +00:00
f38e6720cc
Replace a big gob of old coalescer logic with the new CoalescerPair class.
...
CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.
llvm-svn: 106701
2010-06-24 00:12:39 +00:00
d8dedee96d
Use available typedef for " DenseMap<const Value*, Value*>".
...
llvm-svn: 106699
2010-06-24 00:00:42 +00:00
b8f11de105
Cosmetic change.
...
Do not use "ValueMap" as a name for a local variable or an argument.
llvm-svn: 106698
2010-06-23 23:55:51 +00:00
1abbde3103
use ArgOperand accessors
...
llvm-svn: 106697
2010-06-23 23:38:07 +00:00
f470747a36
We are missing opportunites to use ldm. Take code like this:
...
void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
llvm-svn: 106693
2010-06-23 23:00:16 +00:00
253c6bf366
use the new isFreeCall API and ArgOperand accessors
...
llvm-svn: 106692
2010-06-23 22:48:06 +00:00
5f5a864539
minor enhancement to llvm::isFreeCall API: return CallInst; no functional change
...
llvm-svn: 106686
2010-06-23 21:51:12 +00:00
ad7884ad98
use ArgOperand getters
...
llvm-svn: 106685
2010-06-23 21:41:47 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
...
llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
...
llvm-svn: 106678
2010-06-23 21:10:57 +00:00
5fed9b7c6c
Update according to feedback.
...
llvm-svn: 106677
2010-06-23 20:49:35 +00:00
360d6fe299
Add AVX SHUF{PS,PD}{rr,rm} instructions
...
llvm-svn: 106672
2010-06-23 20:07:15 +00:00
337e8db712
Add support for the x86 instructions "pusha" and "popa".
...
llvm-svn: 106671
2010-06-23 20:00:58 +00:00
d24c66b4a3
Do not do tail calls to external symbols. If the
...
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this. 8120438.
If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.
llvm-svn: 106662
2010-06-23 18:52:34 +00:00
a136521a17
MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
...
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.
llvm-svn: 106643
2010-06-23 18:16:24 +00:00
4df321b7ad
Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
...
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
6f71039fa4
The generic DAG combiner can now fold atomic fences when needed, so switch
...
to using that.
llvm-svn: 106633
2010-06-23 16:25:07 +00:00
a8ea498171
When using libcall expansions for the atomic intrinsics, the explicit
...
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.
llvm-svn: 106631
2010-06-23 16:08:49 +00:00
b58c08b0ba
Some targets don't require the fencing MEMBARRIER instructions surrounding
...
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.
llvm-svn: 106630
2010-06-23 16:07:42 +00:00
731ea71f59
Add a few VNInfo data structure checks.
...
llvm-svn: 106627
2010-06-23 15:34:36 +00:00
4d18165f82
use ArgOperand accessors
...
llvm-svn: 106626
2010-06-23 13:56:57 +00:00
c9a9251844
use ArgOperand accessors
...
llvm-svn: 106623
2010-06-23 13:09:06 +00:00
e54065394e
use helper to neatly access arguments
...
llvm-svn: 106622
2010-06-23 08:45:32 +00:00
3d6e2c6335
Update uses, defs, and comments for darwin tls patterns.
...
llvm-svn: 106621
2010-06-23 08:01:49 +00:00
ef5a4383ad
Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.
...
Conflicts:
lib/CodeGen/MachineSink.cpp
llvm-svn: 106614
2010-06-23 00:48:25 +00:00
7f85520644
Get the addend correct for i386 pic.
...
Thanks Daniel!
llvm-svn: 106608
2010-06-22 23:51:47 +00:00
75c6b0bb1f
Replace ScalarEvolution's private copy of getLoopPredecessor
...
with LoopInfo's public copy.
llvm-svn: 106603
2010-06-22 23:43:28 +00:00
1e13c17a55
Add AVX compare packed instructions
...
llvm-svn: 106600
2010-06-22 23:37:59 +00:00
9ad629367d
Revert 106592 for now. It causes clang-selfhost build failure.
...
llvm-svn: 106598
2010-06-22 23:29:55 +00:00
1081f1a0f5
Fix OptimizeMax to handle an odd case where one of the max operands
...
is another max which folds. This fixes PR7454.
llvm-svn: 106594
2010-06-22 23:07:13 +00:00
535aa8ea91
Reapply support for AVX unpack and interleave instructions, with
...
testcases this time.
llvm-svn: 106593
2010-06-22 23:02:38 +00:00
87f75f75be
If a metadata operand is seeded in value map and the metadata should also be seeded in value map. This is not limited to function local metadata.
...
Failure to seed metdata in such cases causes troubles when in a cloned module, metadata from a new module refers to values in old module. Usually this results in mysterious bugpoint crashes. For example,
Checking to see if we can delete global inits: Unknown constant!
UNREACHABLE executed at /d/g/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp:904!
llvm-svn: 106592
2010-06-22 22:53:21 +00:00
e43c6487da
While cloning a module, clone metadata attached with instructions.
...
llvm-svn: 106591
2010-06-22 22:50:42 +00:00
1a890f9dc0
Add AVX MOV{SS,SD}{rr,rm} instructions
...
llvm-svn: 106588
2010-06-22 22:38:56 +00:00
8ce69cd95a
Fix the formatting of the switch statement and add a missing break.
...
llvm-svn: 106586
2010-06-22 22:16:17 +00:00
1023f6bd98
Also convert SUBREG_TO_REG to a KILL when relevant, like the other subreg
...
instructions.
This does not affect codegen much because SUBREG_TO_REG is only used by X86 and
X86 does not use the register scavenger, but it prevents verifier errors.
llvm-svn: 106583
2010-06-22 22:11:07 +00:00
c5d712232d
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
...
Radar 8031193.
llvm-svn: 106582
2010-06-22 22:04:24 +00:00
e9c1bb6cb1
Look for and use a different darwin crash reporter library.
...
llvm-svn: 106576
2010-06-22 21:01:04 +00:00
6c275bc5a2
fix typo
...
llvm-svn: 106574
2010-06-22 20:52:02 +00:00
c89d2aad4c
use high-level accessors
...
llvm-svn: 106573
2010-06-22 20:40:38 +00:00
b575cf69f4
warmup ritual: use high-level argument accessors
...
llvm-svn: 106563
2010-06-22 19:46:37 +00:00
e3fbbd19ed
Clone named metadata while cloning a module.
...
Reapply Bob's patch.
llvm-svn: 106560
2010-06-22 18:52:38 +00:00
3af915f84b
Reorganize logical and arithmetic SSE 1 & 2 instructions
...
llvm-svn: 106557
2010-06-22 18:17:40 +00:00
b91af24d3e
Reorganize SSE instructions, making easier to see oportunities for refactoring
...
llvm-svn: 106556
2010-06-22 18:09:32 +00:00
3570f81b1e
Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks out
...
into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.
llvm-svn: 106555
2010-06-22 17:25:57 +00:00
9c47dac677
Remove the SimpleJoin optimization from SimpleRegisterCoalescing.
...
Measurements show that it does not speed up coalescing, so there is no reason
the keep the added complexity around.
Also clean out some unused methods and static functions.
llvm-svn: 106548
2010-06-22 16:13:57 +00:00
d2d1ae105d
Use pre-increment instead of post-increment when the result is not used.
...
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
2ceaa71bdb
Add an explicit keyword.
...
llvm-svn: 106538
2010-06-22 13:53:29 +00:00
f820bd327d
Allow "exhaustive" trip count evaluation on phi nodes with all
...
constant operands.
llvm-svn: 106537
2010-06-22 13:15:46 +00:00
f040dec68a
Revert 106528. It is causing self host failures.
...
llvm-svn: 106529
2010-06-22 06:14:09 +00:00
b195eb4acf
Do not rely on DenseMap slot which can be easily invalidated when DenseMap grows.
...
llvm-svn: 106528
2010-06-22 05:16:56 +00:00
6c1fc79cab
Revert my change to clone named metadata. Buildbots are complaining.
...
--- Reverse-merging r106508 into '.':
U lib/Transforms/Utils/CloneModule.cpp
llvm-svn: 106521
2010-06-22 02:08:51 +00:00
2370e2fe0f
When unfolding a load, avoid assuming which instruction that
...
kill and dead flags will end up on.
llvm-svn: 106520
2010-06-22 02:07:21 +00:00
b6e058da18
Use single interface, using twine, to get named metadata.
...
getNamedMetadata().
llvm-svn: 106518
2010-06-22 01:19:38 +00:00
37bb617f8a
Tail merging pass shall not break up IT blocks. rdar://8115404
...
llvm-svn: 106517
2010-06-22 01:18:16 +00:00
cbc6fd8493
Discard special LLVM prefix from linkage name.
...
llvm-svn: 106516
2010-06-22 01:06:05 +00:00
ad51735794
Do not rely on Twine temporaries to survive.
...
llvm-svn: 106515
2010-06-22 01:01:58 +00:00
60bb7c42a7
make sure to initialize indent_level
...
llvm-svn: 106513
2010-06-22 00:40:26 +00:00
851e478e6b
Fix the new load-unfolding code to update LiveVariable's dead flags,
...
in addition to the kill flags.
llvm-svn: 106512
2010-06-22 00:32:04 +00:00
5f9575c1cd
Include named metadata when cloning a module.
...
llvm-svn: 106508
2010-06-22 00:11:03 +00:00
64960f55fe
add some support for blockaddress. This isn't really enough to be useful,
...
but it will cover uses of blockaddress that are actually in a function.
llvm-svn: 106502
2010-06-21 23:19:36 +00:00
bb45b964f8
eliminate a mutable global variable, use raw_ostream::indent instead of
...
rolling our own.
llvm-svn: 106501
2010-06-21 23:14:47 +00:00
a0b8c90870
un-indent a huge amount of code out of an anonymous namespace.
...
llvm-svn: 106500
2010-06-21 23:12:56 +00:00
b7dadb0e95
revert r106482
...
llvm-svn: 106499
2010-06-21 22:59:03 +00:00
3c1b3c61e9
Teach two-address lowering how to unfold a load to open up commuting
...
opportunities. For example, this lets it emit this:
movq (%rax), %rcx
addq %rdx, %rcx
instead of this:
movq %rdx, %rcx
addq (%rax), %rcx
in the case where %rdx has subsequent uses. It's the same number
of instructions, and usually the same encoding size on x86, but
it appears faster, and in general, it may allow better scheduling
for the load.
llvm-svn: 106493
2010-06-21 22:17:20 +00:00
510d9a3404
change parameter name to avoid confusion with global definition
...
llvm-svn: 106486
2010-06-21 21:28:07 +00:00
72df24037e
sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.
...
Radar 8104310.
llvm-svn: 106484
2010-06-21 21:27:34 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
374b2195f6
Add unpack and interleave AVX instructions, encoding tests cooming soon
...
llvm-svn: 106482
2010-06-21 21:21:48 +00:00
1fb4de8ec5
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
...
llvm-svn: 106481
2010-06-21 21:21:14 +00:00
79d2075e4a
"This is just a cosmetic change in MCAsmStreamer.cpp/EmitSymbolAttribute: all attributes have now a \t before and after, as done for '.type'.
...
This makes the output look consistent, as well as help some third party assemblers expecting the attributes to be in the second column."
Patch by Arnaud de Grandmaison!
llvm-svn: 106469
2010-06-21 20:35:01 +00:00
6dd51a2bb6
Remove isTwoAddress from SystemZ.
...
llvm-svn: 106467
2010-06-21 20:25:57 +00:00
d7a7356be6
Remove isTwoAddress from Sparc.
...
llvm-svn: 106466
2010-06-21 20:22:35 +00:00
c7927f2013
Remove isTwoAddress from Mips.
...
llvm-svn: 106465
2010-06-21 20:19:21 +00:00
fb008dfa05
Remove isTwoAddress from Blackfin.
...
llvm-svn: 106457
2010-06-21 20:13:37 +00:00
fa1b54d26e
Remove isTwoAddress from MSP430.
...
llvm-svn: 106455
2010-06-21 20:07:30 +00:00
dd41bba517
Use A.append(...) instead of A.insert(A.end(), ...) when A is a
...
SmallVector, and other SmallVector simplifications.
llvm-svn: 106452
2010-06-21 19:47:52 +00:00
0ca648d758
Make 80-column.
...
llvm-svn: 106448
2010-06-21 18:56:55 +00:00
98392f69e3
Remove isTwoAddress from PIC16.
...
llvm-svn: 106447
2010-06-21 18:55:01 +00:00
2401271217
Remove isTwoAddress from XCore.
...
llvm-svn: 106446
2010-06-21 18:51:38 +00:00
e159407231
Remove isTwoAddress from Alpha.
...
llvm-svn: 106445
2010-06-21 18:48:55 +00:00
ffdee30e90
Move several non-performance-critical member functinos out of line.
...
llvm-svn: 106444
2010-06-21 18:46:45 +00:00
e80de80270
Do not directly use function names to construct new name for named metadata.
...
"llvm.dbg.lv.~A" is not a valid name.
llvm-svn: 106438
2010-06-21 18:36:58 +00:00
29a894dd64
Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms
...
llvm-svn: 106437
2010-06-21 18:36:04 +00:00
20de4258f8
Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed
...
llvm-svn: 106436
2010-06-21 18:22:54 +00:00
d5c58b76ab
Fix PR 7433. Silly typo in non-Darwin ARM tail call
...
handling, plus correct R9 handling in that mode.
llvm-svn: 106434
2010-06-21 18:21:49 +00:00
bf572c7cea
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
...
Based on a patch by Patrick Marlier!
llvm-svn: 106433
2010-06-21 18:21:27 +00:00
97c8a6a928
early exit for dbg_value instructions
...
llvm-svn: 106430
2010-06-21 17:49:23 +00:00
74b5e3e0ae
remove some dead variables reported by clang++
...
llvm-svn: 106428
2010-06-21 17:20:18 +00:00
bbc29ea821
Revert r106422, which is breaking the non-fast-isel path.
...
llvm-svn: 106423
2010-06-21 16:02:28 +00:00
f64fdd69d0
More changes for non-top-down fast-isel.
...
Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.
llvm-svn: 106422
2010-06-21 15:13:54 +00:00
0ab5a02579
Mark the SPU 'lr' instruction to never have side effects.
...
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
2010-06-21 15:08:16 +00:00
d7f50c118a
Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
...
llvm-svn: 106419
2010-06-21 14:42:19 +00:00
f91aff5f13
Do one lookup instead of two.
...
llvm-svn: 106415
2010-06-21 14:21:47 +00:00
7c58cf75fa
Generalize this to look in the regular ValueMap in addition to
...
the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.
llvm-svn: 106414
2010-06-21 14:17:46 +00:00
1cae86f704
Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.
...
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.
llvm-svn: 106413
2010-06-21 13:31:32 +00:00
6f58190f6f
Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
...
used to choke llc with the attached test.
llvm-svn: 106411
2010-06-21 10:17:36 +00:00
c596baa56d
wip
...
llvm-svn: 106408
2010-06-21 02:17:34 +00:00
dcc7b6dcb6
Fix warning in no-asserts build.
...
llvm-svn: 106405
2010-06-20 20:27:42 +00:00
884a8fe5fa
Fix a crash caused by dereference of MBB.end(). rdar://8110842
...
llvm-svn: 106399
2010-06-20 00:54:38 +00:00
c515ab1eb2
Restore a call to rememberInstruction which was accidentally dropped
...
in refactoring.
llvm-svn: 106398
2010-06-19 22:50:35 +00:00
32655906e4
Add a TODO comment.
...
llvm-svn: 106397
2010-06-19 21:30:18 +00:00
51d00092b6
Include the use kind along with the expression in the key of the
...
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.
More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.
llvm-svn: 106396
2010-06-19 21:29:59 +00:00
297fb8b9fc
Don't include things in anonymous namespaces that don't need it.
...
llvm-svn: 106395
2010-06-19 21:21:39 +00:00
bf5c3d42ba
Use calloc instead of new/memset, it is more efficient when the set is very large.
...
llvm-svn: 106390
2010-06-19 17:00:31 +00:00
866971ed3d
Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid
...
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.
llvm-svn: 106389
2010-06-19 14:17:24 +00:00
d277246137
Factor out duplicated code for reusing and inserting casts into
...
a helper function.
llvm-svn: 106388
2010-06-19 13:25:23 +00:00
4581434c27
Tidy.
...
llvm-svn: 106383
2010-06-19 05:33:57 +00:00
6d12973143
Remove a fixme comment that is no longer relevant.
...
llvm-svn: 106382
2010-06-19 05:32:41 +00:00
0ae08935f6
Fix error message to match function name.
...
llvm-svn: 106381
2010-06-19 05:32:09 +00:00
b86a3abcc7
Refactoring of regular logical packed instructions to prepare for AVX ones.
...
llvm-svn: 106375
2010-06-19 04:09:22 +00:00
8737b7d73d
Refactor aliased packed logical instructions, also add
...
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.
llvm-svn: 106374
2010-06-19 02:44:01 +00:00
7079bf815d
Ignore dbg_value's.
...
llvm-svn: 106373
2010-06-19 02:36:21 +00:00
a588049ce9
Move new sse 1 & 2 generic classes to a more appropriate place
...
llvm-svn: 106372
2010-06-19 01:32:46 +00:00
2787efd961
Remove unnecessary arguments
...
llvm-svn: 106371
2010-06-19 01:22:34 +00:00
00ada89f95
Add AVX packed intrinsics for MIN, MAX
...
llvm-svn: 106370
2010-06-19 01:17:05 +00:00
f3c01f3ef6
Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
...
llvm-svn: 106368
2010-06-19 01:01:32 +00:00
42105b2976
Finish ripping isTwoAddress out of X86. Some mindless formatting
...
and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
llvm-svn: 106367
2010-06-19 00:37:40 +00:00
1e205f6b1c
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
...
llvm-svn: 106366
2010-06-19 00:37:31 +00:00
c60cecd88b
rip out dead code.
...
llvm-svn: 106365
2010-06-19 00:34:14 +00:00
e808a78ac1
fix rdar://7873482 by teaching the instruction encoder to emit
...
segment prefixes. Daniel wrote most of this patch.
llvm-svn: 106364
2010-06-19 00:34:00 +00:00
e5fcd333da
Indentation and remove dead code.
...
llvm-svn: 106362
2010-06-19 00:11:54 +00:00
1888f11887
Clean up: remove now unnecessary Constraints
...
llvm-svn: 106361
2010-06-19 00:09:27 +00:00
5fc43eb186
Silence compiler warnings.
...
llvm-svn: 106360
2010-06-19 00:02:06 +00:00
502c4fe61c
more refactoring! yay! big win over the intrinsics
...
llvm-svn: 106359
2010-06-19 00:00:22 +00:00
6bdbdb5544
Remove isTwoAddress from here too.
...
llvm-svn: 106358
2010-06-18 23:56:07 +00:00
66d2d57d9b
Fix typo, SSE1 should be used by XS, not SSE2
...
llvm-svn: 106357
2010-06-18 23:53:27 +00:00
3577c1b811
Remove isTwoAddress from 64-bit files.
...
llvm-svn: 106356
2010-06-18 23:51:21 +00:00
119824ed4d
Move ARM if-conversion before post-ra scheduling.
...
llvm-svn: 106355
2010-06-18 23:32:07 +00:00
8693650422
Teach regular and fast isel to set dead flags on unused implicit defs
...
on calls and similar instructions.
llvm-svn: 106353
2010-06-18 23:28:01 +00:00
2bfad417a1
Apply some refactor to packed instructions
...
llvm-svn: 106349
2010-06-18 23:13:35 +00:00
4f0781c9b3
Update cmake list.
...
llvm-svn: 106348
2010-06-18 23:12:10 +00:00
285935939d
Thumb2 hazard recognizer.
...
llvm-svn: 106347
2010-06-18 23:11:35 +00:00
678927e0b1
Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up
...
the inserted INSERT_SUBREGs after us.
llvm-svn: 106345
2010-06-18 23:10:20 +00:00
2d51c7c592
Allow ARM if-converter to be run after post allocation scheduling.
...
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
llvm-svn: 106344
2010-06-18 23:09:54 +00:00
a57c2885cf
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)
...
llvm-svn: 106342
2010-06-18 23:03:10 +00:00
6860bb7796
Enable Expand handling of atomics for subtargets that can't do them inline.
...
llvm-svn: 106336
2010-06-18 22:35:32 +00:00
07f4fa8198
TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
...
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.
Fix it in LiveVariableAnalysis by adding the <undef> flag.
llvm-svn: 106333
2010-06-18 22:29:44 +00:00
cf9e8a987f
Fix an inverted condition.
...
llvm-svn: 106330
2010-06-18 22:17:13 +00:00
871439abd2
Use the new 'defm' class inheritance in SSE
...
llvm-svn: 106327
2010-06-18 22:10:11 +00:00
f5d62535a5
Fix cross initialization compilation error.
...
llvm-svn: 106324
2010-06-18 22:01:37 +00:00
c0e0d85b18
Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.
...
llvm-svn: 106323
2010-06-18 21:52:57 +00:00
d64dfc1568
Add Expand-to-libcall support for additional atomics. This covers the usual
...
entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.
This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.
llvm-svn: 106321
2010-06-18 21:43:38 +00:00
a92e41a50a
Rewrite chained if's as switches and replace assertions with llvm_unreachable
...
(as suggested in radar 8104405).
llvm-svn: 106318
2010-06-18 21:32:42 +00:00
589ffb4902
Fix ARM/Thumb reversal in previous attempt.
...
llvm-svn: 106314
2010-06-18 21:07:47 +00:00
22a212f97c
When using ADDri to get the address of a stack object, 255 is a conservative
...
limit on the offset that can be materialized without using the register
scavenger.
llvm-svn: 106312
2010-06-18 20:59:25 +00:00
a46d607545
Make this comment less specific.
...
llvm-svn: 106311
2010-06-18 20:45:41 +00:00
af4903d6ee
Fix X86FastISel's address-mode folding to stay within the
...
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.
llvm-svn: 106310
2010-06-18 20:44:47 +00:00
a06c2f79fc
An attempt to fix the problem Anton reported with
...
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.
llvm-svn: 106309
2010-06-18 20:44:28 +00:00
24ceda8eb0
Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
...
optimizations. There is still some nondeterminism remaining.
llvm-svn: 106306
2010-06-18 19:54:20 +00:00
4c807fca97
Reapply 105540, 105542, and 105548, and revert r105732.
...
llvm-svn: 106304
2010-06-18 19:26:04 +00:00
45073042eb
Reapply 105546.
...
llvm-svn: 106302
2010-06-18 19:12:32 +00:00
9136d9fbf8
Reapply 105544.
...
llvm-svn: 106301
2010-06-18 19:09:27 +00:00
c1570dda5c
Enable tail calls on ARM by default, with some
...
basic tests.
This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
B.W <label in other function>
which it has not seen before, at least from llvm-based
compilers. I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.
llvm-svn: 106299
2010-06-18 19:00:18 +00:00
e5457c275d
Don't leak RegClass2VRegMap, which is now a new[] array instead of a
...
std::vector.
llvm-svn: 106298
2010-06-18 18:54:05 +00:00
882bb2984e
Start TargetRegisterClass indices at 0 instead of 1, so that
...
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
llvm-svn: 106296
2010-06-18 18:13:55 +00:00
3ac52b3e43
Last round of changes for ARM tail calls.
...
Not turning them on yet.
llvm-svn: 106295
2010-06-18 18:13:11 +00:00
f82c8fcc58
Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
...
so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.
This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block. Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable. That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.
This is pretty fragile. If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion. But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.
Evan, please review!
llvm-svn: 106291
2010-06-18 17:07:23 +00:00
b9f91667e1
Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
...
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.
llvm-svn: 106289
2010-06-18 16:49:33 +00:00
9f58b3e106
Don't bother calling releaseMemory before destroying the DominatorTreeBase.
...
llvm-svn: 106287
2010-06-18 16:09:11 +00:00
7edb39cc6b
Minor code simplifications.
...
llvm-svn: 106286
2010-06-18 16:00:29 +00:00
6e681a5fbe
Give NamedRegionTimer an Enabled flag, allowing all its clients to
...
switch from this:
if (TimePassesIsEnabled) {
NamedRegionTimer T(Name, GroupName);
do_something();
} else {
do_something(); // duplicate the code, this time without a timer!
}
to this:
{
NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
do_something();
}
llvm-svn: 106285
2010-06-18 15:56:31 +00:00
96ca25eba5
Don't replace the old Ordering object with a new one; just clear()
...
the old one.
llvm-svn: 106284
2010-06-18 15:40:58 +00:00
a4f46b3ef8
Don't call clear() on DbgInfo when it's going to be deleted anyway.
...
Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.
llvm-svn: 106283
2010-06-18 15:36:18 +00:00
92c11acdb8
Change UpdateNodeOperands' operand and return value from SDValue to
...
SDNode *, since it doesn't care about the ResNo value.
llvm-svn: 106282
2010-06-18 15:30:29 +00:00
3d8a9d7490
Remove getIntegerSCEV; it's redundant with getConstant, and getConstant
...
is more consistent with the ConstantInt API.
llvm-svn: 106281
2010-06-18 14:33:50 +00:00
c3479f5342
Delete unused variables.
...
llvm-svn: 106280
2010-06-18 14:32:32 +00:00
f1d8304fe3
Eliminate unnecessary uses of getZExtValue().
...
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
35b6f9a929
isValueValidForType can be a static member function.
...
llvm-svn: 106278
2010-06-18 14:01:07 +00:00
67d25f91c5
Some assorted isTwoAddress -> Constraints cleanup.
...
llvm-svn: 106273
2010-06-18 02:41:19 +00:00
c61056a421
Handle execution entrypoints with non-integer return types.
...
Fix from Russel Power in PR7284.
llvm-svn: 106271
2010-06-18 02:01:10 +00:00
f3aea7aecf
Disable indvars on loops when LoopSimplify form is not available.
...
This fixes PR7333.
llvm-svn: 106267
2010-06-18 01:35:11 +00:00
99ba4dac59
Don't maintain a set of deleted nodes; instead, use a HandleSDNode
...
to track a node over CSE events. This fixes PR7368.
llvm-svn: 106266
2010-06-18 01:24:29 +00:00
2323168705
Add {mix,max}{ss,sd}{rr,rm} AVX forms.
...
llvm-svn: 106264
2010-06-18 01:12:56 +00:00
b92156d5e4
Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
...
which is faster, simpler, and less surprising.
llvm-svn: 106263
2010-06-18 01:05:21 +00:00
8ba26b48bb
Fix a typo in a comment.
...
llvm-svn: 106260
2010-06-18 00:53:08 +00:00
0883789ec4
Handle ext(ext(x)) -> ext(x) immediately, since it's simple.
...
llvm-svn: 106256
2010-06-18 00:08:30 +00:00
8f5954f42c
Simplify this code.
...
llvm-svn: 106254
2010-06-17 23:34:09 +00:00
6b98f7129f
Use new tablegen resources in SSE tablegen code. This will
...
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction
llvm-svn: 106251
2010-06-17 23:05:30 +00:00
0125b6410a
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
...
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
llvm-svn: 106243
2010-06-17 22:43:56 +00:00
0ed5b460dc
add missing break. inconsequential as the code shouldn't be reached, but
...
for correctness' sake, it should be there.
llvm-svn: 106229
2010-06-17 17:58:54 +00:00
3aeae8aeeb
Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder
...
for the moment. The implementation of the libcall will follow.
Currently, the llvm-gcc knows when the intrinsics can be correctly handled by
the back end and only generates them in those cases, issuing libcalls directly
otherwise. That's too much coupling. The intrinsics should always be
generated and the back end decide how to handle them, be it with a libcall,
inline code, or whatever. This patch is a step in that direction.
rdar://8097623
llvm-svn: 106227
2010-06-17 17:50:54 +00:00
5712c77c89
Thumb1 and any pre-v6 ARM target should use the libcall expansion of
...
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.
llvm-svn: 106204
2010-06-17 02:02:03 +00:00
ba451e80dc
ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the target
...
sets the legalize action to Expand.
llvm-svn: 106203
2010-06-17 02:00:53 +00:00
6e758c97fd
simplify code a bit and add a more explanatory assert for cases that
...
previously would result in 'cannot yet select' errors.
llvm-svn: 106199
2010-06-17 01:37:00 +00:00
dd6a4cabf6
Add the entire range of DW_OP_lit[0..31], DW_OP_reg[0..31], and
...
DW_OP_breg[0..31] to Dwarf.h.
Add "DW_" prefix to the llvm::dwarf::*String methods which did not
already have them in Dwarf.cpp.
llvm-svn: 106197
2010-06-17 01:23:24 +00:00
29b58afdf1
Hack to let the move lowering handle dynamic-no-pic absolute moves of
...
TLVP:
movl _a@TLVP, %eax
Daniel: Please review if you get a chance.
llvm-svn: 106194
2010-06-17 00:51:48 +00:00
93f16372f9
Update comment.
...
llvm-svn: 106191
2010-06-17 00:49:46 +00:00
e3864cc15e
format and 80-column cleanup
...
llvm-svn: 106173
2010-06-16 23:45:49 +00:00
e94f1ded24
remove trailing whitespace
...
llvm-svn: 106164
2010-06-16 22:41:09 +00:00
2334144e6e
Don't attempt preserving conservative kill flags. We were doing it wrong.
...
This is before LiveVariables anyway, where these kill flags are recalculated.
llvm-svn: 106157
2010-06-16 22:11:08 +00:00
01ac8f9fc0
Remove the hidden "neon-reg-sequence" option. The reg sequences are working
...
now, so there's no need to disable them.
llvm-svn: 106155
2010-06-16 21:34:01 +00:00
74892d4f1f
In progress on 32-bit addends.
...
llvm-svn: 106154
2010-06-16 21:32:38 +00:00
207cd4bbd7
Allow a register to be redefined multiple times in a basic block.
...
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.
Here is an example of chained INSERT_SUBREGs that we can handle now:
68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
register: %reg1040 +[70,134:0)
76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78)
84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86)
92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)
rdar://problem/8096390
llvm-svn: 106152
2010-06-16 21:29:40 +00:00
fd3b4e7390
A few more places where SCEVExpander bits need to skip over debug intrinsics
...
when iterating through instructions. Yet more work for rdar://7797940
llvm-svn: 106149
2010-06-16 21:13:38 +00:00
ede8e6d2f0
MC/Mach-O: Rewrite atom association to be a final pass we do in Finish(), instead of tracking as part of emission.
...
- This allows sharing more code with the MCObjectStreamer.
llvm-svn: 106143
2010-06-16 20:04:32 +00:00
aa627c39e4
MC: Simplify MCAssembler::isSymbolLinkerVisible to only take an MCSymbol.
...
llvm-svn: 106142
2010-06-16 20:04:29 +00:00
b2347fe504
MC: Lift SwitchSection() and Finish() into MCObjectStreamer.
...
llvm-svn: 106141
2010-06-16 20:04:25 +00:00
8a3c9d9bc4
MC: Factor out an MCObjectStreamer class, which will be shared by the concrete
...
object file format writers.
llvm-svn: 106140
2010-06-16 20:04:22 +00:00
a20e2dfe86
Make sure that simplify libcalls does not replace a call with one calling
...
convention with a new call with a different calling convention.
llvm-svn: 106134
2010-06-16 19:34:01 +00:00
6c0da25129
add FIXME
...
llvm-svn: 106126
2010-06-16 18:45:08 +00:00
d71bd63600
Improve comment to include that the use of a preg is also verboten in this situation.
...
llvm-svn: 106119
2010-06-16 18:01:31 +00:00
41476410c9
TODO--
...
llvm-svn: 106102
2010-06-16 15:47:00 +00:00
a13bd20396
simplify-libcalls: fold strncmp(x, y, 1) -> memcmp(x, y, 1)
...
The memcmp will be optimized further and even the pathological case
'strstr(x, "x") == x' generates optimal code now.
llvm-svn: 106097
2010-06-16 10:30:29 +00:00
f128bdcb55
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
...
llvm-svn: 106091
2010-06-16 07:35:02 +00:00
d119da54de
Check function pointer first, before comparing function names.
...
llvm-svn: 106088
2010-06-16 06:42:02 +00:00
a6d20f446f
Use separate named MDNode to hold each function's local variable info.
...
This speeds up local variable handling in DwarfDebug.
llvm-svn: 106075
2010-06-16 00:53:55 +00:00
b672ab9b53
Don't emit the linkage for initializer label for mach-o tls.
...
llvm-svn: 106073
2010-06-16 00:27:30 +00:00
2092dc2acd
Fix indentation.
...
llvm-svn: 106072
2010-06-16 00:26:36 +00:00
8c0cf0994d
Create a more targeted fix for not sinking instructions into a range where it
...
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.
llvm-svn: 106066
2010-06-15 23:46:31 +00:00
6c4d63e1a5
For 32-bit non-pic tlv mach-o addressing we don't need a pic base or
...
a relative address.
llvm-svn: 106064
2010-06-15 23:08:42 +00:00
9b5005cd4b
Added a comment.
...
llvm-svn: 106063
2010-06-15 23:06:30 +00:00
a86c2bdd2c
Some more work on mach-o TLV relocations.
...
llvm-svn: 106062
2010-06-15 22:59:05 +00:00
438c35b5d1
Add file missing from previous commit.
...
llvm-svn: 106058
2010-06-15 22:24:08 +00:00
8105144fcd
Fix 80col violations, remove trailing whitespace, and clarify a comment.
...
llvm-svn: 106057
2010-06-15 22:18:54 +00:00
44f9dfc9cf
Next round of tail call changes. Register used in a tail
...
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
llvm-svn: 106053
2010-06-15 22:08:33 +00:00
ec2e964fd6
Remove the local register allocator.
...
Please use the fast allocator instead.
llvm-svn: 106051
2010-06-15 21:58:33 +00:00
89456b2612
Reapply 105986 with fix for bug pointed out by Jakob:
...
flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info. I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.
llvm-svn: 106049
2010-06-15 21:36:43 +00:00
1118860e3a
simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0
...
llvm-svn: 106047
2010-06-15 21:34:25 +00:00
7a84689cc5
Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen!
...
llvm-svn: 106038
2010-06-15 20:29:05 +00:00
e22295e8a6
fpcmp: Fix bug where fpcmp wouldn't early exit when files obviously differ and
...
no tolerance is set.
llvm-svn: 106033
2010-06-15 19:20:30 +00:00
b645fa13a9
fpcmp: Fix a possible infinite loop when comparing something like:
...
1..19 ok
to
1..20 o k
(yes, the odd space is necessary).
llvm-svn: 106032
2010-06-15 19:20:28 +00:00
874c92bd47
fix fastisel to handle GS and FS relative pointers. Patch by
...
Nelson Elhage!
llvm-svn: 106031
2010-06-15 19:08:40 +00:00
f3f7a770b7
Add basic support for NEON modified immediates besides VMOV.
...
llvm-svn: 106030
2010-06-15 19:05:35 +00:00
fc7d739422
IfConversion's AnalyzeBlocks method always returns false; clean it up.
...
llvm-svn: 106027
2010-06-15 18:57:15 +00:00
c964585ff8
fix naming
...
llvm-svn: 106024
2010-06-15 18:53:34 +00:00
6e54c908e0
Fix an exotic bug that only showed up in an internal test case.
...
SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a
copy is coalescable, and in very rare cases it can return true where LHS is not
live - the coalescable copy can come from an alias of the physreg in LHS.
llvm-svn: 106021
2010-06-15 18:49:14 +00:00
5947573f39
Fix a comment typo.
...
llvm-svn: 106015
2010-06-15 18:19:27 +00:00
de94e66234
Add some missing checks for the case where the extract_subregs are
...
combined to an insert_subreg, i.e., where the destination register is larger
than the source. We need to check that the subregs can be composed for that
case in a symmetrical way to the case when the destination is smaller.
llvm-svn: 106004
2010-06-15 17:27:54 +00:00
246e9a07a2
Avoid processing early clobbers twice in RegAllocFast.
...
Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.
This fixes PR7382.
llvm-svn: 105998
2010-06-15 16:20:57 +00:00
82eca35b3e
Add CoalescerPair helper class.
...
Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:
- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.
CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.
The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.
llvm-svn: 105997
2010-06-15 16:04:21 +00:00
0904134252
Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.
...
llvm-svn: 105994
2010-06-15 14:50:42 +00:00
a55b8877e6
Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
...
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues. This makes a pretty noticable difference
in our testcases where reg_sequences are used. I've updated one test to
check that we no longer emit the unnecessary subreg moves.
llvm-svn: 105991
2010-06-15 05:56:31 +00:00
1478142485
VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.
...
llvm-svn: 105990
2010-06-15 05:51:27 +00:00
3f253d2353
Revert 105986; looks like I'd better try bootstrapping.
...
llvm-svn: 105988
2010-06-15 04:55:06 +00:00
d52caa5244
Update CMake build.
...
llvm-svn: 105987
2010-06-15 04:08:14 +00:00
c338ef2b65
The form of BuildMI used for TAILJMPr was changing the register
...
containing the target address, an input, into an output. I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.
llvm-svn: 105986
2010-06-15 03:13:49 +00:00
f14e08b01b
Make sure to skip dbg_value instructions when finding an insertion point for
...
the combined load/store instruction. rdar://7797940
llvm-svn: 105982
2010-06-15 00:41:09 +00:00
5b2b504038
Rename functions referring to VMOV immediates to refer to NEON "modified
...
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
llvm-svn: 105969
2010-06-14 22:19:57 +00:00
412800d346
More dbg_value cleanup so the presence of debug info doesn't affect code-gen.
...
Make sure to skip the dbg_value instructions when moving dups out of the
diamond. rdar://7797940
llvm-svn: 105965
2010-06-14 21:30:32 +00:00
078f4cec21
- Do away with SimpleHazardRecognizer.h. It's not used and offers little value.
...
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.
llvm-svn: 105959
2010-06-14 21:06:53 +00:00
a397ada078
Avoid uncessary array copying.
...
llvm-svn: 105955
2010-06-14 20:18:40 +00:00
faa7bdccbf
fix a nasty bug where we were not treating available_externally
...
symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
llvm-svn: 105954
2010-06-14 20:11:56 +00:00
329ea064ed
jump threading can't split a critical edge from an indirectbr. This
...
fixes PR7356.
llvm-svn: 105950
2010-06-14 19:45:43 +00:00
58c09b2859
fix a -Wbool-conversions warning from clang.
...
llvm-svn: 105943
2010-06-14 18:28:57 +00:00
0fc88efda3
fix a -Wbool-conversions warning from clang.
...
llvm-svn: 105942
2010-06-14 18:28:34 +00:00
ba1f1fcae5
Add back some possible optimizations for va_arg, with wording that makes it
...
more clear what exactly is missing.
llvm-svn: 105934
2010-06-14 07:03:30 +00:00
b82de426de
SimplifyCFG: don't turn volatile stores to null/undef into unreachable. Fixes PR7369.
...
llvm-svn: 105914
2010-06-13 14:35:54 +00:00
e302f833e1
Merge getStoreRegOpcode and getLoadRegOpcode.
...
llvm-svn: 105900
2010-06-12 20:13:29 +00:00
2ed39551a7
improve verifier error about unterminated block to include
...
function name, patch by Yuri
llvm-svn: 105887
2010-06-12 15:50:24 +00:00
e17e4aea2a
Add README entry; based on testcase from Bill Hart.
...
llvm-svn: 105878
2010-06-12 05:54:27 +00:00
ada854f8b6
make the avx intrinsics 3 address
...
llvm-svn: 105876
2010-06-12 03:12:14 +00:00
f203703467
Add some basic fp intrinsics for AVX
...
llvm-svn: 105873
2010-06-12 02:38:32 +00:00
5d6103318a
When performing the Horrible Hack(tm-Duncan) on the EH code to convert a
...
clean-up to a catch-all after inlining, take into account that there could be
filter IDs as well. The presence of filters don't mean that the selector catches
anything. It's just metadata information.
llvm-svn: 105872
2010-06-12 02:34:29 +00:00
a714ea0f7d
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm
...
llvm-svn: 105870
2010-06-12 01:53:48 +00:00
b06f54b852
More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr
...
Handle OpSize TSFlag for AVX
llvm-svn: 105869
2010-06-12 01:23:26 +00:00
e60273fd70
Allow target to provide its own hazard recognizer to post-ra scheduler.
...
llvm-svn: 105862
2010-06-12 00:12:18 +00:00
cb1fe56fd9
Code formatting.
...
llvm-svn: 105861
2010-06-12 00:11:53 +00:00
8947c32493
Add some comments about REX fields
...
llvm-svn: 105860
2010-06-12 00:03:52 +00:00
fd5458d4bd
More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
...
Introduce the VEX_X field
llvm-svn: 105859
2010-06-11 23:50:47 +00:00
f07d33d8f1
Add a missing bitcast. This code used to only handle conversions between
...
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type. Radar 8084742.
llvm-svn: 105845
2010-06-11 22:45:25 +00:00
6eae520de9
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
llvm-svn: 105836
2010-06-11 21:34:50 +00:00
afe54f1625
Support for nested functions/classes in debug output. (Again.) Radar 7424645.
...
llvm-svn: 105828
2010-06-11 20:08:44 +00:00
6111abf8ad
Delete duplicate function.
...
llvm-svn: 105827
2010-06-11 20:05:01 +00:00
a349d522f7
Avoid "variable 'bits' set but not used [-Wunused-but-set-variable]"
...
warnings with gcc-4.6, by not setting bits when the result is not
used.
llvm-svn: 105790
2010-06-10 16:23:15 +00:00
38f6560461
Code refactoring, no functionality changes.
...
llvm-svn: 105775
2010-06-10 02:09:31 +00:00
2901371c32
Delete code that's not safe.
...
llvm-svn: 105774
2010-06-10 02:08:20 +00:00
5fa0158ecd
be slightly more subtle about skipping dbg_value instructions; otherwise, if a
...
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.
llvm-svn: 105758
2010-06-09 22:21:24 +00:00
8bc5eca331
Mark physregs defined by inline asm as implicit.
...
This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.
llvm-svn: 105749
2010-06-09 20:05:00 +00:00
a0746bd50a
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
...
llvm-svn: 105745
2010-06-09 19:26:01 +00:00
5ac1d23d3d
It's an error to translate this:
...
%reg1025 = <sext> %reg1024
...
%reg1026 = SUBREG_TO_REG 0, %reg1024, 4
into this:
%reg1025 = <sext> %reg1024
...
%reg1027 = EXTRACT_SUBREG %reg1025, 4
%reg1026 = SUBREG_TO_REG 0, %reg1027, 4
The problem here is that SUBREG_TO_REG is there to assert that an implicit zext
occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG
here, it will give us the value after the <sext>, not the original value of
%reg1024 before <sext>.
llvm-svn: 105741
2010-06-09 19:00:55 +00:00
ae83e1f5cb
Revert 105540, 105542, 105544, 105546, and 105548 to unbreak bootstrapping.
...
llvm-svn: 105740
2010-06-09 18:59:43 +00:00
9b21208bfb
Pulled CodeMetrics out of InlineCost.h and made it a bit more general, so it can be reused from PartialSpecializationCost
...
llvm-svn: 105725
2010-06-09 15:11:37 +00:00
5e0862f7f5
Fix SPU to cope with vector insertelement to an undef position.
...
We default to inserting to lane 0.
llvm-svn: 105722
2010-06-09 09:58:17 +00:00
056113a211
Handle loading from/storing to undef pointers on SPU by inserting a
...
random load/store, rather than crashing llc.
llvm-svn: 105710
2010-06-09 08:29:41 +00:00
83c64ee8de
Typo.
...
llvm-svn: 105677
2010-06-09 03:49:12 +00:00
ab44d1281a
A few new x86-64 specific README entries.
...
llvm-svn: 105674
2010-06-09 02:43:17 +00:00
47cd593023
Thumb2 IT blocks are fairly expensive. When there are multiple selects using
...
the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.
Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.
llvm-svn: 105669
2010-06-09 01:46:50 +00:00
a13b1c29b0
Add argument name comments.
...
llvm-svn: 105665
2010-06-09 00:40:31 +00:00
0de0f3fc02
Incremental improvement to the handling of the x86 "Jump if rCX Zero"
...
instruction. Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode. Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.
llvm-svn: 105661
2010-06-08 23:48:44 +00:00
6ab55c5683
Split out these asserts so it's more apparent why we're not assembling
...
that rip-relative address when executing in 32-bit mode.
llvm-svn: 105656
2010-06-08 22:57:33 +00:00
8fe3cc8055
fix copy/paste/modify think-o
...
llvm-svn: 105653
2010-06-08 22:53:32 +00:00
c2f87b7bb2
Reapply r105521, this time appending "LLU" to 64 bit
...
immediates to avoid breaking the build.
llvm-svn: 105652
2010-06-08 22:51:23 +00:00
89d103a8ce
Ensure that mov and not lea are used to stick the address into
...
the register. While we're at it, make sure it's in the right one.
llvm-svn: 105645
2010-06-08 22:04:25 +00:00
57c6fd452e
fix typo
...
llvm-svn: 105634
2010-06-08 20:06:55 +00:00
5729f51410
Use const_iterator where appropriate.
...
llvm-svn: 105620
2010-06-08 17:21:57 +00:00
f2363de7ad
DeltaAlgorithm: Tweak split to split by first/second half instead of even/odd, since adjacent changes are more likely to be related.
...
llvm-svn: 105613
2010-06-08 16:21:26 +00:00
579ba2ac42
ADT: Add DAGDeltaAlgorithm, which is a DAG minimization algorithm built on top of the standard 'delta debugging' algorithm.
...
- This can give substantial speedups in the delta process for inputs we can construct dependency information for.
llvm-svn: 105612
2010-06-08 16:21:22 +00:00
4e36e5bb4c
Use realloc instead of malloc+memcpy when growing a POD SmallVector. A smart
...
realloc implementation can try to expand the allocated memory block in-place,
avoiding the copy.
llvm-svn: 105605
2010-06-08 11:44:30 +00:00
6c40caf729
Flag SPU's function call sequence together.
...
Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html
llvm-svn: 105601
2010-06-08 07:55:16 +00:00
0271c5928e
Fix up a comment.
...
llvm-svn: 105591
2010-06-08 00:42:08 +00:00
846bd7992c
Further changes for Neon vector shuffles:
...
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
llvm-svn: 105586
2010-06-07 23:53:38 +00:00
7149cfcda3
Fix a mistake in my previous change r105437: don't access operand 2 and assume
...
that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.
llvm-svn: 105585
2010-06-07 23:48:46 +00:00
7398758719
Add some basic debug output.
...
llvm-svn: 105561
2010-06-07 22:32:10 +00:00
723d242a95
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
...
rdar://7797940
llvm-svn: 105557
2010-06-07 21:48:47 +00:00
6201b991a2
Cleanup. Process the dbg_values separately
...
llvm-svn: 105554
2010-06-07 21:28:55 +00:00
fb8ed43349
Make bugpoint dead-argument-hacking actually work, and actually test it.
...
llvm-svn: 105551
2010-06-07 20:20:33 +00:00
ebf2e977cf
The FoldingSet hash data includes pointer values, so it isn't
...
determinstic. Instead, give SCEV objects an arbitrary sequence
number.
llvm-svn: 105548
2010-06-07 19:36:14 +00:00
3553feed79
Optimize this code somewhat by taking advantage of the fact
...
that the operands are sorted.
llvm-svn: 105546
2010-06-07 19:20:57 +00:00
cfcd0e12cf
Another place where the code wanted to access the argument list and not all of
...
the operands.
llvm-svn: 105545
2010-06-07 19:18:58 +00:00
a2effb6452
Micro-optimize this, to speed up this hotspot in debug builds a little.
...
llvm-svn: 105544
2010-06-07 19:16:37 +00:00
18a4b46404
Micro-optimize this.
...
llvm-svn: 105542
2010-06-07 19:12:54 +00:00
0f445f328e
Move exit check where it really belongs.
...
llvm-svn: 105541
2010-06-07 19:12:21 +00:00
70910a6ab6
Optimize ScalarEvolution's SCEVComplexityCompare predicate: don't go
...
scrounging through SCEVUnknown contents and SCEVNAryExpr operands;
instead just do a simple deterministic comparison of the precomputed
hash data.
Also, since this is more precise, it eliminates the need for the slow
N^2 duplicate detection code.
llvm-svn: 105540
2010-06-07 19:06:13 +00:00
a3bba3371a
Create new accessors to get arguments for call/invoke instructions. It breaks
...
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.
llvm-svn: 105539
2010-06-07 19:05:06 +00:00
1850444000
Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization. Patch by Takumi Nakamura\!
...
llvm-svn: 105528
2010-06-05 14:50:21 +00:00
e4f45cc88f
This bug is also present in MSVC10. Requested by Elrood on IRC.
...
llvm-svn: 105527
2010-06-05 12:40:43 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
...
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
...
yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
81ef35b3ca
Improvements to tail call code. No functional effect
...
unless using -arm-tail-calls.
llvm-svn: 105515
2010-06-05 00:51:39 +00:00
520913cf9e
getFoldedOffsetOf no longer does anything special with vector types.
...
llvm-svn: 105514
2010-06-05 00:47:34 +00:00
3ca391027f
Revert 105492 & 105493 due to a testcase regression. Radar 7424645.
...
llvm-svn: 105511
2010-06-05 00:39:29 +00:00
bbfb6aca92
LSR needs to remember inserted instructions even in postinc mode, because
...
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.
llvm-svn: 105510
2010-06-05 00:33:07 +00:00
df1a7f83bf
Fix some liveout handling related to tail calls, see comments.
...
I don't think this ever resulted in problems on x86, but it
would on ARM.
llvm-svn: 105509
2010-06-05 00:30:45 +00:00
a03e6f85fe
Re-apply 105308 with fix.
...
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
67b4403101
Don't track users of undef values; they aren't interesting for
...
register pressure.
llvm-svn: 105501
2010-06-04 23:16:05 +00:00
a1e08fb256
Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940
...
llvm-svn: 105498
2010-06-04 23:01:26 +00:00
7c015988fe
Support for nested functions/classes in debug output. Radar 7424645.
...
llvm-svn: 105492
2010-06-04 22:36:03 +00:00
36da24b546
Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.
...
llvm-svn: 105490
2010-06-04 22:27:30 +00:00
50d229e6b3
Skip dbg_value instructions when scanning instructions in register scavenging.
...
llvm-svn: 105481
2010-06-04 20:18:30 +00:00
538b413ccb
Fix normalization and de-normalization of non-affine SCEVs.
...
llvm-svn: 105480
2010-06-04 19:16:34 +00:00
864827afb0
Keep track of the call instructions whose clobber lists were skipped during fast
...
register allocation.
Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.
This is necessary in case the calls clobber callee-saved registers (sic).
llvm-svn: 105473
2010-06-04 18:08:29 +00:00
d1b9311afa
More thoroughly disable tails calls by default.
...
8060143, although this doesn't fix the real problem with tail call.
llvm-svn: 105472
2010-06-04 18:04:24 +00:00
3548803f62
Another fix to prevent debug info from affecting codegen. rdar://7797940
...
llvm-svn: 105470
2010-06-04 17:57:34 +00:00
4e5e6a8973
more dbg_value adjustments so debug info doesn't affect codegen
...
llvm-svn: 105454
2010-06-04 01:23:30 +00:00
622cdd2297
Fixed a bug during widening where we would avoid legalizing a node. When we
...
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes. Since OpA has been processed, the new uses are
not examined again. The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.
llvm-svn: 105453
2010-06-04 01:20:10 +00:00
1bcdf32d22
fix typo
...
llvm-svn: 105441
2010-06-04 00:15:00 +00:00
d8a9a04739
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
...
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
llvm-svn: 105439
2010-06-04 00:04:02 +00:00
a733daf18c
Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.
...
Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass. Some of
these constraints can be relaxed with a bit more work. Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.
llvm-svn: 105437
2010-06-03 23:53:58 +00:00
01edd68225
Cleanup 80-column and trim trailing whitespace
...
llvm-svn: 105435
2010-06-03 23:49:57 +00:00
b30b81edb6
Teach the ARM load-store optimizer to deal with dbg_value instructions.
...
llvm-svn: 105427
2010-06-03 22:41:15 +00:00
d679ff7330
Early implementation of tail call for ARM.
...
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
d83e3e7750
Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
...
needs to demand the high bits because it's asserting that they're zero.
llvm-svn: 105406
2010-06-03 20:21:33 +00:00
30093b5d8b
Revert 105308.
...
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
f82aea634c
Machine sink could potentially sink instructions into a block where the physical
...
registers it defines then interfere with an existing preg live range.
For instance, if we had something like these machine instructions:
BB#0
... = imul ... EFLAGS<imp-def,dead>
test ..., EFLAGS<imp-def>
jcc BB#2 EFLAGS<imp-use>
BB#1
... ; fallthrough to BB#2
BB#2
... ; No code that defines EFLAGS
jcc ... EFLAGS<imp-use>
Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).
The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.
llvm-svn: 105387
2010-06-03 07:54:20 +00:00
b0e1a458ce
Add first pass at darwin tls compiler support.
...
llvm-svn: 105381
2010-06-03 04:07:48 +00:00
f67fe3b1e8
One underscore, not two.
...
llvm-svn: 105379
2010-06-03 04:02:59 +00:00
dbbbf73c96
Implement expansion in type legalization for add/sub with overflow. The
...
expansion is the same as that used by LegalizeDAG.
The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.
llvm-svn: 105378
2010-06-03 03:49:50 +00:00
ceb13f2af3
Remove some already-fixed README entries.
...
llvm-svn: 105377
2010-06-03 01:47:31 +00:00
a59b7a72b9
Remove README entry which no longer compiles to something sane.
...
llvm-svn: 105376
2010-06-03 01:16:51 +00:00
1f41303260
Remove a fixed item, update a couple partially-fixed items.
...
llvm-svn: 105375
2010-06-03 01:01:48 +00:00
4029596f93
Use the fast register allocator by default for -O0 builds.
...
This affects both llvm-gcc and clang.
llvm-svn: 105372
2010-06-03 00:39:06 +00:00
818e4df2b4
Use readsWritesVirtualRegister instead of counting uses and defs when inserting
...
spills and reloads.
This means that a partial define of a register causes a reload so the other
parts of the register are preserved.
The reload can be prevented by adding an <imp-def> operand for the full
register. This is already done by the coalescer and live interval analysis where
relevant.
llvm-svn: 105369
2010-06-03 00:07:47 +00:00
42c642cd24
Add full register <imp-def> operands when the coalescer is creating partial
...
register updates.
These operands tell the spiller that the other parts of the partially defined
register are don't-care, and a reload is not necessary.
llvm-svn: 105361
2010-06-02 23:22:11 +00:00
df84e8baf7
Speedup bitcode writer. Do not walk all values for all functions to emit function local metadata. In one testcase, probably worst case scenario, the 70x speed up is seen.
...
llvm-svn: 105360
2010-06-02 23:05:04 +00:00
7ee730eb40
Compulsive reformating. No functionalitical changes.
...
llvm-svn: 105359
2010-06-02 23:04:26 +00:00
a8ad97743d
Slightly change the meaning of the reMaterialize target hook when the original
...
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
llvm-svn: 105358
2010-06-02 22:47:25 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
f2dffcef82
Remove the TargetRegisterClass member from CalleeSavedInfo
...
llvm-svn: 105344
2010-06-02 20:02:30 +00:00
6e3d5af945
Fix comment so it doesn't include comments which are irrelevant to the x86
...
backend. Add a FIXME noting what can be fixed here.
llvm-svn: 105342
2010-06-02 19:35:46 +00:00
a690618c58
Use comments to document non-obvious code rather than
...
mailing list archives.
llvm-svn: 105341
2010-06-02 19:13:40 +00:00
c2254f6b98
Skip identical instruction while calculating DBG_VALUE range.
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llvm-svn: 105340
2010-06-02 19:05:13 +00:00
2d35a9e810
Rename canCombinedSubRegIndex method to something more grammatically correct
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and tidy up the comment describing it.
llvm-svn: 105339
2010-06-02 18:54:47 +00:00
94801a47f8
Replace ARM's getCalleeSavedRegClasses with a simpler solution
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llvm-svn: 105335
2010-06-02 17:54:50 +00:00
21ccf05b4c
Use local small vector.
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llvm-svn: 105332
2010-06-02 16:42:51 +00:00
7881a64a50
Remove unused function.
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llvm-svn: 105325
2010-06-02 15:44:20 +00:00
848548300d
Not all entries in the range will have an SUnit. Check for that when looking
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for debug information.
llvm-svn: 105324
2010-06-02 15:29:36 +00:00
ef2b6ce00a
cleanup
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llvm-svn: 105322
2010-06-02 13:53:17 +00:00
c08ecba597
Remove uses of getCalleeSavedRegClasses from outside the
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backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
llvm-svn: 105321
2010-06-02 12:39:06 +00:00
a2da22734f
Enable machine cse of instructions which define physical registers.
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llvm-svn: 105308
2010-06-02 01:08:27 +00:00
526e6d045f
Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
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x86 backend currently doesn't know how to handle them.
This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either. We do get a better error message, though.
llvm-svn: 105305
2010-06-02 00:27:18 +00:00
f4a34b97b8
Fix an obvious mistake: don't change the operands until all of them have been
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checked and it is safe to proceed with the changes.
llvm-svn: 105304
2010-06-02 00:16:08 +00:00
6382c9c681
Remove outdated README entries.
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llvm-svn: 105303
2010-06-02 00:10:36 +00:00
12ac8f0352
Update debug information when breaking anti-dependencies. rdar://7759363
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llvm-svn: 105300
2010-06-01 23:48:44 +00:00
7b0ac865a4
Properly compose subregister indices when coalescing.
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The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.
llvm-svn: 105294
2010-06-01 22:39:25 +00:00
5ba76b94f8
Remove unused code
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llvm-svn: 105293
2010-06-01 21:56:30 +00:00
d43e0ca916
Ignore line number of debug value in undefined register.
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llvm-svn: 105292
2010-06-01 21:43:09 +00:00
0e20dc5cd6
fix think-o
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llvm-svn: 105291
2010-06-01 21:35:50 +00:00
47a0724425
Fix the allocation of shadow space for the Win64 calling convention
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in X86FastISel. Patch by Jan Sjodin.
llvm-svn: 105290
2010-06-01 21:09:47 +00:00
b69c68742a
Simplify things a bit more. Fix prototype to use SmallVectorImpl and
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change a few SmallVectors to vanilla C arrays.
llvm-svn: 105289
2010-06-01 21:06:46 +00:00
49a372cebc
Fix the noalias checking so that it doesn't worry about
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an argument aliasing itself. Thanks Duncan!
llvm-svn: 105288
2010-06-01 20:51:40 +00:00
b0c76394a3
Keep track of incoming debug value of unused argument.
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Radar 7927666.
llvm-svn: 105285
2010-06-01 19:59:01 +00:00
b782caa393
Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
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llvm-svn: 105283
2010-06-01 18:35:14 +00:00
b24d5c6ce2
Add a FIXME
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llvm-svn: 105282
2010-06-01 18:06:35 +00:00
a37af16221
mirror of r105280 changes for LowerInvoke, which uses the same basic logic here
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llvm-svn: 105281
2010-06-01 18:04:56 +00:00
74d8345512
When processing function arguments when splitting live ranges across invokes,
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handle structs passed by value via an extract/insert pair, as a bitcast
won't work on a struct. rdar://7742824
llvm-svn: 105280
2010-06-01 18:04:09 +00:00
7352167560
Use SmallVector instead of std::vector.
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llvm-svn: 105279
2010-06-01 17:56:41 +00:00
d44677ba69
Refactor some SSE 2 unpack instructions
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llvm-svn: 105276
2010-06-01 17:02:50 +00:00
a76715fc88
Don't call flush() at a library level which isn't checking for errors
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and doesn't know where the output is going.
llvm-svn: 105274
2010-06-01 16:31:34 +00:00
8916358f97
Fix handling of 'load' nodes.
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llvm-svn: 105269
2010-06-01 13:34:47 +00:00
4c904fa797
Fix PR7272: when inlining through a callsite with byval arguments,
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the newly created allocas may be used by inlined calls, so these
need to have their tail call flags cleared. Fixes PR7272.
llvm-svn: 105255
2010-05-31 21:00:26 +00:00
14c46517b5
fix PR6623: when optimizing for size, don't inline memcpy/memsets
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that are too large. This causes the freebsd bootloader to be too
large apparently.
It's unclear if this should be an -Os or -Oz thing. Thoughts welcome.
llvm-svn: 105228
2010-05-31 17:30:14 +00:00
b4a773b452
the 'limit' argument to FindOptimalMemOpLowering is unsigned, not uint64_t.
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llvm-svn: 105226
2010-05-31 17:12:23 +00:00
5ac57e3440
Avoid swap when a copy suffices.
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llvm-svn: 105220
2010-05-31 12:50:41 +00:00
aee2632be3
The memcpy intrinsic only takes i8* for %src and %dst, so cast them to that
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first. Fixes PR7265.
llvm-svn: 105206
2010-05-31 06:16:35 +00:00
a97311f152
Use `llvm::next' instead of `next' to make VC++ 2010 happy.
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llvm-svn: 105168
2010-05-30 13:14:21 +00:00
a09d95412e
Some A9 load/store cleanups
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llvm-svn: 105109
2010-05-29 19:25:39 +00:00
2a21aef8f2
Some rough approximations for load/stores on A9
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llvm-svn: 105108
2010-05-29 19:25:34 +00:00
d4c7cceb70
NEON/VFP stuff can be issued only via Pipe1 on A9
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llvm-svn: 105107
2010-05-29 19:25:29 +00:00
94d7fd88fd
Add some integer instruction itineraries for A9
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llvm-svn: 105106
2010-05-29 19:25:17 +00:00
4db93c9700
Reorder some code in SelectionDAGBuilder.
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llvm-svn: 105105
2010-05-29 17:53:24 +00:00
d16aa541af
SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue
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shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.
llvm-svn: 105101
2010-05-29 17:03:36 +00:00
c488e92f0b
Remove unused function.
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llvm-svn: 105100
2010-05-29 14:03:51 +00:00
707b7cc429
Remove schedule-livein-copies. It's not being used.
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llvm-svn: 105095
2010-05-29 02:23:39 +00:00
27c4933e02
Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
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llvm-svn: 105092
2010-05-29 01:35:22 +00:00
ab6223949e
Handle composed subreg indices when processing REQ_SEQUENCE instructions.
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llvm-svn: 105066
2010-05-29 00:14:14 +00:00
032f3261a2
Doh. Machine LICM is re-initializing the CSE map over and over. Patch by Anna Zaks. rdar://8037934.
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llvm-svn: 105065
2010-05-29 00:06:36 +00:00
e02996ca8f
Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
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were overspecified when inheriting sub-subregisters, for instance:
R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.
This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.
llvm-svn: 105063
2010-05-28 23:48:29 +00:00
cc2efe11db
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
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llvm-svn: 105061
2010-05-28 23:26:21 +00:00
bf91499f1a
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
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llvm-svn: 105060
2010-05-28 23:25:23 +00:00
e8be73f3e7
Fix comment typos.
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llvm-svn: 105059
2010-05-28 23:24:28 +00:00
1f79289806
More SSE 1 & 2 merge, this time with logical instructions
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llvm-svn: 105014
2010-05-28 22:47:03 +00:00
34709d06c0
Fix AliasDebugger to be aware of operand values too.
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llvm-svn: 105012
2010-05-28 22:31:51 +00:00
0fa67e479a
Add lint checks for function attributes.
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llvm-svn: 105009
2010-05-28 21:43:57 +00:00
0d7f3b8195
Split the logic behind CastInst::isNoopCast into a separate static function,
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as is done with most other cast opcode predicates.
llvm-svn: 105008
2010-05-28 21:41:37 +00:00
4c71e08ed8
MC/X86: Add alias for movzx.
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llvm-svn: 105005
2010-05-28 21:20:21 +00:00
b29228905f
MC/X86: Add alias for fwait.
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llvm-svn: 105001
2010-05-28 20:59:10 +00:00
76413597a9
Fix the use of x86 control and debug registers so that the assertion failure in
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getX86RegNum() does not happen. Patch by Shantonu Sen!
llvm-svn: 104994
2010-05-28 19:01:27 +00:00
64824ea99f
Add a TargetRegisterInfo::composeSubRegIndices hook with a default
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implementation that is correct for most targets. Tablegen will override where
needed.
Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.
llvm-svn: 104985
2010-05-28 18:18:53 +00:00
b342e09b5e
correct retattr
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llvm-svn: 104980
2010-05-28 18:03:48 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
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llvm-svn: 104974
2010-05-28 17:51:20 +00:00
c575ec61ea
Fix lint's memcpy and memmove checks, and its basic block traversal.
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llvm-svn: 104970
2010-05-28 17:44:00 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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llvm-svn: 104967
2010-05-28 17:37:40 +00:00
fb85820f9a
Minor code simplification.
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llvm-svn: 104959
2010-05-28 16:50:23 +00:00
feaeb36edf
Fix a redundant-return warning.
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llvm-svn: 104958
2010-05-28 16:50:01 +00:00
862f034188
Detect self-referential values.
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llvm-svn: 104957
2010-05-28 16:45:33 +00:00
c1e216583f
Revert 104841, 104842, 104876 due to buildbot failures. Radar 7424645.
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llvm-svn: 104953
2010-05-28 16:41:07 +00:00
cef9fc37f4
Eli pointed out that va_arg instruction result values don't
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reference the stack.
llvm-svn: 104951
2010-05-28 16:34:49 +00:00
54d7aaa819
Teach lint how to look through simple store+load pairs and other
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effective no-op constructs, to make it more effective on
unoptimized IR.
llvm-svn: 104950
2010-05-28 16:21:24 +00:00
826bdf8c10
Move FindAvailableLoadedValue isSafeToLoadUnconditionally out of
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lib/Transforms/Utils and into lib/Analysis so that Analysis passes
can use them.
llvm-svn: 104949
2010-05-28 16:19:17 +00:00
a3b6c4b529
ConstantFoldConstantExpression can theoretically return null.
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llvm-svn: 104948
2010-05-28 16:12:08 +00:00
df5d7dcef1
Teach instcombine to promote alloca array sizes.
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llvm-svn: 104945
2010-05-28 15:09:00 +00:00
ddba4b725a
Add a lint check for returning the address of stack memory.
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llvm-svn: 104936
2010-05-28 04:33:42 +00:00
05a6555acb
Fix instcombine's handling of alloca to accept non-i32 types.
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llvm-svn: 104935
2010-05-28 04:33:04 +00:00
9da5bb0756
Bitcode support for allocas with arbitrary array size types.
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llvm-svn: 104915
2010-05-28 01:38:28 +00:00
3e0fbafab2
Fix typo.
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llvm-svn: 104914
2010-05-28 01:29:50 +00:00
e2099e8088
Fix typo.
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llvm-svn: 104913
2010-05-28 01:17:51 +00:00
2140a74979
Eliminate the restriction that the array size in an alloca must be i32.
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This will help reduce the amount of casting required on 64-bit targets.
llvm-svn: 104911
2010-05-28 01:14:11 +00:00
b6112e8706
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
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the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
llvm-svn: 104907
2010-05-28 00:27:15 +00:00
b613ae2c89
Add a -regalloc=default option that chooses a register allocator based on the -O
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optimization level.
This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.
llvm-svn: 104904
2010-05-27 23:57:25 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c2ebe0334a
Use report_fatal_error, not llvm_unreachable.
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llvm-svn: 104899
2010-05-27 23:45:31 +00:00
c9f532dddc
back out 104862/104869. Can reuse stacksave after all. Very cool.
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llvm-svn: 104897
2010-05-27 23:11:57 +00:00
288999b829
Factor out the handler work from SignalHandler into a helper function,
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and change llvm::sys::RunInterruptHandlers to call that function directly
instead of calling SignalHandler, because the rest of SignalHandler
invokes side effects which aren't appropriate, including raising the
signal.
llvm-svn: 104896
2010-05-27 23:11:55 +00:00
3d3ee87d4e
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
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llvm-svn: 104891
2010-05-27 22:08:38 +00:00
9738f64bd9
MC/X86: Add aliases for Jcc variants.
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llvm-svn: 104890
2010-05-27 21:33:19 +00:00
6debf89587
Eliminate some unnessary Path::exists() calls.
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llvm-svn: 104888
2010-05-27 20:51:54 +00:00
a880546c65
Don't flush the raw_ostream in llvm::WriteBitcodeToFile; it's at
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the wrong level. Clients which need to leave the stream open but
which still require the bitcode bits to be on disk should call
flush themselves.
llvm-svn: 104885
2010-05-27 20:26:51 +00:00
7a9dedf0ab
Do not drop location info for inlined function args.
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llvm-svn: 104884
2010-05-27 20:25:04 +00:00
40e62dfdc0
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
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should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
llvm-svn: 104883
2010-05-27 20:23:42 +00:00
9e43c07bc5
Mark some math lib intrinsic nodes Legal on SSE4.1.
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No functional effect as these nodes are not generated yet.
llvm-svn: 104879
2010-05-27 20:12:41 +00:00
d9225cee20
Don't special-case stdout in llvm::WriteBitcodeToFile; just consider
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it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.
llvm-svn: 104878
2010-05-27 20:06:51 +00:00
f162eace49
Teach instCombine to remove malloc+free if malloc's only uses are comparisons
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to null. Patch by Matti Niemenmaa.
llvm-svn: 104871
2010-05-27 19:09:06 +00:00
b68dfb45f5
hook ISD::STACKADDR to an intrinsic
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llvm-svn: 104869
2010-05-27 18:52:11 +00:00
dc53f1cb5c
FastISel doesn't yet handle callee-pop functions.
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To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
2010-05-27 18:43:40 +00:00
5cde219fb1
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
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to update the jmpbuf in the presence of VLAs.
llvm-svn: 104862
2010-05-27 18:23:48 +00:00
54b07ad2cd
Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring
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common code between SSE versions.
llvm-svn: 104860
2010-05-27 18:17:40 +00:00
c36b1f35f0
Add basic error checking to MemoryBuffer::getSTDIN.
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llvm-svn: 104855
2010-05-27 17:31:51 +00:00
ece4bf5148
Use the return value of getMagicNumber instead of using a
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separate canRead() call.
llvm-svn: 104853
2010-05-27 17:18:38 +00:00
78d1e84521
Don't bother clearing the Magic string when the magic number
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can't be read, since it isn't cleared on other error paths.
llvm-svn: 104852
2010-05-27 17:14:10 +00:00
16f4bd8140
Don't bother checking canRead() before calling getMagicNumber();
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getMagicNumber() does its own error checking.
llvm-svn: 104851
2010-05-27 17:12:23 +00:00
5e6b71ce34
inlined function's arguments need a label to mark the start point because they are not directly attached to current function.
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llvm-svn: 104848
2010-05-27 16:47:30 +00:00
8e99e50d08
Support for nested functions/classes in debug output. Radar 7424645.
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llvm-svn: 104841
2010-05-27 16:16:54 +00:00
eaddfac539
Rearrange conditionals so we don't get caught with the correct type as wrong.
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llvm-svn: 104793
2010-05-27 00:52:31 +00:00
6b9a9fe207
Simplify. Eliminate unneeded debug_loc entry.
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llvm-svn: 104785
2010-05-26 23:55:23 +00:00
d67defdfe2
Avoid counting InlineAsm as a call - it prevents loop unrolling.
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PR7026
Patch by Pekka Jääskeläinen!
llvm-svn: 104780
2010-05-26 22:40:28 +00:00
084bcb1322
Fix Lint printing warnings multiple times. Remove the ErrorStr
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option from lintModule, which was an artifact from being
based on Verifier code.
llvm-svn: 104765
2010-05-26 22:28:53 +00:00
c0b69020cd
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
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to be matched.
llvm-svn: 104757
2010-05-26 22:21:28 +00:00
a20a5cd24f
Reinstate checking of stackrestore, with checking for both Read
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and Write, and add a comment explaining this.
llvm-svn: 104756
2010-05-26 22:21:25 +00:00
4f6da9e3a8
Give SubRegIndex names to all ARM subregisters. This will be required by
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TableGen shortly.
llvm-svn: 104754
2010-05-26 22:15:03 +00:00
996bc42a26
Stackrestore is not a load.
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llvm-svn: 104752
2010-05-26 22:00:10 +00:00
ddee3cb163
Add FIXME comment to remove this.
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llvm-svn: 104749
2010-05-26 21:53:50 +00:00
c96c6db59d
Remove a TODO which isn't practical.
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llvm-svn: 104748
2010-05-26 21:50:41 +00:00
b33dfbcba4
MC: Add TargetMachine support for setting the value of MCRelaxAll with
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-filetype=obj.
llvm-svn: 104747
2010-05-26 21:48:55 +00:00
d1d7ed63ff
Add StringRef::compare_numeric and use it to sort TableGen register records.
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This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
llvm-svn: 104745
2010-05-26 21:47:28 +00:00
1249adf160
Implement checking of the tail keyword.
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llvm-svn: 104744
2010-05-26 21:46:36 +00:00
acc32a5c19
There is no need to force an line number entry (using previous location) for a temp label at unknown location.
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llvm-svn: 104740
2010-05-26 21:23:46 +00:00
27311269cb
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
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usual suspects that could "return twice".
llvm-svn: 104737
2010-05-26 20:39:00 +00:00
b889fc987e
MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments.
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llvm-svn: 104736
2010-05-26 20:37:03 +00:00
9d40ef162b
MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment.
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llvm-svn: 104735
2010-05-26 20:37:00 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
1b08572a66
Update debug info when live-in reg is copied into a vreg.
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llvm-svn: 104732
2010-05-26 20:18:50 +00:00
70e34983e8
Fix the x86 move to/from segment register instructions.
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llvm-svn: 104731
2010-05-26 20:10:45 +00:00
0c3bfd3fb0
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
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more than just the stack slot coloring algorithm.
llvm-svn: 104722
2010-05-26 19:46:12 +00:00
002d54ddc9
Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().
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llvm-svn: 104720
2010-05-26 19:37:24 +00:00
52c2738324
Eliminate the use of PriorityQueue and just use a std::vector,
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implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
llvm-svn: 104718
2010-05-26 18:52:00 +00:00
1e5d0b0456
Delete an unused function.
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llvm-svn: 104716
2010-05-26 18:34:12 +00:00
7c8bd0fc98
MC: Change RelaxInstruction to only take the input and output instructions.
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llvm-svn: 104713
2010-05-26 18:15:06 +00:00
338674a323
Fix a typo in a comment that Gabor noticed.
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llvm-svn: 104711
2010-05-26 18:03:53 +00:00
388ff9b1a2
MC: Eliminate an unnecessary copy.
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llvm-svn: 104709
2010-05-26 17:50:16 +00:00
a19838e107
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
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before encoding.
llvm-svn: 104707
2010-05-26 17:45:29 +00:00
95fcc96752
Remove dead code.
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llvm-svn: 104706
2010-05-26 17:42:50 +00:00
5a5e0bc3b5
Do not construct location list backword!
...
llvm-svn: 104705
2010-05-26 17:29:32 +00:00
7de379467e
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
2010-05-26 17:27:12 +00:00
b34440a6a8
MC: Eliminate MCAsmFixup, replace with MCFixup.
...
llvm-svn: 104699
2010-05-26 15:18:56 +00:00
353a91ff76
MC: Use accessors for access to MCAsmFixup.
...
llvm-svn: 104697
2010-05-26 15:18:31 +00:00
3627af5da4
MC: Change MCInst::dump_pretty to not include a trailing newline.
...
llvm-svn: 104696
2010-05-26 15:18:13 +00:00
6877119ef3
Kill unneeded SExt.
...
llvm-svn: 104692
2010-05-26 09:45:04 +00:00
730a977e02
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
...
llvm-svn: 104691
2010-05-26 08:10:02 +00:00
870e5759e7
MC: Eliminate MCFragment vtable, which was unnecessary.
...
llvm-svn: 104689
2010-05-26 06:50:57 +00:00
c4376b9b1b
Coding style change (Adding 1 missing space.)
...
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
0568ca0ddc
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
llvm-svn: 104667
2010-05-26 03:21:39 +00:00
e805ea9e39
Temporarily revert r104655 as it's breaking the bots.
...
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
50eec620f4
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
...
This reverts commit 104654.
llvm-svn: 104660
2010-05-26 01:21:14 +00:00
7c00576a62
Change push_all to a non-virtual function and implement it in the
...
base class, since all the implementations are the same.
llvm-svn: 104659
2010-05-26 01:10:55 +00:00
3701b3928e
Trim #include.
...
llvm-svn: 104657
2010-05-26 00:55:59 +00:00
c5222d6c38
Dale and Evan suggested putting the "check for setjmp" much earlier in the
...
machine code generation. That's a good idea, so I made it so.
llvm-svn: 104655
2010-05-26 00:32:40 +00:00
0b0274524c
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
2010-05-26 00:28:19 +00:00
b6e0bc9457
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
llvm-svn: 104653
2010-05-26 00:25:05 +00:00
e22abfa823
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
llvm-svn: 104652
2010-05-26 00:02:28 +00:00
e7b64dcc1e
Start adding mach-o tls reloc support.
...
llvm-svn: 104651
2010-05-26 00:02:12 +00:00
66c939a2ca
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
...
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
9fc11706e3
First cut at supporting .debug_loc section.
...
This is used to track variable information.
llvm-svn: 104649
2010-05-25 23:40:22 +00:00
9439084cea
Properly promote operands when optimizing a single-character memcmp.
...
llvm-svn: 104648
2010-05-25 22:53:43 +00:00
388f638511
Constify function.
...
llvm-svn: 104646
2010-05-25 22:02:22 +00:00
ce3269b815
Do one map lookup instead of two.
...
llvm-svn: 104645
2010-05-25 21:59:42 +00:00
a4abd035ea
Fix a missing newline in debug output.
...
llvm-svn: 104644
2010-05-25 21:50:35 +00:00
f3925438e5
Move the verbose asm output up a bit so it can be used in the special cases
...
as well.
llvm-svn: 104642
2010-05-25 21:49:43 +00:00
b04ef0cfbc
Okay, bear with me here...
...
If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
llvm-svn: 104640
2010-05-25 21:44:26 +00:00
19a4b843cc
Add support for initialized global data for darwin tls. Update comments
...
and testcases accordingly.
llvm-svn: 104635
2010-05-25 21:28:50 +00:00
492d4f409a
Changed the encoding of X86 floating point stack operations where both operands
...
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
2010-05-25 20:52:34 +00:00
3311eb50d7
Separate unrelated cases that once shared a numeric value
...
llvm-svn: 104629
2010-05-25 19:49:40 +00:00
1ad0d5e25b
Print symbolic SubRegIndex names on machine operands.
...
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
673e7e0f37
Remove NumberHack entirely.
...
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
2010-05-25 19:49:33 +00:00
0e767d7364
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
...
llvm-svn: 104626
2010-05-25 19:49:32 +00:00
60fe2cdc4f
Fix another variant of PR 7191. Also add a testcase
...
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
llvm-svn: 104624
2010-05-25 18:47:23 +00:00
4a5b2c597b
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
...
llvm-svn: 104622
2010-05-25 18:40:53 +00:00
c798965e63
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
llvm-svn: 104621
2010-05-25 18:16:58 +00:00
ff384ad981
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
...
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
llvm-svn: 104619
2010-05-25 17:50:03 +00:00
f6562d35ac
Make sure aeskeygenassist uses an unsigned immediate field.
...
Fixes rdar://8017638
llvm-svn: 104617
2010-05-25 17:33:22 +00:00
3b59e0601e
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
...
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
llvm-svn: 104615
2010-05-25 17:21:04 +00:00
36caaf1c59
Use enums instead of literals for SystemZ subregisters
...
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
396c8802b2
Use enums instead of literals for X86 subregisters.
...
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
llvm-svn: 104611
2010-05-25 17:04:16 +00:00
a6714e8a43
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
2da5aa1b60
Add support to MOVimm32 using movt/movw for ARM JIT
...
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
26fdebcae9
Clean up indentation.
...
llvm-svn: 104580
2010-05-25 03:36:52 +00:00
adff18518a
Disable invalid coalescer assertion.
...
llvm-svn: 104574
2010-05-25 00:15:18 +00:00
70affbd988
Use enums instead of literals in the ARM backend.
...
llvm-svn: 104573
2010-05-25 00:15:15 +00:00
0b7488e8d5
Print out the name of the function during SSC.
...
llvm-svn: 104572
2010-05-24 23:16:04 +00:00
fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
...
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
1181a19318
Lose the dummies
...
llvm-svn: 104564
2010-05-24 21:47:01 +00:00
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
...
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
1b79babdec
Avoid adding duplicate function live-in's.
...
llvm-svn: 104560
2010-05-24 21:33:37 +00:00
79b6a0f140
Fix an mmx movd encoding.
...
llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
...
llvm-svn: 104549
2010-05-24 20:32:23 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
51b37e0bd8
Do not emit line number entries for unknown debug values.
...
This fixes recent regression in store.exp from gdb testsuite.
llvm-svn: 104524
2010-05-24 18:26:49 +00:00
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
...
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
...
never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
8a57aeca2a
Use SubRegIndex in SystemZ.
...
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
5d56769fb6
SubRegIndex'ize Mips
...
llvm-svn: 104514
2010-05-24 17:42:58 +00:00
fd6f16fab9
SubRegIndex'ize MSP430
...
llvm-svn: 104513
2010-05-24 17:42:55 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
9340ea59e1
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
c5327226e4
Encode the Caml frametable by following what the comment says: the number of descriptors
...
is first emitted, and StackOffsets are emitted in 16 bits.
llvm-svn: 104488
2010-05-24 12:24:11 +00:00
6738a2e39e
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104467
2010-05-23 18:36:38 +00:00
8271d1bb4a
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104466
2010-05-23 18:36:34 +00:00
3ff1a06de6
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
...
llvm-svn: 104463
2010-05-23 17:44:06 +00:00
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
...
llvm-svn: 104455
2010-05-23 05:42:31 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
...
llvm-svn: 104435
2010-05-22 06:37:33 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
...
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
...
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
6fdea1bda8
Add full bss data support for darwin tls variables.
...
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
...
llvm-svn: 104412
2010-05-22 00:04:14 +00:00
61438fe064
Clean up extra whitespace.
...
llvm-svn: 104410
2010-05-21 23:53:55 +00:00
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
...
Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
4dc833c607
add a note
...
llvm-svn: 104404
2010-05-21 23:16:21 +00:00
09d47031b1
Expand on comment.
...
llvm-svn: 104396
2010-05-21 23:03:53 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
...
llvm-svn: 104394
2010-05-21 23:01:38 +00:00
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
...
llvm-svn: 104385
2010-05-21 21:22:19 +00:00
3dca28d0e2
Fix section attribute name.
...
llvm-svn: 104381
2010-05-21 21:08:52 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
...
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
...
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
7d7f604321
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
...
reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
llvm-svn: 104372
2010-05-21 20:02:01 +00:00
1782aae355
Simplify
...
llvm-svn: 104338
2010-05-21 18:49:09 +00:00
2b78565842
Previous commit message should refer to 104308.
...
llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
...
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
...
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
...
llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
...
llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
...
eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
...
llvm-svn: 104326
2010-05-21 17:49:07 +00:00
a81e1cab04
constify accessor.
...
llvm-svn: 104325
2010-05-21 17:47:50 +00:00
b4e1687270
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
...
This reverts r104322. I think it was causing miscompilations.
llvm-svn: 104323
2010-05-21 17:36:32 +00:00
8e8e090301
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
...
This correctly handles partial redefines and undef uses.
llvm-svn: 104322
2010-05-21 16:42:30 +00:00
a648c6a757
Teach VirtRegRewriter to handle spilling in instructions that have multiple
...
definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
llvm-svn: 104321
2010-05-21 16:36:13 +00:00
1f3801062d
If the first definition of a virtual register is a partial redef, add an
...
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
llvm-svn: 104320
2010-05-21 16:32:16 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
...
isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
...
differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
ec9d6faef0
Add support for parsing the ELF .type assembler directive.
...
llvm-svn: 104316
2010-05-21 11:36:59 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
...
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
...
llvm-svn: 104307
2010-05-21 00:43:17 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
...
llvm-svn: 104306
2010-05-21 00:42:32 +00:00
fbd6c45e06
Simplify.
...
llvm-svn: 104302
2010-05-21 00:10:20 +00:00
c120ffe3f6
Fix __crashreport_info__ declaration.
...
llvm-svn: 104300
2010-05-20 23:50:19 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
...
llvm-svn: 104293
2010-05-20 23:26:43 +00:00
9b48b856ea
DominatorTree.getNode can return null for unreachable blocks.
...
llvm-svn: 104290
2010-05-20 22:46:54 +00:00
86110fa2bb
Minor code cleanups.
...
llvm-svn: 104287
2010-05-20 22:25:20 +00:00
3a48292204
Print a space after the colon.
...
llvm-svn: 104279
2010-05-20 21:11:37 +00:00
6295f2ebb8
Make Solve check its own post-condition, to reduce clutter in the
...
top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
a4ca28a3ae
Add comments.
...
llvm-svn: 104276
2010-05-20 20:52:00 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
...
llvm-svn: 104275
2010-05-20 20:36:29 +00:00
0adee9b362
Rename variable. add comment.
...
llvm-svn: 104274
2010-05-20 20:35:24 +00:00
927bcaadda
More code cleanups. Use iterators instead of indices when indices
...
aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
...
llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
...
llvm-svn: 104271
2010-05-20 20:20:35 +00:00
4c4043cf34
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
...
Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
llvm-svn: 104269
2010-05-20 20:05:31 +00:00
8ec018cedf
Add some comments.
...
llvm-svn: 104268
2010-05-20 20:00:41 +00:00
8ce95cc3c5
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
...
llvm-svn: 104267
2010-05-20 20:00:25 +00:00
490c8ab76d
Refactor.
...
llvm-svn: 104265
2010-05-20 19:57:06 +00:00
141791c6d1
Grammar fix. This is a test commit.
...
llvm-svn: 104264
2010-05-20 19:45:09 +00:00
ab5fb7f559
Minor code cleanups.
...
llvm-svn: 104263
2010-05-20 19:44:23 +00:00
ee2fea3cd7
When canonicalizing icmp operand order to put the loop invariant
...
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
llvm-svn: 104262
2010-05-20 19:26:52 +00:00
3e69aa0399
llvmc: Make segfault detection work on Win32.
...
llvm-svn: 104261
2010-05-20 19:23:47 +00:00
fdf9874ba7
Set Changed to true when canonicalizing ICmp operand order; even though
...
it isn't a very interesting change, it's a change nonetheless.
llvm-svn: 104260
2010-05-20 19:16:03 +00:00
5954994bba
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
...
This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
63d4f68df4
Remove dbg_value workaround and associated command line option
...
llvm-svn: 104254
2010-05-20 18:34:01 +00:00
098a47931c
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
...
have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
d7d6638e3e
The PPC MFCR instruction implicitly uses all 8 of the CR
...
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
e2ff7f3a7d
Strip llvm.dbg.lv also.
...
llvm-svn: 104236
2010-05-20 16:49:22 +00:00
981563d0ba
Rename a variable to avoid shadowing.
...
llvm-svn: 104234
2010-05-20 16:41:11 +00:00
e1c53f29d3
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
...
llvm-svn: 104233
2010-05-20 16:36:41 +00:00
6b733fc189
Minor code simplification.
...
llvm-svn: 104232
2010-05-20 16:23:28 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
...
instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
5238275478
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
...
16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
80a9608442
Move the code for deleting BaseRegs and LSRUses into helper functions,
...
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
llvm-svn: 104225
2010-05-20 15:17:54 +00:00
7c3e230cd1
Reduce string trashing.
...
llvm-svn: 104223
2010-05-20 14:14:22 +00:00
bdd062dae0
Add a hybrid bottom up scheduler that reduce register usage while avoiding
...
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
c53cc4f8bf
Fix typo in comment.
...
llvm-svn: 104209
2010-05-20 03:30:09 +00:00
1e19eab963
Define the x86 pause instruction.
...
llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
...
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
27e7ffc7d4
Partial code for emitting thread local bss data.
...
llvm-svn: 104197
2010-05-20 00:49:07 +00:00
20fab456da
Teach LSR how to cope better with unrolled loops on targets where
...
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
llvm-svn: 104186
2010-05-19 23:43:12 +00:00
42603958fb
Optimize away insertelement of an undef value. This shows up in
...
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
7cbfa4462f
fix rdar://7986634 - match instruction opcodes case insensitively.
...
llvm-svn: 104183
2010-05-19 23:34:33 +00:00
f98511473e
Enable preserving debug information through post-RA scheduling
...
llvm-svn: 104175
2010-05-19 22:57:47 +00:00
604560c5fe
Fix the post-RA instruction scheduler to handle instructions referenced by
...
more than one dbg_value instruction. rdar://7759363
llvm-svn: 104174
2010-05-19 22:57:06 +00:00
70e506e18a
Code clean up.
...
llvm-svn: 104173
2010-05-19 22:42:23 +00:00
a08130864e
Revert r104165.
...
llvm-svn: 104172
2010-05-19 21:58:28 +00:00
e0eddb21f5
Add support for partial redefs to the fast register allocator.
...
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
llvm-svn: 104167
2010-05-19 21:36:05 +00:00
0fe341e2e2
There is no need to maintain InsnsBeginScopeSet separately.
...
llvm-svn: 104165
2010-05-19 21:26:53 +00:00
5d4c134a94
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
...
partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
llvm-svn: 104149
2010-05-19 20:36:22 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
...
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
e11cdf8cc8
TwoAddressInstructionPass doesn't really know how to merge live intervals when
...
lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
llvm-svn: 104146
2010-05-19 20:08:00 +00:00
59a61fd7cc
llvmc: report an error if a child process segfaults.
...
llvm-svn: 104145
2010-05-19 19:24:32 +00:00
6a1bfd282b
When expanding a vector_shuffle, the element type may not be legal and may
...
need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
llvm-svn: 104141
2010-05-19 18:48:32 +00:00
52e37becf6
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
...
llvm-svn: 104122
2010-05-19 17:20:58 +00:00
d2f78e755f
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
...
prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
llvm-svn: 104120
2010-05-19 15:26:43 +00:00
b243dfb085
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
...
CALL64pcrel32, for the same reason.
llvm-svn: 104116
2010-05-19 08:07:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
...
llvm-svn: 104114
2010-05-19 07:26:50 +00:00
4f6c7c6d94
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
...
llvm-svn: 104112
2010-05-19 06:20:44 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
...
llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
...
avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
744c96dd48
Add a comment explaining why this code uses Append mode.
...
llvm-svn: 104095
2010-05-19 01:21:34 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
...
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
...
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
beebef4137
Add a comment.
...
llvm-svn: 104089
2010-05-18 23:55:57 +00:00
50f8f2c23d
Fix the predicate which checks for non-sensical formulae which have
...
constants in registers which partially cancel out their immediate fields.
llvm-svn: 104088
2010-05-18 23:48:08 +00:00
4cf99b5303
Factor out the code for recomputing an LSRUse's Regs set after some
...
of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
llvm-svn: 104087
2010-05-18 23:42:37 +00:00
055c01d9dc
Fix a crash when debugging the coalescer. DebugValue instructions are not
...
in the coalescer's instruction map.
llvm-svn: 104086
2010-05-18 23:19:42 +00:00
a4eca05174
Factor out code for estimating search space complexity into a helper
...
function.
llvm-svn: 104082
2010-05-18 22:51:59 +00:00
63e9015248
Add some more debug output.
...
llvm-svn: 104080
2010-05-18 22:41:32 +00:00
f1c7b1b42f
Factor out the code for deleting a formula from an LSRUse into
...
a helper function.
llvm-svn: 104079
2010-05-18 22:39:15 +00:00
8aca7ef903
Make some debug output more informative.
...
llvm-svn: 104078
2010-05-18 22:37:37 +00:00
06ab08f795
Print an error message in Formula::print if the HasBaseReg flag
...
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
llvm-svn: 104077
2010-05-18 22:35:55 +00:00
248c41d108
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
...
confusion with LSRInstance's RegUses member.
llvm-svn: 104076
2010-05-18 22:33:00 +00:00
430b6e40ab
Remember to update VirtRegLastUse when spilling without killing before a call.
...
llvm-svn: 104074
2010-05-18 22:20:09 +00:00
f8bf663873
Teach mode load folding and unfolding code about CMP32ri8 and friends.
...
llvm-svn: 104068
2010-05-18 21:54:15 +00:00
4ed63f8687
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
...
specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
887dd1cd31
When converting a test to a cmp to fold a load, use the cmp that has an
...
8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
9f46539e07
make mcinstlower remove all but the first operand to CALL64pcrel32.
...
The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
...
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
feedc90c57
Implement EmitTBSSSymbol for MachOStreamer.
...
Fixes build failure as well.
llvm-svn: 104059
2010-05-18 21:26:41 +00:00
5c87be766d
Make EmitTBSSSymbol take a section argument so that we can find it later.
...
Fix up callers and users.
llvm-svn: 104057
2010-05-18 21:16:04 +00:00
663543b4d7
Properly handle multiple definitions of a virtual register in the same
...
instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
llvm-svn: 104056
2010-05-18 21:10:50 +00:00
45b3f702ab
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
...
llvm-svn: 104051
2010-05-18 20:07:47 +00:00
e7fc64a5c9
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
...
llvm-svn: 104050
2010-05-18 20:03:28 +00:00
7bcc9e9450
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
...
CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
llvm-svn: 104039
2010-05-18 18:09:20 +00:00
53e0631516
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
...
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
llvm-svn: 104038
2010-05-18 17:51:35 +00:00
4843178d6b
Teach the machine code verifier to use getSubRegisterRegClass().
...
The old approach was wrong. It had an off-by-one error.
llvm-svn: 104034
2010-05-18 17:31:12 +00:00
d5563f420a
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
...
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
llvm-svn: 104033
2010-05-18 17:28:24 +00:00
f16c12d7a1
MC/Mach-O: Remove some FIXMEs.
...
llvm-svn: 104032
2010-05-18 17:28:20 +00:00
39617bb08a
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
...
llvm-svn: 104031
2010-05-18 17:28:17 +00:00
a4820fcc78
MC/X86: Implement custom lowering to make sure we match things like
...
X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
llvm-svn: 104030
2010-05-18 17:22:24 +00:00
62bc96a1a5
llc (et al): Add support for --show-encoding and --show-inst.
...
llvm-svn: 104029
2010-05-18 17:22:19 +00:00
dea5310433
Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream.
...
Update the comment.
llvm-svn: 104021
2010-05-18 15:25:14 +00:00
ab7be75e3f
Simplify MCContext::(Next|Get)Instance
...
- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.
llvm-svn: 104020
2010-05-18 12:15:34 +00:00
48f0de96d6
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
...
llvm-svn: 104004
2010-05-18 00:03:40 +00:00
93d8844699
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
...
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
llvm-svn: 103995
2010-05-17 23:29:23 +00:00
1e4f55200d
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
...
llvm-svn: 103994
2010-05-17 23:24:12 +00:00
02d3368831
- Set the "HasCalls" flag after instruction selection is finished.
...
- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00
0510b48fd9
Added support in MC for Directional Local Labels.
...
llvm-svn: 103989
2010-05-17 23:08:19 +00:00
9635b3da6b
More data/parsing support for tls directives. Add a few more testcases
...
and cleanup comments as well.
llvm-svn: 103985
2010-05-17 22:53:55 +00:00
f2c9a96f3c
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
...
llvm-svn: 103984
2010-05-17 22:09:49 +00:00
cd04ed3533
vmov of immediates are trivially re-materializable.
...
llvm-svn: 103982
2010-05-17 21:54:50 +00:00
bb166bed40
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
...
llvm-svn: 103981
2010-05-17 21:54:30 +00:00
ce5e1bb326
MC: Add dyn_cast support to MCSection.
...
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.
llvm-svn: 103980
2010-05-17 21:54:26 +00:00
b7b796cc11
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
...
- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
llvm-svn: 103979
2010-05-17 21:19:59 +00:00
585792738b
Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.
...
This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.
llvm-svn: 103975
2010-05-17 21:02:08 +00:00
bf79238599
Add some section and constant support for darwin TLS.
...
llvm-svn: 103974
2010-05-17 21:02:07 +00:00
29c463862e
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
...
llvm-svn: 103971
2010-05-17 20:57:12 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
0211a96989
MC/Mach-O: Fix some differences in symbol flag handling.
...
- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
llvm-svn: 103964
2010-05-17 20:12:31 +00:00
70563bbba5
Remove debug option. Add comment on spill order determinism.
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llvm-svn: 103961
2010-05-17 20:01:22 +00:00
3d98b996ff
Turn on -neon-reg-sequence by default.
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Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
2010-05-17 19:51:20 +00:00
9b4a824217
llvm-mc: Support reassignment of variables in one special case, when the
...
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
llvm-svn: 103950
2010-05-17 17:46:23 +00:00
176a9c4272
Avoid allocating the same physreg to multiple virtregs in one instruction.
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While that approach works wonders for register pressure, it tends to break
everything.
This should unbreak the arm-linux builder and fix a number of miscompilations.
llvm-svn: 103946
2010-05-17 17:18:59 +00:00
f5e8c86424
Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map.
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llvm-svn: 103940
2010-05-17 15:30:37 +00:00
6649cdaa23
Extract spill cost calculation to a new method, and use definePhysReg() to clear
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out aliases when allocating. Clean up allocVirtReg().
Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.
llvm-svn: 103939
2010-05-17 15:30:32 +00:00
188855abef
Remove unused member variable.
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llvm-svn: 103936
2010-05-17 09:47:55 +00:00
7d22a81b61
Only use clairvoyance when defining a register, and then only if it has one use.
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This makes allocation independent on the ordering of use-def chains.
llvm-svn: 103935
2010-05-17 04:50:57 +00:00
f915d14955
Eliminate a hash table probe when killing virtual registers.
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llvm-svn: 103934
2010-05-17 03:26:09 +00:00
edd3d9db13
Execute virtreg kills immediately instead of after processing all uses.
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This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.
llvm-svn: 103933
2010-05-17 03:26:06 +00:00
e07a408afc
Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
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llvm-svn: 103931
2010-05-17 02:49:21 +00:00
1069a09691
Now that we don't keep live registers across calls, there is not reason to go
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through the very long list of call-clobbered registers. We just assume all
registers are clobbered.
llvm-svn: 103930
2010-05-17 02:49:18 +00:00
397068de06
Boldly attempt consistent capitalization. Functional changes unintended.
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llvm-svn: 103929
2010-05-17 02:49:15 +00:00
68b1bbe66a
Assume that we'll handle mangling the symbols earlier and just put the
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symbol to the file as we have it. Simplifies out tbss handling.
llvm-svn: 103928
2010-05-17 02:13:02 +00:00
8044c989d1
Spill and kill all virtual registers across a call.
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Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.
llvm-svn: 103927
2010-05-17 02:07:32 +00:00
d2ef1fbc82
Reduce hashtable probes by using DenseMap::insert() for lookup.
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llvm-svn: 103926
2010-05-17 02:07:29 +00:00
fb43e065a4
Make MBB a class member instead of passing it around everywhere.
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llvm-svn: 103925
2010-05-17 02:07:22 +00:00
166a7993ba
Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
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llvm-svn: 103922
2010-05-17 01:47:47 +00:00
5a2809cbd8
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
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llvm-svn: 103917
2010-05-17 01:11:46 +00:00
2ef974ee0e
Revert 103911; it broke a test that expects bitconvert
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<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
llvm-svn: 103914
2010-05-16 20:19:04 +00:00
fc1492d71b
Make x86-64 64-bit bitconvert work when SSE is not available.
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(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
llvm-svn: 103911
2010-05-16 18:22:38 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
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llvm-svn: 103903
2010-05-16 09:15:36 +00:00
8f35fabbc1
Add support for thiscall calling convention.
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Patch by Charles Davis and Steven Watanabe!
llvm-svn: 103902
2010-05-16 09:08:45 +00:00
4c719c4515
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
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llvm-svn: 103901
2010-05-16 08:54:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
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llvm-svn: 103898
2010-05-16 03:27:48 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
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The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
bb4656c05e
Improve assertion messages.
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llvm-svn: 103882
2010-05-15 18:38:02 +00:00
1bf28a128b
Some cheap DAG combine goodness for multiplication with a particular constant.
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This can be extended later on to handle more "complex" constants.
llvm-svn: 103881
2010-05-15 18:16:59 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
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Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
9e01b615a4
improve portability to systems that don't have round, patch by
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Evzen Muller!
llvm-svn: 103877
2010-05-15 17:11:55 +00:00
93cd0f1c89
improve portability to systems that don't have powf/modf (e.g. solaris 9)
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patch by Evzen Muller!
llvm-svn: 103876
2010-05-15 17:10:24 +00:00
75142e6bfc
Fix an GCC warning that seems to have actually caught a bug (!!!) in
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a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.
llvm-svn: 103869
2010-05-15 10:23:23 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
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llvm-svn: 103868
2010-05-15 07:53:37 +00:00
84ce290822
Calculate liveness on the fly for local registers.
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When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.
This makes the fast allocator independent of incoming kill flags.
llvm-svn: 103866
2010-05-15 06:09:08 +00:00
b35818eb25
Teach the always inliner to release its inline cost estimates, like the basic
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inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?
llvm-svn: 103858
2010-05-15 04:26:25 +00:00
002a45eb64
Clean up, no functional change.
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llvm-svn: 103857
2010-05-15 03:41:58 +00:00
3d214cdfaf
v4i64 and v8i64 are only synthesizable when NEON is available.
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llvm-svn: 103855
2010-05-15 02:20:21 +00:00
4cad68eb34
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
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allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
2010-05-15 02:18:07 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
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llvm-svn: 103851
2010-05-15 01:36:29 +00:00
e26e56e72b
A partial re-def instruction may be a copy.
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llvm-svn: 103850
2010-05-15 01:35:44 +00:00
8c2d062ea6
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
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instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-14 23:21:14 +00:00
cb78e5558b
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
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llvm-svn: 103833
2010-05-14 22:54:52 +00:00
88fb253562
Fast ISel trivially coalesces away no-op casts, so check for this when
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setting kill flags.
llvm-svn: 103832
2010-05-14 22:53:18 +00:00
089e9421d2
Don't bother spilling before a return
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llvm-svn: 103831
2010-05-14 22:40:43 +00:00
cdef6bc8de
RegAllocLocal can count copies too
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llvm-svn: 103830
2010-05-14 22:40:40 +00:00
0160e55893
SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
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replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)
llvm-svn: 103829
2010-05-14 22:17:42 +00:00
b16013936b
Track allocatable instead of reserved regs, and never take an unallocatable hint.
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llvm-svn: 103828
2010-05-14 22:02:56 +00:00
2f277c866d
Don't set kill flags for instructions which the scheduler has cloned.
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llvm-svn: 103827
2010-05-14 22:01:14 +00:00
062a97f0f6
BR is a barrier.
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llvm-svn: 103826
2010-05-14 22:00:27 +00:00
Bruno Cardoso Lopes