Commit Graph

3 Commits

Author SHA1 Message Date
Paul Walker 6cba90dc4d [AArch64][SVE] Correct intrinsics and patterns for logical predicate instructions
In general SVE intrinsics are considered predicated and merging
with everything else having suitable decoration.  For predicated
zeroing operations (like the predicate logical instructions) we
use the "_z" suffix.  After this change all intrinsics use their
expected names (i.e. orr instead of or and eor instead of xor).

I've removed intrinsics and patterns for condition code setting
instructions as that data is not returned as part of the intrinsic.
The expectation is to ask for a cc flag explicitly.

For example:
  a = and_z(pg, p1, p2)
  cc = ptest_<flag>(pg, a)

With the code generator expected to use "s" variants of instructions
when available.

Differential Revision: https://reviews.llvm.org/D71715
2019-12-20 14:22:27 +00:00
Danilo Carvalho Grael 53b95a3cb6 [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions
Add instrinics and patters for the following logical predicate instructions:
-- and, ands, bic, bics, eor, eors
-- sel
-- orr, orrs, orn, orns, nor, nors, nand, nads
2019-12-04 23:11:46 -05:00
Ehsan Amiri ed7bcb2cb1 [AArch64][SVE] Add patterns for some integer vector instructions
Add pattern matching for SVE vector instructions:

-- add, sub, and, or, xor instructions
-- sqadd, uqadd, sqsub, uqsub target-independent intrinsics
-- bic intrinsics
-- predicated add, sub, subr intrinsics

Patch Review: https://reviews.llvm.org/D69128
Patch authored by: dancgr (Danilo Carvalho Grael)
2019-10-30 21:52:19 -04:00