Commit Graph

5 Commits

Author SHA1 Message Date
Miloš Stojanović 24b7b99b7d [llvm-exegesis][NFC] Disassociate snippet generators from benchmark runners
The addition of `inverse_throughput` mode highlighted the disjointedness
of snippet generators and benchmark runners because it used the
`UopsSnippetGenerator` with the  `LatencyBenchmarkRunner`.
To keep the code consistent tie the snippet generators to
parallelization/serialization rather than their benchmark runners.

Renaming `LatencySnippetGenerator` -> `SerialSnippetGenerator`.
Renaming `UopsSnippetGenerator` -> `ParallelSnippetGenerator`.

Differential Revision: https://reviews.llvm.org/D72928
2020-01-20 16:19:13 +01:00
Miloš Stojanović ea91758a3c [llvm-exegesis][mips] Add support for memory instructions
Implementing functions used to enable testing of memory instructions.

Differential Revision: https://reviews.llvm.org/D72858
2020-01-17 13:26:09 +01:00
Miloš Stojanović 31458a9fee [llvm-exegesis][NFC] Refactor Mips tests fixtures into a base class.
Differential Revision: https://reviews.llvm.org/D72003
2020-01-16 17:50:44 +01:00
Guillaume Chatelet 32d384c020 [llvm-exegesis][NFC] internal changes
Summary:
BitVectors are now cached to lower memory utilization.
Instructions have reference semantics.

Reviewers: courbet

Subscribers: sdardis, tschuett, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71653
2019-12-18 17:24:07 +01:00
Miloš Stojanović 0add79aec2 [llvm-exegesis][mips] Add SnippetGeneratorTest unit test
Test latency with explicit register dependency, without and with
forbidden registers.

Differential Revision: https://reviews.llvm.org/D71471
2019-12-16 16:50:03 +01:00