055845f5cb
[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.
...
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.
Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.
llvm-svn: 225075
2015-01-02 07:02:25 +00:00
99bcab7b85
[X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not.
...
llvm-svn: 225036
2014-12-31 07:07:31 +00:00
b86338f7b2
[X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags.
...
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.
llvm-svn: 224809
2014-12-24 06:05:22 +00:00
5068d0f8e8
[AVX512] Support mask register in MRMDestReg format
...
This is necessary for masking vextract*x4.
llvm-svn: 219359
2014-10-08 23:25:29 +00:00
fd6a73d70a
[X86 disasm tblegen backend] Clean up numPhysicalOperands asserts
...
No functionality change intended.
This implements Elena's idea to put the new additionalOperand outside the
switch to cover all cases
(http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140929/237763.html ).
Note only nontrivial change is in MRMSrcMemFrm. This requires an inclusive
interval of [2, 4] because we have prefix-dependent *optional* immediate
operand.
llvm-svn: 218790
2014-10-01 19:28:11 +00:00
373b2b1728
[x86] Fix a pretty horrible bug and inconsistency in the x86 asm
...
parsing (and latent bug in the instruction definitions).
This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.
The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:
insertps $192, %xmm0, %xmm1
insertps $-64, %xmm0, %xmm1
These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.
The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.
Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.
The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.
In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.
I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.
llvm-svn: 217310
2014-09-06 10:00:01 +00:00
2ea081d4d1
[SKX] avx512_icmp_packed multiclass extension
...
Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions
Differential Revision: http://reviews.llvm.org/D5024
llvm-svn: 216383
2014-08-25 14:49:34 +00:00
0d928a142b
Add support for the X86 secure guard extensions instructions in assembler (SGX).
...
This allows assembling the two new instructions, encls and enclu for the
SKX processor model.
Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.
rdar://16228228
llvm-svn: 214460
2014-07-31 23:57:38 +00:00
595683da00
[SKX] Enabling mask logic instructions: encoding, lowering
...
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214081
2014-07-28 13:46:45 +00:00
74acbb7767
[SKX] Enabling mask instructions: encoding, lowering
...
KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 213757
2014-07-23 14:49:42 +00:00
bfa0131365
[SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.
...
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)
Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 213545
2014-07-21 14:54:21 +00:00
5933c2f824
[X86] AVX512: Add disassembler support for compressed displacement
...
There are two parts here. First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.
The second is to use the new encoding types to compute the correct
displacement in the decoder.
Fixes <rdar://problem/17608489>
llvm-svn: 213281
2014-07-17 17:04:56 +00:00
2406477179
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
...
llvm-svn: 206254
2014-04-15 07:20:03 +00:00
e413b628f8
[x86] Simplify disassembler code slightly.
...
llvm-svn: 202233
2014-02-26 06:01:21 +00:00
e2347df24d
[x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
...
llvm-svn: 201767
2014-02-20 07:59:43 +00:00
56f0ed815e
Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
...
llvm-svn: 201649
2014-02-19 08:25:02 +00:00
2fb696b214
Put some of the X86 formats in a more logical order.
...
llvm-svn: 201645
2014-02-19 06:59:13 +00:00
0d1fd55c13
Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
...
llvm-svn: 201641
2014-02-19 05:34:21 +00:00
5ccb61781f
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
...
llvm-svn: 201538
2014-02-18 00:21:49 +00:00
69e245c01d
Remove filtering concept from X86 disassembler table generation. It's no longer necessary.
...
llvm-svn: 201299
2014-02-13 07:07:16 +00:00
5b3a6bd370
Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already.
...
llvm-svn: 201216
2014-02-12 08:09:20 +00:00
ea91f02762
Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code.
...
llvm-svn: 201215
2014-02-12 08:02:29 +00:00
a0869dceea
Recommit r201059 and r201060 with hopefully a fix for its original failure.
...
Original commits messages:
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
llvm-svn: 201065
2014-02-10 06:55:41 +00:00
ebdae7c2ff
Revert r201059 and r201060.
...
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.
llvm-svn: 201064
2014-02-10 05:28:30 +00:00
0a43c2c393
Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.
...
llvm-svn: 201060
2014-02-10 01:58:12 +00:00
0d88de8c56
Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
...
llvm-svn: 201059
2014-02-10 00:50:34 +00:00
fa6298a162
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
...
llvm-svn: 200626
2014-02-02 09:25:09 +00:00
8e92e85ac7
Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.
...
llvm-svn: 200625
2014-02-02 07:46:05 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
...
llvm-svn: 200624
2014-02-02 07:08:01 +00:00
10243c8907
Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
...
llvm-svn: 200522
2014-01-31 08:47:06 +00:00
ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
...
llvm-svn: 200520
2014-01-31 07:00:55 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
...
llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
...
llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
...
llvm-svn: 199803
2014-01-22 15:08:08 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
...
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
...
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
...
llvm-svn: 199295
2014-01-15 05:02:02 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
...
llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
...
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
...
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
...
llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
...
llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
...
llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
...
llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
...
llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
...
llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
...
llvm-svn: 198543
2014-01-05 04:17:28 +00:00
5999d47538
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
...
llvm-svn: 198530
2014-01-05 01:35:51 +00:00
bc281ad8c1
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
...
llvm-svn: 198515
2014-01-04 22:29:41 +00:00
1da8582322
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
...
llvm-svn: 198475
2014-01-04 05:09:27 +00:00
66c20f344e
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
...
llvm-svn: 198336
2014-01-02 19:12:10 +00:00
fae226c67e
Remove unused HasFROperands field from disassembler.
...
llvm-svn: 198332
2014-01-02 18:44:21 +00:00
eabdbcb8a9
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
...
llvm-svn: 198327
2014-01-02 18:20:48 +00:00
a941d2b08e
Remove unnecessary stirng comparison from disassembler.
...
llvm-svn: 198325
2014-01-02 17:41:40 +00:00
9dd48c8ed4
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
...
llvm-svn: 198323
2014-01-02 17:28:14 +00:00
83b7e24b76
Remove unused function argument.
...
llvm-svn: 198291
2014-01-02 03:58:45 +00:00
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
...
llvm-svn: 198284
2014-01-01 21:52:57 +00:00
9155118602
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
...
llvm-svn: 198278
2014-01-01 15:29:32 +00:00
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
...
Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
623b0d64b3
Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
...
llvm-svn: 198276
2014-01-01 14:22:37 +00:00
e98c8cb9f0
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
...
llvm-svn: 198265
2013-12-31 17:21:44 +00:00
0e21bca6dd
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
...
llvm-svn: 198238
2013-12-30 19:16:48 +00:00
6d776e2660
Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change.
...
llvm-svn: 198226
2013-12-30 17:37:10 +00:00
c0a5aaeab0
[x86] Rename In32BitMode predicate to Not64BitMode
...
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)
Patch by David Woodhouse
llvm-svn: 197768
2013-12-20 02:04:49 +00:00
47fc44e52e
AVX-512: Added legal type MVT::i1 and VK1 register for it.
...
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
2013-12-16 13:52:35 +00:00
dacddb0bab
AVX-512: added VPCONFLICT instruction and intrinsics,
...
added EVEX_KZ to tablegen
llvm-svn: 193959
2013-11-03 13:46:31 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
...
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
88adf2a49c
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
...
llvm-svn: 192525
2013-10-12 05:41:08 +00:00
aab53e7785
Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
...
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
81034928c6
Remove another unnecessary filter from the disassembler.
...
llvm-svn: 192425
2013-10-11 06:59:57 +00:00
e1ceeb40c1
Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
...
llvm-svn: 192339
2013-10-10 04:26:52 +00:00
2d0d180ab4
More x86 disassembler filtering cleanup.
...
llvm-svn: 192279
2013-10-09 06:12:53 +00:00
043d749ba3
Remove some old filters from the x86 disassembler table builder.
...
llvm-svn: 192275
2013-10-09 05:02:29 +00:00
a984729f8a
Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
...
llvm-svn: 192175
2013-10-08 06:30:39 +00:00
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
...
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
07ad1b23bb
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
...
llvm-svn: 192090
2013-10-07 07:19:47 +00:00
2658d89728
Add disassembler support for long encodings for INC/DEC in 32-bit mode.
...
llvm-svn: 192086
2013-10-07 04:28:06 +00:00
9e3e38ae3f
Add XOP disassembler support. Fixes PR13933.
...
llvm-svn: 191874
2013-10-03 05:17:48 +00:00
c35219e3ee
AVX-512: Added masked SHIFT commands, more encoding tests
...
llvm-svn: 189005
2013-08-22 12:18:28 +00:00
9469e906a5
Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file.
...
llvm-svn: 187333
2013-07-28 21:28:02 +00:00
baf51e3e61
fixed compilation issue
...
llvm-svn: 187325
2013-07-28 08:45:12 +00:00
003e7d73b9
Added encoding prefixes for KNL instructions (EVEX).
...
Added 512-bit operands printing.
Added instruction formats for KNL instructions.
llvm-svn: 187324
2013-07-28 08:28:38 +00:00
8811ad4f81
Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
...
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.
llvm-svn: 184207
2013-06-18 17:08:10 +00:00
95d9440348
Add CLAC/STAC instruction encoding/decoding support
...
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
llvm-svn: 179266
2013-04-11 04:52:28 +00:00
656e8515fc
x86 -- add the XTEST instruction
...
llvm-svn: 177888
2013-03-25 18:59:43 +00:00
f15856ebb4
Fixes disassembler crashes on 2013 Haswell RTM instructions.
...
rdar://13318048
llvm-svn: 176828
2013-03-11 21:17:13 +00:00
ab588efe42
Added 0x0D to 2-byte opcode extension table for prefetch* variants
...
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs
llvm-svn: 174920
2013-02-12 00:19:12 +00:00
91d19d8e93
Sort the #include lines for utils/...
...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
llvm-svn: 169251
2012-12-04 10:37:14 +00:00
73cffddb95
Add support of RTM from TSX extension
...
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
llvm-svn: 167573
2012-11-08 07:28:54 +00:00
3f23c1a8b9
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
...
llvm-svn: 164204
2012-09-19 06:37:45 +00:00
c30fdbc46c
Add support for converting llvm.fma to fma4 instructions.
...
llvm-svn: 162999
2012-08-31 15:40:30 +00:00
c6b7ef61f4
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
...
llvm-svn: 160951
2012-07-30 06:48:11 +00:00
08ead0b14e
Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly
...
llvm-svn: 160950
2012-07-30 06:27:19 +00:00
6f4ad80dc8
Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.
...
llvm-svn: 160949
2012-07-30 05:39:34 +00:00
b58dc17025
Simplify code that filtered certain instructions in two different ways. No functional change.
...
llvm-svn: 160948
2012-07-30 05:10:05 +00:00
60a58ac3e2
Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.
...
llvm-svn: 160946
2012-07-30 04:53:00 +00:00
ac172e225d
Remove trailing whitespace.
...
llvm-svn: 160945
2012-07-30 04:48:12 +00:00
c7690ac7ac
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
...
llvm-svn: 160775
2012-07-26 07:48:28 +00:00
9208abd7c3
Move around some enum elements so that lastMRM corrects gets assigned 56, which
...
is one more that MRM_DF which is 55. Previously, it held value 45, the same
as MRM_D0.
llvm-svn: 160465
2012-07-18 23:04:22 +00:00
01deb5f2df
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
...
llvm-svn: 160420
2012-07-18 04:11:12 +00:00
f7755df776
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
...
llvm-svn: 160110
2012-07-12 06:52:41 +00:00
a09820414a
X86: add GATHER intrinsics (AVX2) in LLVM
...
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
ef479ea854
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
...
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
2012-05-29 19:05:25 +00:00
7629d63bc4
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
...
llvm-svn: 153935
2012-04-03 05:20:24 +00:00
014e1cde5f
Fix the x86 disassembler to at least print the lock prefix if it is the first
...
prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
2012-03-09 17:52:49 +00:00
6491c8020e
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
...
llvm-svn: 151510
2012-02-27 01:54:29 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
...
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
...
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
2ba766ae84
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
...
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
03a0beda88
Add FMA4 instructions to disassembler.
...
llvm-svn: 147367
2011-12-30 05:20:36 +00:00
75ffc5fbb5
Remove some unnecessary filtering checks from X86 disassembler table build.
...
llvm-svn: 144986
2011-11-19 05:48:20 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
...
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
980d59832a
Add X86 RORX instruction
...
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
...
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
...
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
...
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
...
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
...
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
...
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
...
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
4f2fba1108
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
...
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
7e2489a7c9
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
...
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
af8ee2cdee
Unconstify Inits
...
Remove const qualifiers from Init references, per Chris' request.
llvm-svn: 136531
2011-07-29 22:43:06 +00:00
1aa0e3e118
[AVX] Constify Inits
...
Make references to Inits const everywhere. This is the final step
before making them unique.
llvm-svn: 136485
2011-07-29 19:07:05 +00:00
5ef6c453a6
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
...
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
2011-07-27 23:01:50 +00:00
0318036c4d
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
...
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
71520a867d
Revert r134921, 134917, 134908 and 134907. They're causing failures
...
in multiple buildbots.
llvm-svn: 134936
2011-07-11 23:06:52 +00:00
af973b4f36
[AVX] Make Inits Foldable
...
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
llvm-svn: 134907
2011-07-11 18:25:51 +00:00
fc4789da4a
Add support for the VIA PadLock instructions.
...
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
c3fd523731
X86 table-generator and disassembler support for the AVX
...
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
e39062199e
Implement xgetbv and xsetbv.
...
Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
578074b2f3
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
...
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
d8adec70f3
factor the operand list (and related fields/operations) out of
...
CodeGenInstruction into its own helper class. No functionality change.
llvm-svn: 117893
2010-11-01 04:03:32 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
8d302b2e71
Fixed the disassembler to handle two new X86
...
instruction forms. Now the ENTER instruction
disassembles correctly.
llvm-svn: 115573
2010-10-04 22:45:51 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
605acfe533
Add patterns for MMX that use the new intrinsics.
...
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
llvm-svn: 113233
2010-09-07 18:10:56 +00:00
41b4a6b36a
Convert some tab stops into spaces.
...
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
...
in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
Craig Topper