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99 Commits

Author SHA1 Message Date
Jim Laskey 4e153f1b91 Use an enumeration to eliminate data relocations. 
llvm-svn: 29249
 2006-07-21 20:57:35 +00:00
Jim Laskey f7300b2706 It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey c3d341ea98 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Evan Cheng 55772ccfd6 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng 0c0996a97b commuteInstruction() does not always create a new MI! 
llvm-svn: 28592
 2006-05-31 18:03:39 +00:00
Evan Cheng 9d91caa053 Eliminate a memory leak. 
llvm-svn: 28585
 2006-05-31 07:13:03 +00:00
Evan Cheng d8e2f6ebc1 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Chris Lattner 957cb6733a Move function-live-in-handling code from the sdisel code to the scheduler. 
This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.

llvm-svn: 28315
 2006-05-16 06:10:58 +00:00
Evan Cheng 99f2f79e2f Fixing 2006-05-01-SchedCausingSpills.ll; some clean up 
llvm-svn: 28279
 2006-05-13 08:22:24 +00:00
Owen Anderson 8c2c1e90c4 Refactor a bunch of includes so that TargetMachine.h doesn't have to include 
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.

llvm-svn: 28238
 2006-05-12 06:33:49 +00:00
Evan Cheng 095c9d9b7f Duh. That could take a long time. 
llvm-svn: 28235
 2006-05-12 06:05:18 +00:00
Evan Cheng afed73eebe Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.

llvm-svn: 28230
 2006-05-12 01:58:24 +00:00
Evan Cheng d38c22bdd3 Refactor scheduler code. Move register-reduction list scheduler to a 
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
 2006-05-11 23:55:42 +00:00
Chris Lattner 469647bf38 Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner 10b71c0d08 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner 940cc978ef Remove a bunch more SparcV9 specific stuff 
llvm-svn: 28093
 2006-05-04 01:15:02 +00:00
Owen Anderson 20a631fde7 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.

llvm-svn: 28074
 2006-05-03 01:29:57 +00:00
Nate Begeman 4ca2ea5b43 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner 87b1dddb1c fix spello 
llvm-svn: 27053
 2006-03-24 07:15:07 +00:00
Chris Lattner 6b20104410 TargetData doesn't know the alignment of vectors :( 
llvm-svn: 26884
 2006-03-20 01:51:46 +00:00
Chris Lattner a5b93b8c6d Move some simple-sched-specific instance vars to the simple scheduler. 
llvm-svn: 26690
 2006-03-10 07:42:02 +00:00
Chris Lattner e015178de1 prune #includes 
llvm-svn: 26689
 2006-03-10 07:37:35 +00:00
Chris Lattner 4b70ff7876 move some simple scheduler methods into the simple scheduler 
llvm-svn: 26688
 2006-03-10 07:35:21 +00:00
Chris Lattner dc2f135f5c Make EmitNode take a SDNode instead of a NodeInfo* 
llvm-svn: 26687
 2006-03-10 07:28:36 +00:00
Chris Lattner b9d8fa0342 Move the VRBase field from NodeInfo to being a separate, explicit, map. 
llvm-svn: 26686
 2006-03-10 07:25:12 +00:00
Chris Lattner 2f8c7c3d55 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy 
llvm-svn: 26682
 2006-03-10 06:34:51 +00:00
Chris Lattner 543832d39d Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner 2d945ba4c7 When a hazard recognizer needs noops to be inserted, do so. This represents 
noops as null pointers in the instruction sequence.

llvm-svn: 26564
 2006-03-05 23:51:47 +00:00
Evan Cheng ed169db8a5 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Chris Lattner 5af3fdec12 Pass all the flags to the asm printer, not just the # operands. 
llvm-svn: 26362
 2006-02-24 19:50:58 +00:00
Chris Lattner 2f8a794b13 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.

llvm-svn: 26361
 2006-02-24 19:18:20 +00:00
Chris Lattner 86c51000db Refactor operand adding out to a new AddOperand method 
llvm-svn: 26358
 2006-02-24 18:54:03 +00:00
Chris Lattner 571d9647c6 Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.

llvm-svn: 26332
 2006-02-23 19:21:04 +00:00
Chris Lattner 4576bb74d5 Make MachineConstantPool entries alignments explicit 
llvm-svn: 26071
 2006-02-09 02:23:13 +00:00
Jeff Cohen 95ae171d5b Fix VC++ warning. 
llvm-svn: 25975
 2006-02-04 16:20:31 +00:00
Evan Cheng f9adce90bf Get rid of some memory leaks identified by Valgrind 
llvm-svn: 25960
 2006-02-04 06:49:00 +00:00
Chris Lattner 3b48431333 Add initial support for immediates. This allows us to compile this: 
int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr

llvm-svn: 25955
 2006-02-04 02:26:14 +00:00
Evan Cheng 32be2dc0af Allow the specification of explicit alignments for constant pool entries. 
llvm-svn: 25855
 2006-01-31 22:23:14 +00:00
Chris Lattner 2e56e89452 Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.

llvm-svn: 25827
 2006-01-31 02:03:41 +00:00
Chris Lattner 4df279cfda Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an 
ISD::INLINEASM node.

llvm-svn: 25668
 2006-01-26 23:28:04 +00:00
Evan Cheng 1880f8db02 No need to keep track of top and bottom nodes in a group since the vector is 
already in order. Thanks Jim for pointing it out.

llvm-svn: 25608
 2006-01-25 18:54:24 +00:00
Evan Cheng fbc88a624a Keep track of bottom / top element of a set of flagged nodes. 
llvm-svn: 25600
 2006-01-25 09:13:41 +00:00
Evan Cheng c1e1d9724d Factor out more instruction scheduler code to the base class. 
llvm-svn: 25532
 2006-01-23 07:01:07 +00:00
Evan Cheng 739a6a456e Do some code refactoring on Jim's scheduler in preparation of the new list 
scheduler.

llvm-svn: 25493
 2006-01-21 02:32:06 +00:00
Duraid Madina fb6a914ca7 purity++ 
llvm-svn: 25041
 2005-12-29 05:59:19 +00:00
Jim Laskey 9e296bee9a Disengage DEBUG_LOC from non-PPC targets. 
llvm-svn: 24919
 2005-12-21 20:51:37 +00:00
Jim Laskey 9b9688aeb8 Amend comment. 
llvm-svn: 24861
 2005-12-19 16:32:26 +00:00
Jim Laskey ce23987e6b Create a strong dependency for loads following stores. This will leave a 
latency period between the two.

llvm-svn: 24860
 2005-12-19 16:30:13 +00:00
Jeff Cohen c7cb351aac Keep VC++ happy. 
llvm-svn: 24835
 2005-12-18 22:20:05 +00:00
Jim Laskey c97b7d0be9 Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.

llvm-svn: 24816
 2005-12-18 04:40:52 +00:00