d7c4e7d255
add support for splitting casts. This implements
...
CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
...
llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
...
llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
c6c9e65301
remove temporary option
...
llvm-svn: 26646
2006-03-09 17:31:22 +00:00
d17d77aa1d
yes yes, enabled debug output is bad
...
llvm-svn: 26637
2006-03-09 07:39:25 +00:00
6398c13128
switch the t-d scheduler to use a really dumb and trivial critical path
...
latency priority function.
llvm-svn: 26636
2006-03-09 07:38:27 +00:00
d4130375c0
Pull latency information for target instructions out of the latency tables. :)
...
Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
2006-03-09 07:15:18 +00:00
da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
...
copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
...
llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
...
llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
...
bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
...
llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c610e62e46
print arbitrary constant pool entries
...
llvm-svn: 26545
2006-03-05 09:38:03 +00:00
d428e22c07
Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now.
...
It's causing an infinite loop compiling ldecod on x86 / Darwin.
llvm-svn: 26544
2006-03-05 07:30:16 +00:00
3bc4050217
Add some simple copysign folds
...
llvm-svn: 26543
2006-03-05 05:30:57 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
f29f5204cc
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
...
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
llvm-svn: 26535
2006-03-04 23:33:26 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
23e75f5b49
SDOperand::isOperand should not be a forwarding. It must check *this against N's operands.
...
llvm-svn: 26502
2006-03-03 06:42:32 +00:00
6b08ae8497
Added isOperand(N): true if this is an operand of N
...
llvm-svn: 26501
2006-03-03 06:24:54 +00:00
5e9a695026
A bit more tweaking
...
llvm-svn: 26500
2006-03-03 06:23:43 +00:00
55c1173a6c
Fix VC++ compilation errors.
...
llvm-svn: 26498
2006-03-03 03:25:07 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
4e3904f637
- Fixed some priority calculation bugs that were causing bug 478. Among them:
...
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
2006-03-02 21:38:29 +00:00
0db2f2c689
Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
...
in the dag combiner on 176.gcc on x86.
llvm-svn: 26459
2006-03-01 21:47:21 +00:00
232024edb8
Fix a typo evan noticed
...
llvm-svn: 26454
2006-03-01 19:55:35 +00:00
bc1c85beea
Add support for target-specific dag combines
...
llvm-svn: 26443
2006-03-01 04:53:38 +00:00
fbcd62d3bb
Add a new AddToWorkList method, start using it
...
llvm-svn: 26441
2006-03-01 04:03:14 +00:00
324871ef1a
Pull shifts by a constant through multiplies (a form of reassociation),
...
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
llvm-svn: 26440
2006-03-01 03:44:24 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
be85e89ec4
- Added VConstant as an abstract version of ConstantVec.
...
- All abstrct vector nodes must have # of elements and element type as their
first two operands.
llvm-svn: 26432
2006-03-01 00:51:13 +00:00
f0032b350c
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
llvm-svn: 26419
2006-02-28 06:49:37 +00:00
bdbc4476d9
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26417
2006-02-28 06:35:35 +00:00
0f8a727c49
fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
...
llvm-svn: 26416
2006-02-28 06:23:04 +00:00
9fed5b6122
Add support for output memory constraints.
...
llvm-svn: 26410
2006-02-27 23:45:39 +00:00
47ee42829d
remove some completed notes
...
llvm-svn: 26390
2006-02-27 00:39:31 +00:00
9f9662b86e
Print ConstantPoolSDNode offset field.
...
llvm-svn: 26381
2006-02-26 08:36:57 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
5af3fdec12
Pass all the flags to the asm printer, not just the # operands.
...
llvm-svn: 26362
2006-02-24 19:50:58 +00:00
2f8a794b13
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
...
Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
86c51000db
Refactor operand adding out to a new AddOperand method
...
llvm-svn: 26358
2006-02-24 18:54:03 +00:00
83c22e0d75
Get VC++ building again.
...
llvm-svn: 26351
2006-02-24 02:52:40 +00:00
dcf785bf46
Implement (most of) selection of inline asm memory operands.
...
llvm-svn: 26350
2006-02-24 02:13:54 +00:00
7ef7a64ebb
Lower C_Memory operands.
...
llvm-svn: 26346
2006-02-24 01:11:24 +00:00
e7c0ffb3a0
Fix an endianness problem on big-endian targets with expanded operands
...
to inline asms. Mark some methods const.
llvm-svn: 26334
2006-02-23 20:06:57 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
b1124f3c76
This fixes a couple of problems with expansion
...
llvm-svn: 26318
2006-02-22 23:09:03 +00:00
6f87d18be9
Change a whole bunch of code to be built around RegsForValue instead of
...
a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
llvm-svn: 26316
2006-02-22 22:37:12 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
301f45cf6f
Fix a problem Nate and Duraid reported where simplifying nodes can cause
...
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.
llvm-svn: 26291
2006-02-20 06:51:04 +00:00
486d1bc5ed
Fix a problem on itanium with memset. The value to set has been promoted to
...
i64 before this code, so zero_ext doesn't work.
llvm-svn: 26290
2006-02-20 06:38:35 +00:00
abac61603f
Add checks to make sure we don't create bogus extend nodes, and fix a bug
...
where we were doing exactly that which was causing failures on x86 and
alpha.
llvm-svn: 26284
2006-02-18 02:40:58 +00:00
375e1a71cc
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
...
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
llvm-svn: 26269
2006-02-17 21:58:01 +00:00
fb5dbadf15
Clean up DemandedBitsAreZero interface
...
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
llvm-svn: 26263
2006-02-17 19:54:08 +00:00
57b3567552
Don't expand sdiv by power of two before legalize, since it will likely
...
generate illegal nodes.
llvm-svn: 26261
2006-02-17 07:26:20 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
9ec392b2aa
Fix another miscompilation exposed by lencode, where we lowered i64->f32
...
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
llvm-svn: 26254
2006-02-17 04:32:33 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
471627c49d
Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written
...
by Nate, I'm just committing it for him.
llvm-svn: 26230
2006-02-16 08:02:36 +00:00
93e4865d4b
Remove an unused function parameter.
...
llvm-svn: 26221
2006-02-15 22:12:35 +00:00
6781b6e62e
Turn a memcpy from string constant into a series of stores of constant values.
...
llvm-svn: 26219
2006-02-15 21:59:04 +00:00
2eea436192
Should not combine ISD::LOCATIONs until we have scheme to remove from
...
MachineDebugInfo tables.
llvm-svn: 26216
2006-02-15 19:34:44 +00:00
e2038bdeee
Lower memcpy with small constant size operand into a series of load / store
...
ops.
llvm-svn: 26195
2006-02-15 01:54:51 +00:00
0451499b3c
Doh again!
...
llvm-svn: 26188
2006-02-14 23:05:54 +00:00
db2a7a736a
Keep to < 80 cols
...
llvm-svn: 26177
2006-02-14 20:12:38 +00:00
038521ef76
Missed a break so memcpy cases fell through to memset. Doh.
...
llvm-svn: 26176
2006-02-14 19:45:56 +00:00
d502610604
Fixed a build breakage.
...
llvm-svn: 26175
2006-02-14 09:11:59 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
81fcea8aa2
Expand memset dst, c, size to a series of stores if size falls below the
...
target specific theshold, e.g. 16 for x86.
llvm-svn: 26171
2006-02-14 08:22:34 +00:00
1784a9d267
now that libcalls don't suck, we can remove this hack
...
llvm-svn: 26164
2006-02-14 05:39:35 +00:00
8e2ee7358f
Fix a latent bug in the call sequence handling stuff. Some targets (e.g. x86)
...
create these nodes with flag results. Remember that we legalized them.
llvm-svn: 26156
2006-02-14 00:55:02 +00:00
390c63e9d9
Rename to better reflect usage (current and planned.)
...
llvm-svn: 26145
2006-02-13 12:50:39 +00:00
462505fc5f
Completely rewrite libcall insertion by the legalizer, providing the
...
following handy-dandy properties:
1. it is always correct now
2. it is much faster than before
3. it is easier to understand
This implementation builds off of the recent simplifications of the
legalizer that made it single-pass instead of iterative.
This fixes JM/lencod, JM/ldecod, and
CodeGen/Generic/2006-02-12-InsertLibcall.ll (at least on PPC).
llvm-svn: 26144
2006-02-13 09:18:02 +00:00
5995d0160c
Reorg for integration with gcc4. Old style debug info will not be passed though
...
to SelIDAG.
llvm-svn: 26115
2006-02-11 01:01:30 +00:00
a1ef3ec5b5
Added SelectionDAG::InsertISelMapEntry(). This is used to workaround the gcc
...
problem where it inline the map insertion call too aggressively. Before this
change it was producing a frame size of 24k for Select_store(), now it's down
to 10k (by calling this method rather than calling the map insertion operator).
llvm-svn: 26094
2006-02-09 22:11:03 +00:00
d3f1db93c1
More changes to reduce frame size.
...
Move all getTargetNode() out of SelectionDAG.h into SelectionDAG.cpp. This
prevents them from being inlined.
Change getTargetNode() so they return SDNode * instead of SDOperand to prevent
copying. It should also help compilation speed.
llvm-svn: 26083
2006-02-09 07:15:23 +00:00
4576bb74d5
Make MachineConstantPool entries alignments explicit
...
llvm-svn: 26071
2006-02-09 02:23:13 +00:00
a10e23c19f
Compile this:
...
xori r6, r2, 1
rlwinm r6, r6, 0, 31, 31
cmpwi cr0, r6, 0
bne cr0, LBB1_3 ; endif
to this:
rlwinm r6, r2, 0, 31, 31
cmpwi cr0, r6, 0
beq cr0, LBB1_3 ; endif
llvm-svn: 26047
2006-02-08 02:13:15 +00:00
8c9cd461df
Back out previous commit, it isn't safe.
...
llvm-svn: 26006
2006-02-05 08:23:00 +00:00
3dc8b89493
fold c1 << (x + c2) into (c1 << c2) << x. fix a warning.
...
llvm-svn: 26005
2006-02-05 08:07:24 +00:00
c89fdf1eb3
Handle urem by shifted powers of 2.
...
llvm-svn: 26001
2006-02-05 07:36:48 +00:00
25d178bece
handle combining A / (B << N) into A >>u (log2(B)+N) when B is a power of 2
...
llvm-svn: 26000
2006-02-05 07:20:23 +00:00
d37645c07d
* Added SDNode::isOnlyUse().
...
* Fix hasNUsesOfValue(), it should be const.
llvm-svn: 25990
2006-02-05 06:29:23 +00:00
95ae171d5b
Fix VC++ warning.
...
llvm-svn: 25975
2006-02-04 16:20:31 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
65ad53feb3
Initial early support for non-register operands, like immediates
...
llvm-svn: 25952
2006-02-04 02:16:44 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
f68fd20286
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
...
llvm-svn: 25941
2006-02-03 20:13:59 +00:00
6091407783
remove dead fn
...
llvm-svn: 25935
2006-02-03 06:51:34 +00:00
22e251abf1
Add common code for reassociating ops in the dag combiner
...
llvm-svn: 25934
2006-02-03 06:46:56 +00:00
02b5b9cdd6
Added case HANDLENODE to getOperationName().
...
llvm-svn: 25920
2006-02-03 01:33:01 +00:00
49beaf40fc
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
...
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
llvm-svn: 25901
2006-02-02 07:17:31 +00:00
49ce35542f
add two dag combines:
...
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
llvm-svn: 25898
2006-02-02 06:36:13 +00:00
0bd74558ae
make -debug output less newliney
...
llvm-svn: 25895
2006-02-02 00:38:08 +00:00
7f5880b1c7
Implement matching constraints. We can now say things like this:
...
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 00:25:23 +00:00
01bd9d9911
*** empty log message ***
...
llvm-svn: 25879
2006-02-01 19:05:15 +00:00
1558fc64f9
Implement simple register assignment for inline asms. This allows us to compile:
...
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-01 18:59:47 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3a5ed55187
adjust to changes in InlineAsm interface. Fix a few minor bugs.
...
llvm-svn: 25865
2006-02-01 01:28:23 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
2443ab932d
Allow custom lowering of fabs. I forgot to check in this change which
...
caused several test failures.
llvm-svn: 25852
2006-01-31 18:14:25 +00:00
e9721b2984
Only insert an AND when converting from BR_COND to BRCC if needed.
...
llvm-svn: 25832
2006-01-31 05:04:52 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
f263a23735
Fix a bug in my legalizer reworking that caused the X86 backend to not get
...
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll
llvm-svn: 25821
2006-01-30 22:43:50 +00:00
d6f5ae4455
don't insert an and node if it isn't needed here, this can prevent folding
...
of lowered target nodes.
llvm-svn: 25804
2006-01-30 04:22:28 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
3b40e64aa3
pass the address of MaskedValueIsZero into isMaskedValueZeroForTargetNode,
...
to permit recursion
llvm-svn: 25799
2006-01-30 03:49:37 +00:00
4d1ea71a31
Fix RET of promoted values on targets that custom expand RET to a target node.
...
llvm-svn: 25794
2006-01-29 21:02:23 +00:00
2c748afd6c
cleanups to the ValueTypeActions interface
...
llvm-svn: 25785
2006-01-29 08:42:06 +00:00
ccb4476c87
Remove some special case hacks for CALLSEQ_*, using UpdateNodeOperands
...
instead.
llvm-svn: 25780
2006-01-29 07:58:15 +00:00
2f292789dc
Allow custom expansion of ConstantVec nodes. PPC will use this in the future.
...
llvm-svn: 25774
2006-01-29 06:34:16 +00:00
758b0ac54b
Legalize ConstantFP into TargetConstantFP when the target allows. Implement
...
custom expansion of ConstantFP nodes.
llvm-svn: 25772
2006-01-29 06:26:56 +00:00
678da98835
eliminate uses of SelectionDAG::getBR2Way_CC
...
llvm-svn: 25767
2006-01-29 06:00:45 +00:00
d02b05473c
Use the new "UpdateNodeOperands" method to simplify LegalizeDAG and make it
...
faster. This cuts about 120 lines of code out of the legalizer (mostly code
checking to see if operands have changed).
It also fixes an ugly performance issue, where the legalizer cloned the entire
graph after any change. Now the "UpdateNodeOperands" method gives it a chance
to reuse nodes if the operands of a node change but not its opcode or valuetypes.
This speeds up instruction selection time on kimwitu++ by about 8.2% with a
release build.
llvm-svn: 25746
2006-01-28 10:58:55 +00:00
580b12ad34
add another method variant
...
llvm-svn: 25744
2006-01-28 10:09:25 +00:00
f34156e8cb
add some methods for updating nodes
...
llvm-svn: 25742
2006-01-28 09:32:45 +00:00
eb63751499
minor tweaks
...
llvm-svn: 25740
2006-01-28 08:31:04 +00:00
689bdcc9cf
move a bunch of code, no other change.
...
llvm-svn: 25739
2006-01-28 08:25:58 +00:00
fcfda5a174
remove a couple more now-extraneous legalizeop's
...
llvm-svn: 25738
2006-01-28 08:22:56 +00:00
364b89a784
fix a bug
...
llvm-svn: 25737
2006-01-28 07:42:08 +00:00
9dcce6da8e
Several major changes:
...
1. Pull out the expand cases for BSWAP and CT* into a separate function,
reducing the size of LegalizeOp.
2. Fix a bug where expand(bswap i64) was wrong when i64 is legal.
3. Changed LegalizeOp/PromoteOp so that the legalizer never needs to be
iterative. It now operates in a single pass over the nodes.
4. Simplify a LOT of code, with a net reduction of ~280 lines.
llvm-svn: 25736
2006-01-28 07:39:30 +00:00
fd4a7f76a9
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
...
relegalizes the stuff it returns.
Add the ability to custom expand ADD/SUB, so that targets don't need to deal
with ADD_PARTS/SUB_PARTS if they don't want.
Fix some obscure potential bugs and simplify code.
llvm-svn: 25732
2006-01-28 05:07:51 +00:00
10f677508f
Instead of making callers of ExpandLibCall legalize the result, make
...
ExpandLibCall do it itself.
llvm-svn: 25731
2006-01-28 04:28:26 +00:00
a593acfe66
Eliminate the need to do another iteration of the legalizer after inserting
...
a libcall.
llvm-svn: 25730
2006-01-28 04:23:12 +00:00
98ed05c81d
remove method I just added
...
llvm-svn: 25728
2006-01-28 03:43:09 +00:00
43b867dd3b
add a new callback
...
llvm-svn: 25727
2006-01-28 03:37:03 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
af397cec0b
Add a missing case to the dag combiner.
...
llvm-svn: 25723
2006-01-28 01:06:30 +00:00
fb16a62fba
Remove the ISD::CALL and ISD::TAILCALL nodes
...
llvm-svn: 25721
2006-01-28 00:18:58 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
4df279cfda
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
...
ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
476e67be14
initial selectiondag support for new INLINEASM node. Note that inline asms
...
with outputs or inputs are not supported yet. :)
llvm-svn: 25664
2006-01-26 22:24:51 +00:00
c4c339c3d0
Clean up some code; improve efficiency; and fixed a potential bug involving
...
chain successors.
llvm-svn: 25630
2006-01-26 00:30:29 +00:00
5edde66863
Don't break the optimized build (by incorrect placement of #endif)
...
llvm-svn: 25613
2006-01-25 21:49:13 +00:00
1880f8db02
No need to keep track of top and bottom nodes in a group since the vector is
...
already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
fb20616aa6
Fix VC++ compilation error.
...
llvm-svn: 25604
2006-01-25 17:17:49 +00:00
ab49556cf4
Bottom up register usage reducing list scheduler.
...
llvm-svn: 25601
2006-01-25 09:14:32 +00:00
fbc88a624a
Keep track of bottom / top element of a set of flagged nodes.
...
llvm-svn: 25600
2006-01-25 09:13:41 +00:00
a6eff8a432
If scheduler choice is the default (-sched=default), use target scheduling
...
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
llvm-svn: 25599
2006-01-25 09:12:57 +00:00
f9a1e3aadc
Fix an infinite loop I caused by making sure to legalize the flag operand
...
of CALLSEQ_* nodes
llvm-svn: 25582
2006-01-24 05:48:21 +00:00
12f8441c03
Fix VC++ compilation error.
...
llvm-svn: 25577
2006-01-24 04:43:17 +00:00
683352382e
another couple selects
...
llvm-svn: 25551
2006-01-23 21:51:14 +00:00
c28563874c
another selectto
...
llvm-svn: 25548
2006-01-23 20:59:12 +00:00
b8566fa10a
Typo.
...
llvm-svn: 25545
2006-01-23 13:34:04 +00:00
31272347d4
Skeleton of the list schedule.
...
llvm-svn: 25544
2006-01-23 08:26:10 +00:00
421cfe8006
Minor clean up.
...
llvm-svn: 25543
2006-01-23 08:25:34 +00:00
763dfd7723
Fix Regression/CodeGen/SparcV8/2006-01-22-BitConvertLegalize.ll by making
...
sure that the result of expanding a BIT_CONVERT node is itself legalized.
llvm-svn: 25538
2006-01-23 07:30:46 +00:00
87063b9986
Remove a couple of unnecessary #include's
...
llvm-svn: 25535
2006-01-23 07:21:01 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
...
llvm-svn: 25532
2006-01-23 07:01:07 +00:00
deda32a786
Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on
...
PPC.
llvm-svn: 25522
2006-01-23 05:22:07 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
e23928c67f
Fix a bug in a recent refactor that caused a bunch of programs to miscompile
...
or the compiler to crash.
llvm-svn: 25503
2006-01-21 19:12:11 +00:00
44cab00045
Fix CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
...
llvm-svn: 25496
2006-01-21 04:27:00 +00:00
739a6a456e
Do some code refactoring on Jim's scheduler in preparation of the new list
...
scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
15afe462a8
remove some unintentionally committed code
...
llvm-svn: 25483
2006-01-20 18:40:10 +00:00
222ceabbee
If the target doesn't support f32 natively, insert the FP_EXTEND in target-indep
...
code, so that the LowerReturn code doesn't have to handle it.
llvm-svn: 25482
2006-01-20 18:38:32 +00:00
13e8c9d6de
Another typo
...
llvm-svn: 25440
2006-01-19 04:54:52 +00:00
7599b6e4af
was ignoring the legalized chain in this case, fixed SPASS on alpha
...
llvm-svn: 25428
2006-01-18 23:19:08 +00:00
569c439567
Get rid of code in the DAGCombiner that is duplicated in SelectionDAG.cpp
...
Now all constant folding in the code generator is in one place.
llvm-svn: 25426
2006-01-18 22:35:16 +00:00
e2ee190821
Temporary work around for a libcall insertion bug: If a target doesn't
...
support FSIN/FCOS nodes, do not lower sin/cos to them.
llvm-svn: 25425
2006-01-18 21:50:14 +00:00
5fee908be5
Fix a backwards conditional that caused an inf loop in some cases. This
...
fixes: test/Regression/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
llvm-svn: 25419
2006-01-18 19:13:41 +00:00
03e95af9f7
Support for the insertelement operation.
...
llvm-svn: 25405
2006-01-17 20:06:42 +00:00
6f86a7db07
Bug fix: missing LegalizeOp() on newly created nodes.
...
llvm-svn: 25401
2006-01-17 19:47:13 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
...
I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
b4f9a6f110
For PR411:
...
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.
llvm-svn: 25366
2006-01-16 21:12:35 +00:00
1e1eb5ee6c
Constant fold ctpop/ctlz/cttz, and a couple other small cleanups
...
llvm-svn: 25357
2006-01-16 08:07:10 +00:00
2642a35f4c
Expand case for 64b Legalize, even though no one should end up using this
...
(itanium supports bswap natively, alpha should custom lower it using the
VAX floating point swapload, ha ha).
llvm-svn: 25356
2006-01-16 07:59:13 +00:00
fcdb420baf
Disable two transformations that contribute to bus errors on SparcV8.
...
llvm-svn: 25339
2006-01-15 18:58:59 +00:00
59b82f9848
Allow the target to specify 'expand' if they just require the amount to
...
be subtracted from the stack pointer.
llvm-svn: 25331
2006-01-15 08:54:32 +00:00
Chris Lattner