57ff158255
Remove dead code.
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llvm-svn: 41899
2007-09-12 23:45:46 +00:00
dbfc4e4b07
Teach the dag scheduler to handle inline asm nodes with multi-value immediate operands.
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llvm-svn: 41386
2007-08-25 00:53:07 +00:00
358c3d1dac
Do not emit copies for physical register output if it's not used.
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llvm-svn: 40722
2007-08-02 05:29:38 +00:00
c5549fc3a0
Instead of adding copyfromreg's to handle physical definitions. Now isel can
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simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)
Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)
And let scheduledag emit the move from X86::EAX to a virtual register.
llvm-svn: 40710
2007-08-02 00:28:15 +00:00
18603b03e1
Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350
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llvm-svn: 40520
2007-07-26 08:12:07 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
5e9084207f
If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def.
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llvm-svn: 38496
2007-07-10 17:52:20 +00:00
ff6f279adf
When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value.
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llvm-svn: 38485
2007-07-10 07:08:32 +00:00
642be16bbf
Change CalculateHeights and CalculateDepths to be non-recursive.
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llvm-svn: 37934
2007-07-06 01:37:28 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
1baf5c84ab
Fix some VC++ warnings.
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llvm-svn: 35224
2007-03-20 20:43:18 +00:00
971aa18867
Code clean up.
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llvm-svn: 35220
2007-03-20 20:09:03 +00:00
25878b45f5
CopyToReg source operand can be a physical register.
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llvm-svn: 35213
2007-03-20 16:46:44 +00:00
56e5fea163
print target nodes nicely
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llvm-svn: 34369
2007-02-17 06:38:37 +00:00
68dcec6fea
fix indentation
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llvm-svn: 34307
2007-02-15 18:19:15 +00:00
21ebae3394
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
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abort case.
llvm-svn: 34306
2007-02-15 18:17:56 +00:00
09575bac2e
For PR1195:
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Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
llvm-svn: 34300
2007-02-15 03:39:18 +00:00
19083a4671
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
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speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
llvm-svn: 33879
2007-02-04 08:47:20 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
f5c96fabf9
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
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llvm-svn: 33482
2007-01-24 07:03:39 +00:00
be48a47d9d
Remove the DoubleTy special case.
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llvm-svn: 33449
2007-01-22 23:13:55 +00:00
a8a0f2cf68
Compensate for loss of DerivedTypes.h in TargetLowering.h
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llvm-svn: 33159
2007-01-12 23:31:12 +00:00
376c9c4c97
CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg.
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llvm-svn: 32929
2007-01-05 20:59:06 +00:00
22e978a736
Removing even more <iostream> includes.
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llvm-svn: 32320
2006-12-07 20:04:42 +00:00
67fc141db5
Match TargetInstrInfo changes.
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llvm-svn: 32098
2006-12-01 21:52:58 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
979bbf48d5
Add methods to add implicit def use operands to a MI.
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llvm-svn: 31675
2006-11-11 10:20:02 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
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llvm-svn: 31633
2006-11-10 08:43:01 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
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llvm-svn: 31453
2006-11-04 09:44:31 +00:00
1fd360e13a
handle global address constant sdnodes
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llvm-svn: 31323
2006-10-31 20:01:56 +00:00
47fbeda5ce
Debug tweak.
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llvm-svn: 30959
2006-10-14 08:34:06 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
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representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
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This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
1640ae5a84
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
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llvm-svn: 29545
2006-08-07 22:12:12 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
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llvm-svn: 29249
2006-07-21 20:57:35 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
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llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
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non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
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operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
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llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
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llvm-svn: 28585
2006-05-31 07:13:03 +00:00
d8e2f6ebc1
lib/Target/Target.td
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llvm-svn: 28386
2006-05-18 20:42:07 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
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This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
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llvm-svn: 28279
2006-05-13 08:22:24 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
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TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
095c9d9b7f
Duh. That could take a long time.
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llvm-svn: 28235
2006-05-12 06:05:18 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
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If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
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separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
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llvm-svn: 28105
2006-05-04 18:16:01 +00:00
Evan Cheng