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155 Commits

Author SHA1 Message Date
Craig Topper 367c86ddbe [AVX-512] Replace subvector broadcast builtins with shufflevectors and selects. 
Verified that the backend codegens this equally well.

llvm-svn: 292329
 2017-01-18 02:17:10 +00:00
Craig Topper 70536f4e47 [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects. 
llvm-svn: 290580
 2016-12-27 04:04:57 +00:00
Craig Topper c5ab78d4c3 Revert r290575 "[AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects." 
I failed to merge this with r290574.

llvm-svn: 290578
 2016-12-27 04:03:25 +00:00
Craig Topper 6ad5bcc8ac [AVX-512] Replace masked 512-bit pmuldq and pmuludq builtins with the newly added unmasked versions and selects. 
llvm-svn: 290575
 2016-12-27 03:46:16 +00:00
Craig Topper 678b07fe3c [AVX-512] Remove masking from 512-bit vpermil builtins. The backend now has versions without masking so wrap it with select. 
This will allow the backend to constant fold these to generic shuffle vectors like 128-bit and 256-bit without having to working about handling masking.

llvm-svn: 289351
 2016-12-11 01:26:52 +00:00
Craig Topper 6aefe00ccf [X86] Replace valignd/q builtins with appropriate __builtin_shufflevector. 
llvm-svn: 287733
 2016-11-23 01:47:12 +00:00
Simon Pilgrim 698528d83b [X86][AVX512] Replace lossless i32/u32 to f64 conversion intrinsics with generic IR 
Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the headers - a future patch will deal with removing the llvm intrinsics.

This is an extension patch to D20528 which dealt with the equivalent sse/avx cases.

Differential Revision: https://reviews.llvm.org/D26686

llvm-svn: 287088
 2016-11-16 09:27:40 +00:00
Craig Topper 5e0709d60b [AVX-512] Replace masked dword and qword variable shift builtins with unmasked builtins and a select. 
This is part of a set of changes to allow InstCombine in the backend to optimize variable shifts without having to know about masking.

llvm-svn: 286757
 2016-11-13 07:26:34 +00:00
Craig Topper 2c8f49e67b [AVX-512] Use scalar vfmsub/vfnmsub mask3 intrinsics instead of inverting the mask argument of a vfmadd intrinsic. 
Summary: Inverting the mask argument does not reflect the intended semantics of the intrinsic.

Reviewers: igorb, delena

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D26019

llvm-svn: 286733
 2016-11-12 23:24:34 +00:00
Craig Topper 1a44193afd [AVX-512] Convert the rest of the masked shift by immediate and by single element builtins over to the newly added unmasked builtins and a select. 
This should also fix PR30691 since the new builtins are handled like the legacy builtins in the backend.

llvm-svn: 286714
 2016-11-12 07:16:59 +00:00
Ayman Musa e60a41ca28 [X86][AVX512][Clang] Add support for mask_{move|store|load}_s{s/d} and int2mask/mask2int intrinsics. 
Differential Revision: https://reviews.llvm.org/D26021

llvm-svn: 286229
 2016-11-08 12:00:30 +00:00
Craig Topper 08bf53ffda [AVX-512] Remove masked vector insert builtins and replace with native shufflevectors and selects. 
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285667
 2016-11-01 05:47:56 +00:00
Craig Topper 93ffabd28d [AVX-512] Remove masked vector extract builtins and replace with native shufflevectors and selects. 
Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.

llvm-svn: 285540
 2016-10-31 04:30:56 +00:00
Craig Topper 531ce28311 [AVX-512] Replace 64-bit element and 512-bit vector pmin/pmax builtins with native IR like we do for 128/256-bit, but with the addition of masking. 
llvm-svn: 284956
 2016-10-24 04:04:24 +00:00
Craig Topper 0c5da26572 [AVX-512] Replace 512-bit pmovzx/sx builtins with native IR. 
llvm-svn: 284936
 2016-10-23 07:35:47 +00:00
Michael Zuckerman 9e43ccfe68 [Clang][AVX512][BuiltIn]Adding missing intrinsics move_{sd|ss} to clang 
Differential Revision: http://reviews.llvm.org/D21021

llvm-svn: 283314
 2016-10-05 12:56:06 +00:00
Craig Topper c4a8228bcc [AVX-512] Use native IR for masked 512-bit add/sub/mul/div ps/pd intrinsics when rounding mode isn't used. 
llvm-svn: 283073
 2016-10-02 17:43:00 +00:00
Craig Topper 4910755107 [AVX-512] Add _MM_FROUND_NO_EXC to test cases that pass a rounding mode intrinsics. This is preparation for a follow up commit that will check validity of rounding mode argument. 
llvm-svn: 283053
 2016-10-01 21:03:46 +00:00
Elad Cohen b107a22afb [X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests 
The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include
guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted
environment since it expects stdlib.h to be available - which is not the case
in these internal clang codegen tests).
This patch removes this hack and instead passes -ffreestanding to clang cc1.

Differential Revision: https://reviews.llvm.org/D24825

llvm-svn: 282581
 2016-09-28 11:59:09 +00:00
Ayman Musa 2e250e8845 [avx512] Add aliases to some missing avx512 intrinsics. 
Differential Revision:https: //reviews.llvm.org/D24961

llvm-svn: 282488
 2016-09-27 14:06:32 +00:00
Craig Topper 5fbabd77c7 [X86] Fix some illegal rounding modes in some builtin test cases to ones that would properly compile to valid assembly. 
llvm-svn: 282137
 2016-09-22 06:13:33 +00:00
Craig Topper f43e4a1728 [AVX-512] Remove masked integer mullo builtins and replace with native IR. 
llvm-svn: 280597
 2016-09-03 19:19:49 +00:00
Craig Topper 0e18976b8d [AVX-512] Remove masked integer add/sub builtins and replace with native IR. 
llvm-svn: 280596
 2016-09-03 18:29:35 +00:00
Asaf Badouh 2f344b788c [AVX512] integer comparisions enumeration. 
fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842

Differential Revision: https://reviews.llvm.org/D22212

 

llvm-svn: 277955
 2016-08-07 10:43:04 +00:00
Eric Christopher abb2b54ad3 After PR28761 use -Wall with -Werror in builtins tests to identify 
possible problems in headers.

llvm-svn: 277696
 2016-08-04 06:02:50 +00:00
Craig Topper 45db56c375 [X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume 64-bit GPRs are available. 
Usages of these intrinsics in a 32-bit build results in assertions in the backend.

llvm-svn: 276249
 2016-07-21 07:38:39 +00:00
Craig Topper 4d61a3c2d8 [AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove the builtins. 
llvm-svn: 275049
 2016-07-11 06:14:18 +00:00
Craig Topper 6e76fb61a7 [X86] Use __butilin_shufflevector for 512-bit shufps intrinsics. 
llvm-svn: 275012
 2016-07-10 05:57:21 +00:00
Simon Pilgrim f5a8837e1b [X86][AVX512] Converted the VBROADCAST intrinsics to generic IR 
llvm-svn: 274544
 2016-07-05 12:59:33 +00:00
Asaf Badouh 136332888a [X86][AVX512F] add float/double abs intrinsics 
add abs intrinsics that use native LLVM-IR.
change _mm512_mask[z]_and_epi{32|64} to use select intrinsic

Differential Revision: http://reviews.llvm.org/D21973

llvm-svn: 274542
 2016-07-05 12:24:14 +00:00
Craig Topper 2a383c9273 [X86] Use undefined instead of setzero in shufflevector based intrinsics when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z. 
llvm-svn: 274525
 2016-07-04 22:18:01 +00:00
Simon Pilgrim 427154db2a [X86][AVX512] Converted the VSHUFPD intrinsics to generic IR 
llvm-svn: 274523
 2016-07-04 21:30:47 +00:00
Simon Pilgrim 30db811526 [X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IR 
llvm-svn: 274502
 2016-07-04 13:34:44 +00:00
Simon Pilgrim 17388f2569 [X86][AVX512] Converted the VPERMILPD/VPERMILPS intrinsics to generic IR 
llvm-svn: 274492
 2016-07-04 11:06:15 +00:00
Simon Pilgrim 275d721485 [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR 
llvm companion patch imminent

llvm-svn: 274442
 2016-07-02 17:16:25 +00:00
Artur Pilipenko 70d4bb566c Update the expected masked load/store intrinsics names in tests 
The mangling of their names was changed in order to support arbitrary addrspace pointers as arguments in rL274043.

llvm-svn: 274044
 2016-06-28 18:28:45 +00:00
Craig Topper 79f53ca0b5 [AVX512] Replace masked unpack builtins with shufflevector and selects. 
llvm-svn: 273533
 2016-06-23 06:36:42 +00:00
Craig Topper d1691c7026 [AVX512] Replace masked integer cmp and ucmp builtins with native IR. 
llvm-svn: 273378
 2016-06-22 04:47:58 +00:00
Craig Topper a54c21e742 [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics. 
llvm-svn: 272787
 2016-06-15 14:06:34 +00:00
Michael Zuckerman 223676d2cc [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps 
Differential Revision: http://reviews.llvm.org/D20626

llvm-svn: 272658
 2016-06-14 12:38:58 +00:00
Asaf Badouh 880f0c252b [X86][AVX512F] bugfix - sqrtps should get __mask16 as mask parameter 
CR: Michael Zuckerman
llvm-svn: 272549
 2016-06-13 15:15:57 +00:00
Simon Pilgrim beca5f295c [Clang][X86] Convert non-temporal store builtins to generic __builtin_nontemporal_store in headers 
We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp

The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores.

The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load

Differential Revision: http://reviews.llvm.org/D21272

llvm-svn: 272540
 2016-06-13 09:57:52 +00:00
Craig Topper 7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. 
llvm-svn: 272467
 2016-06-11 12:50:19 +00:00
Igor Breger aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics. 
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
 2016-06-08 13:59:20 +00:00
Michael Zuckerman 95721ac863 [Clang][AVX512]Adding set4 intrinsics 
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
 2016-06-05 15:43:30 +00:00
Michael Zuckerman f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32 
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
 2016-06-05 15:12:52 +00:00
Asaf Badouh 89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer 
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
 2016-06-02 08:11:35 +00:00
Michael Zuckerman 6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang 
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
 2016-06-01 14:41:41 +00:00
Michael Zuckerman e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang 
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
 2016-06-01 08:34:03 +00:00
Michael Zuckerman c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang 
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
 2016-06-01 07:35:44 +00:00