Commit Graph

46 Commits

Author SHA1 Message Date
Zakk Chen cfe7f69036 [RISCV][NFC] Refactor RISCVISAInfo.
1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://reviews.llvm.org/D119250
2022-02-08 18:37:43 -08:00
Zakk Chen 57b5f4b2ec [RISCV][Clang] Compute the default target-abi if it's empty.
Every generated IR has a corresponding target-abi value, so
encoding a non-empty value would improve the robustness and
correctness.

Reviewed By: asb, jrtc27, arichardson

Differential Revision: https://reviews.llvm.org/D105555
2021-12-10 08:54:23 -08:00
Craig Topper 1053e0b27c [RISCV] Use a lambda to avoid having the Support library depend on Option library.
RISCVISAInfo::toFeatures needs to allocate strings using
ArgList::MakeArgString, but toFeatures lives in Support and
MakeArgString lives in Option.

toFeature only has one caller, so the simple fix is to have that
caller pass a lamdba that wraps MakeArgString to break the
dependency.

Differential Revision: https://reviews.llvm.org/D112032
2021-10-18 13:39:37 -07:00
Kito Cheng 8efa6512e0 [RISCV][NFC] Fix build error 2021-10-17 16:38:53 +08:00
Kito Cheng ff13189c5d [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.
How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::initFeatureMap@RISCV.cpp for handling feature vector.
- RISCVTargetInfo::getTargetDefines@RISCV.cpp for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
  canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
  canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to RISCVSupportedExtension@RISCVISAInfo.cpp or
  SupportedExperimentalExtensions@RISCVISAInfo.cpp .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168
2021-10-17 16:25:23 +08:00
Craig Topper f7ba572483 [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.
I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tests are updated or split accordingly.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D110669
2021-10-14 09:25:03 -07:00
Craig Topper f2ad8c9dc6 [RISCV] Remove experimental-b extension that includes all Zb* extensions
At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ratified
together as a package. Unknown at this time when or if the other
Zb* extensions will be ratified.

This patch removes references to the B extension. I've updated and
split tests accordingly.

This has been split from D110669 to make review a little easier.

Differential Revision: https://reviews.llvm.org/D111338
2021-10-07 20:47:17 -07:00
Craig Topper a21c557955 [RISCV] Remove Zbproposedc extension
This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't think it makes sense to keep them in bitmanip. It
will eventually cause a conflict if/when Zce is implemented in llvm.

Differential Revision: https://reviews.llvm.org/D110871
2021-09-30 14:23:05 -07:00
ShihPo Hung f1cbea3e52 [RISCV] Remove Zvamo implication for v1.0-rc change
As v1.0-rc specs say Zvamo is removed from standard extension,
Zvamo has to be specified explicitly.

Reviewed By: evandro

Differential Revision: https://reviews.llvm.org/D105396
2021-07-07 00:14:58 +08:00
Martin Storsjö e5c7c171e5 [clang] Rename StringRef _lower() method calls to _insensitive()
This is mostly a mechanical change, but a testcase that contains
parts of the StringRef class (clang/test/Analysis/llvm-conventions.cpp)
isn't touched.
2021-06-25 00:22:01 +03:00
Hsiangkai Wang 282aca10ae [RISCV] Update the version number to v0.10 for vector.
v0.10 is tagged in V specification. Update the version to v0.10.

Differential Revision: https://reviews.llvm.org/D95680
2021-01-30 07:20:05 +08:00
Hsiangkai Wang f19849a07b [RISCV] Update V extension to v1.0-draft 08a0b464.
Differential Revision: https://reviews.llvm.org/D94583
2021-01-26 12:02:43 +08:00
Simon Cook 666815d61b [RISCV] Implement new architecture extension macros
This adds support for the new architecture extension test macros as
defined in the C-API Document:
https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md

Extension versions have been taken from what are used in
RISCVTargetStreamer for ratified extensions, and the -march parser
for experimental extensions.

Differential Revision: https://reviews.llvm.org/D94403
2021-01-25 08:58:46 +00:00
Simon Cook afd483e57d [RISCV] Add support for Zvamo/Zvlsseg to driver
Differential Revision: https://reviews.llvm.org/D94930
2021-01-24 22:07:56 +00:00
Craig Topper 20f2e32d2c [RISCV] Update B extension version to 0.93.
Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D95002
2021-01-22 12:49:10 -08:00
Craig Topper 4e6ad11bc6 [RISCV] Add Zba feature and move add.uw and slli.uw to it.
Still need to add SH*ADD instructions.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94617
2021-01-22 12:49:10 -08:00
Hsiangkai Wang 432d05174e [RISCV] Handle zfh in the arch string.
Differential Revision: https://reviews.llvm.org/D91315
2020-12-03 09:16:44 +08:00
Hsiangkai Wang 721d93fc5a Support experimental v extension v0.9.
Differential revision: https://reviews.llvm.org/D81213
2020-08-01 07:42:06 +08:00
Benjamin Kramer 9a0689e072 Make helpers static. NFC. 2020-07-17 13:49:11 +02:00
Zakk Chen 294d1eae75 [RISCV] Add support for -mcpu option.
Summary:
1. gcc uses `-march` and `-mtune` flag to chose arch and
pipeline model, but clang does not have `-mtune` flag,
we uses `-mcpu` to chose both infos.
2. Add SiFive e31 and u54 cpu which have default march
and pipeline model.
3. Specific `-mcpu` with rocket-rv[32|64] would select
pipeline model only, and use the driver's arch choosing
logic to get default arch.

Reviewers: lenary, asb, evandro, HsiangKai

Reviewed By: lenary, asb, evandro

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D71124
2020-07-16 11:46:22 -07:00
Simon Cook de7bf722c2 [RISCV] Add error checking for extensions missing separating underscores
Currently if two multi-letter extensions are provided in a -march=
string, the verification code checks the version of the first and
consumes the second, resulting in that part of the architecture
string being ignored. This adds a test that when a version number has
been parsed for an extension, there are no subsequent characters.

Differential Revision: https://reviews.llvm.org/D83819
2020-07-15 09:23:35 +01:00
Hsiangkai Wang d698ff92a5 [RISCV] Support experimental v extensions.
This follows the design as discussed on the mailing lists in the
following RFC:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Support for the vector 'v' extension v0.8.

Differential revision: https://reviews.llvm.org/D81188
2020-06-28 00:54:07 +08:00
Simon Cook dd1ee6dc07 [RISCV] Support experimental/unratified extensions
This adds support for enabling experimental/unratified RISC-V ISA
extensions in the -march string in the case where an explicit version
number has been declared, and the -menable-experimental-extensions flag
has been provided.

This follows the design as discussed on the mailing lists in the
following RFC: http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Since the RISC-V toolchain definition currently rejects any extension
with an explicit version number, the parsing logic has been tweaked to
support this, and to allow standard extensions to have their versions
checked in future patches.

The bitmanip 'b' extension has been added as a first use of this support,
it should easily extend to other as yet unratified extensions (such as
the vector 'v' extension).

Differential Revision: https://reviews.llvm.org/D73891
2020-04-09 18:04:22 +01:00
lewis-revill 07f7c00208 [RISCV] Add support for save/restore of callee-saved registers via libcalls
This patch adds the support required for using the __riscv_save and
__riscv_restore libcalls to implement a size-optimization for prologue
and epilogue code, whereby the spill and restore code of callee-saved
registers is implemented by common functions to reduce code duplication.

Logic is also included to ensure that if both this optimization and
shrink wrapping are enabled then the prologue and epilogue code can be
safely inserted into the basic blocks chosen by shrink wrapping.

Differential Revision: https://reviews.llvm.org/D62686
2020-02-11 21:23:03 +00:00
Benjamin Kramer adcd026838 Make llvm::StringRef to std::string conversions explicit.
This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly mechanical from a custom clang-tidy check, with a lot of
manual fixups. It uncovers a lot of minor inefficiencies.

This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2020-01-28 23:25:25 +01:00
Scott Egerton cbe681bd83 Revert "[RISCV] Add Clang frontend support for Bitmanip extension"
This reverts commit 57cf6ee9c8.
2020-01-15 10:43:42 +00:00
Scott Egerton 57cf6ee9c8 [RISCV] Add Clang frontend support for Bitmanip extension
Summary: This adds the __riscv_bitmanip macro and the 'b' target feature to enable it.

Reviewers: asb, simoncook, lewis-revill, PaoloS, lenary

Reviewed By: lenary

Subscribers: Jim, rbar, johnrusso, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, pzheng, sameer.abuasal, apazos, luismarques, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D71553
2020-01-14 17:45:45 +00:00
Sam Elliott e3d5ff5a0b [RISCV] Match GCC `-march`/`-mabi` driver defaults
Summary:
Clang/LLVM is a cross-compiler, and so we don't have to make a choice
about `-march`/`-mabi` at build-time, but we may have to compute a
default `-march`/`-mabi` when compiling a program. Until now, each
place that has needed a default `-march` has calculated one itself.

This patch adds a single place where a default `-march` is calculated,
in order to avoid calculating different defaults in different places.

This patch adds a new function `riscv::getRISCVArch` which encapsulates
this logic based on GCC's for computing a default `-march` value
when none is provided. This patch also updates the logic in
`riscv::getRISCVABI` to match the logic in GCC's build system for
computing a default `-mabi`.

This patch also updates anywhere that `-march` is used to now use the
new function which can compute a default. In particular, we now
explicitly pass a `-march` value down to the gnu assembler.

GCC has convoluted logic in its build system to choose a default
`-march`/`-mabi` based on build options, which would be good to match.
This patch is based on the logic in GCC 9.2.0. This commit's logic is
different to GCC's only for baremetal targets, where we default
to rv32imac/ilp32 or rv64imac/lp64 depending on the target triple.

Tests have been updated to match the new logic.

Reviewers: asb, luismarques, rogfer01, kito-cheng, khchen

Reviewed By: asb, luismarques

Subscribers: sameer.abuasal, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D69383
2019-11-15 15:10:42 +00:00
Simon Cook aed9d6d64a [RISCV] Add support for -ffixed-xX flags
This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. The backend checks that it does not need to write to
any reserved register; if it does a relevant error is generated.

Differential Revision: https://reviews.llvm.org/D67185
2019-10-22 21:25:01 +01:00
Roger Ferrer Ibanez 93c4d53b0a [RISCV] Make -march=rv{32,64}gc the default in RISC-V Linux
This is the logical follow-up of D65634.

Differential Revision: https://reviews.llvm.org/D66003

llvm-svn: 371496
2019-09-10 08:16:24 +00:00
Roger Ferrer Ibanez 8e87396307 [RISCV] Default to ilp32d/lp64d in RISC-V Linux
When running clang as a native compiler in RISC-V Linux the flag
-mabi=ilp32d / -mabi=lp64d is always mandatory. This change makes it the
default there.

Differential Revision: https://reviews.llvm.org/D65634

llvm-svn: 371494
2019-09-10 07:57:36 +00:00
Roger Ferrer Ibanez 60f0a6f6ff [RISCV] Move architecture parsing code into its own function
I plan to reuse it in a later patch.

This is almost NFC except a small change in control flow when diagnosing
+d without +f.

Differential Revision: https://reviews.llvm.org/D66002

llvm-svn: 371492
2019-09-10 07:47:34 +00:00
Roger Ferrer Ibanez 371bdc9b7f [RISCV] Remove duplicated logic when determining the target ABI
We were calculating twice ilp32/lp64. Do this in one place instead.

Differential Revision: https://reviews.llvm.org/D48357

llvm-svn: 368128
2019-08-07 07:08:00 +00:00
Sam Elliott 28145735f7 [RISCV] Avoid save-restore target feature warning
Summary:
LLVM issues a warning if passed unknown target features. Neither I nor
@asb noticed this until after https://reviews.llvm.org/D63498 landed.

This patch stops passing the (unknown) "save-restore" target feature to
the LLVM backend, but continues to emit a warning if a driver asks for
`-msave-restore`. The default of assuming `-mno-save-restore` (and
emitting no warnings) remains.

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, cfe-commits, asb

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64008

llvm-svn: 364777
2019-07-01 14:53:56 +00:00
Sam Elliott 3e53e0e4d4 [RISC-V] Add -msave-restore and -mno-save-restore to clang driver
Summary:
The GCC RISC-V toolchain accepts `-msave-restore` and `-mno-save-restore`
to control whether libcalls are used for saving and restoring the stack within
prologues and epilogues.

Clang currently errors if someone passes -msave-restore or -mno-save-restore.
This means that people need to change build configurations to use clang. This
patch adds these flags, so that clang invocations can now match gcc.

As the RISC-V backend does not currently have a `save-restore` target feature,
we emit a warning if someone requests `-msave-restore`. LLVM does not error if
we pass the (unimplemented) target features `+save-restore` or `-save-restore`.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63498

llvm-svn: 364018
2019-06-21 10:03:31 +00:00
Fangrui Song f29120658b [Driver][RISCV] Simplify. NFC
llvm-svn: 361710
2019-05-26 07:43:45 +00:00
Shiva Chen e3aaeabb6d [RISCV] Default enable RISCV linker relaxation
Differential Revision: https://reviews.llvm.org/D47127

llvm-svn: 354222
2019-02-17 16:05:51 +00:00
Fangrui Song 9ac13a1244 Use llvm::is_contained. NFC
llvm-svn: 353635
2019-02-10 05:54:57 +00:00
Chandler Carruth 2946cd7010 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
2019-01-19 08:50:56 +00:00
Fangrui Song 6907ce2f8f Remove trailing space
sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h}

llvm-svn: 338291
2018-07-30 19:24:48 +00:00
Shiva Chen f78fc3842f [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation
Differential Revision: https://reviews.llvm.org/D44888

llvm-svn: 333385
2018-05-29 00:44:15 +00:00
Richard Trieu 563296abd8 Switch to Clang's isDigit function.
std::isdigit can be overloaded, causing the template deduction to fail.  Use
Clang's isDigit function which to avoid this.  Switch the other calls for
consistency.

llvm-svn: 330887
2018-04-25 23:50:55 +00:00
Reid Kleckner f0562390e2 Include <cctype> to get std::isdigit, fixes MSVC STL build
llvm-svn: 330886
2018-04-25 23:38:54 +00:00
Ana Pazos c85505450a [RISCV] More validations on the input value of -march=
Supporting additional rules for parsing ISA string.

- RISC-V ISA strings must be lowercase.
E.g.: rv32IMC is not supported, rv32imc is correct.

- Multi-letter extensions are to be separated by a single
underscore '_'. The extension prefix counts as a letter.
This means extensions that start with 's', 'sx' and 'sx'
are all multi-letter.
E.g.:
xasb is a single non-standard extension named 'xasb'
xa_sb are two extensions, the non-standard user level extension
'xa', and the supervisor level extension 'sb'.

- Standard user-level extensions are specified following
a canonical order, according to Table 22.1 in
RISC-V User-Level ISA V2.2.

- Non-standard user-level 'x' extensions,
standard supervisor-level 's' extensions and
non-standard supervisor-level 'sx' extensions
are also specified following a canonical order according
to Table 22.1 in RISC-V User-Level ISA V2.2:
'x' extensions, follwed by 's' extensions and then 'sx' extensions.

- Extensions might have a version number.
Underscores may be used to separate ISA subset components to
improve readability and to provide disambiguation.
E.g.: rv32i2_m3_a1_f2_d2

- Version numbers are divided into major and minor numbers,
separated by a 'p'. If the minor version is 0, then 'p0' can
be omitted.

- Additional checks for dependent extensions and invalid
extensions combinations.
E.g.:
'e' requires rv32
'e' can't be combined with 'f' nor 'd'
'q' requires rv64

- TODO items have also been marked with comments in the code.

Reviewers: asb, kito-cheng

Reviewed By: asb

Subscribers: edward-jones, mgrang, zzheng, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, shiva0217, cfe-commits

Differential Revision: https://reviews.llvm.org/D45284

llvm-svn: 330880
2018-04-25 22:42:38 +00:00
Shiva Chen 203917e26e [PATCH] [RISCV] Verify the input value of -march=
Summary:
This patch doing more check and verify the -march= string and will issue
an error if it's a invalid combination.

Reviewers: asb, apazos

Differential Revision: https://reviews.llvm.org/D44189

Patch by Kito Cheng.

llvm-svn: 328690
2018-03-28 08:29:50 +00:00
Alex Bradbury 71f45455e1 [RISCV] Add the RISCV target and compiler driver
As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver 
support (RV64 to follow).

Differential Revision: https://reviews.llvm.org/D39963

llvm-svn: 322276
2018-01-11 13:36:56 +00:00