c8db10725b
Add information preventing several register class constraints from working.
...
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
llvm-svn: 29118
2006-07-12 16:59:49 +00:00
298ef37e02
Implement the inline asm 'A' constraint. This implements PR825 and
...
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
llvm-svn: 29101
2006-07-11 02:54:03 +00:00
79cf9a5342
Fixed stack objects do not specify alignments, but their offsets are known.
...
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
llvm-svn: 29090
2006-07-10 21:37:44 +00:00
9aabc1e16f
Mark internal function static
...
llvm-svn: 29085
2006-07-10 19:53:12 +00:00
5987cfb7b1
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
...
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 08:33:52 +00:00
0261242aa6
Reorg. No functionality change.
...
llvm-svn: 28999
2006-07-05 22:17:51 +00:00
38c5aee959
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
...
llvm-svn: 28910
2006-06-24 08:36:10 +00:00
de7156f12c
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 28796
2006-06-15 08:14:54 +00:00
ca25486603
Add argument registers to the end of call operand list (partial fix).
...
llvm-svn: 28783
2006-06-14 18:17:40 +00:00
0e14a56d35
Minor compilation speed improvement.
...
llvm-svn: 28736
2006-06-09 06:24:42 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
...
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
2b2c1be49c
Typos
...
llvm-svn: 28617
2006-06-01 05:53:27 +00:00
2489ccdd90
Remove a warning
...
llvm-svn: 28607
2006-06-01 00:30:39 +00:00
550cb663e8
Remove dead code.
...
llvm-svn: 28581
2006-05-31 00:50:42 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
b92f418408
Vector argument must be passed in memory location aligned on 16-byte boundary.
...
llvm-svn: 28505
2006-05-26 20:37:47 +00:00
bfb5ea6875
Mac OS X ABI document lied. The first four XMM registers are used to pass
...
vector arguments, not three.
llvm-svn: 28504
2006-05-26 19:22:06 +00:00
a01e799927
Minor update to make the code more clear
...
llvm-svn: 28499
2006-05-26 18:39:59 +00:00
cbfb3d07e0
Update more comments.
...
llvm-svn: 28498
2006-05-26 18:37:16 +00:00
763f9b00f0
Fix some comments.
...
llvm-svn: 28497
2006-05-26 18:25:43 +00:00
83dc51d7ff
No need to handle illegal types.
...
llvm-svn: 28496
2006-05-26 18:22:49 +00:00
8aca43e8da
Consistency
...
llvm-svn: 28488
2006-05-25 23:31:23 +00:00
0421aca87a
Some clean up.
...
llvm-svn: 28483
2006-05-25 22:38:31 +00:00
29f805ec65
Remove some dead code.
...
llvm-svn: 28481
2006-05-25 22:25:52 +00:00
5ee96893ae
Build breakage.
...
llvm-svn: 28475
2006-05-25 18:56:34 +00:00
2a33094284
Switch X86 over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
llvm-svn: 28463
2006-05-25 00:59:30 +00:00
a58f559848
Fix file header comment
...
llvm-svn: 28441
2006-05-23 23:20:42 +00:00
7068a93cae
Better way to check for vararg.
...
llvm-svn: 28440
2006-05-23 21:08:24 +00:00
17e734f0a6
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
...
FORMAL_ARGUMENTS nodes include a token operand.
llvm-svn: 28439
2006-05-23 21:06:34 +00:00
8be5be817c
Implement an annoying part of the Darwin/X86 abi: the callee of a struct
...
return argument pops the hidden struct pointer if present, not the caller.
For example, in this testcase:
struct X { int D, E, F, G; };
struct X bar() {
struct X a;
a.D = 0;
a.E = 1;
a.F = 2;
a.G = 3;
return a;
}
void foo(struct X *P) {
*P = bar();
}
We used to emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
addl $28, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
ret
This is correct on Linux/X86 but not Darwin/X86. With this patch, we now
emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
*** addl $24, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
*** ret $4
For the record, GCC emits (which is functionally equivalent to our new code):
_bar:
movl 4(%esp), %eax
movl $3, 12(%eax)
movl $2, 8(%eax)
movl $1, 4(%eax)
movl $0, (%eax)
ret $4
_foo:
pushl %esi
subl $40, %esp
movl 48(%esp), %esi
leal 16(%esp), %eax
movl %eax, (%esp)
call _bar
subl $4, %esp
movl 16(%esp), %eax
movl %eax, (%esi)
movl 20(%esp), %eax
movl %eax, 4(%esi)
movl 24(%esp), %eax
movl %eax, 8(%esi)
movl 28(%esp), %eax
movl %eax, 12(%esi)
addl $40, %esp
popl %esi
ret
This fixes SingleSource/Benchmarks/CoyoteBench/fftbench with LLC and the
JIT, and fixes the X86-backend portion of PR729. The CBE still needs to
be updated.
llvm-svn: 28438
2006-05-23 18:50:38 +00:00
01dd6df5f3
CSRet allows varargs
...
llvm-svn: 28409
2006-05-19 21:34:04 +00:00
8c6b234ce8
Should pass by reference.
...
llvm-svn: 28357
2006-05-17 19:07:40 +00:00
c7df70db57
Implement the custom lowering hook right, returning values for all of the
...
arguments at once.
llvm-svn: 28327
2006-05-16 17:14:26 +00:00
7b8b8bbbf9
Fix a bug I introduced yesterday, which broke functions with *no* arguments.
...
llvm-svn: 28326
2006-05-16 17:08:35 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
22f95b74ba
Dead variable
...
llvm-svn: 28265
2006-05-12 21:12:22 +00:00
6d4a2dc4ad
Teach the X86 backend about non-i32 inline asm register classes.
...
llvm-svn: 28139
2006-05-06 00:29:37 +00:00
44a73e9fa5
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
llvm-svn: 28131
2006-05-05 21:35:18 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
88decded82
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
...
passing by value.
llvm-svn: 28015
2006-04-28 21:29:37 +00:00
3cd4362ade
Implement four-wide shuffle with 2 shufps if no more than two elements come
...
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
llvm-svn: 28011
2006-04-28 07:03:38 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
f4f3f0d25f
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
llvm-svn: 27994
2006-04-27 08:40:39 +00:00
89001ad729
Support for passing 128-bit vector arguments via XMM registers.
...
llvm-svn: 27992
2006-04-27 08:31:10 +00:00
a0374e1bed
Oops
...
llvm-svn: 27989
2006-04-27 05:44:50 +00:00
24eb3f4765
Bug fix: not updating NumIntRegs.
...
llvm-svn: 27988
2006-04-27 05:35:28 +00:00
48940d16b2
- Clean up formal argument lowering code. Prepare for vector pass by value work.
...
- Fixed vararg support.
llvm-svn: 27985
2006-04-27 01:32:22 +00:00
1c39903297
Fix fastcc failures.
...
llvm-svn: 27980
2006-04-26 18:21:31 +00:00
e0bcfbe811
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
...
llvm-svn: 27975
2006-04-26 01:20:17 +00:00
a9467aab0a
Separate LowerOperation() into multiple functions, one per opcode.
...
llvm-svn: 27972
2006-04-25 20:13:52 +00:00
5c2bfb069e
Special case handling two wide build_vector(0, x).
...
llvm-svn: 27961
2006-04-24 22:58:52 +00:00
b0461080e4
A little bit more build_vector enhancement for v8i16 cases.
...
llvm-svn: 27959
2006-04-24 18:01:45 +00:00
b4f31dd1a8
MOVL shuffle (i.e. movd or movss / movsd from memory) of undef, V2 == V2
...
llvm-svn: 27953
2006-04-23 06:35:19 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
e728efdfce
Don't do all the lowering stuff for 2-wide build_vector's. Also, minor optimization for shuffle of undef.
...
llvm-svn: 27946
2006-04-22 08:34:05 +00:00
16ef94f4e8
Fix a performance regression. Use {p}shuf* when there are only two distinct elements in a build_vector.
...
llvm-svn: 27945
2006-04-22 06:21:46 +00:00
14215c36b6
Revamp build_vector lowering to take advantage of movss and movd instructions.
...
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
llvm-svn: 27939
2006-04-21 23:03:30 +00:00
e8b5180044
Now generating perfect (I think) code for "vector set" with a single non-zero
...
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 01:05:10 +00:00
60f0b8998e
- Added support to turn "vector clear elements", e.g. pand V, <-1, -1, 0, -1>
...
to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.
llvm-svn: 27875
2006-04-20 08:58:49 +00:00
15c264b753
Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,
...
but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.
llvm-svn: 27849
2006-04-20 00:11:39 +00:00
4a1b0d3292
isSplatMask() bug: first element can be an undef.
...
llvm-svn: 27847
2006-04-19 23:28:59 +00:00
a3caaee503
- Added support to do aribitrary 4 wide shuffle with no more than three
...
instructions.
- Fixed a commute vector_shuff bug.
llvm-svn: 27845
2006-04-19 22:48:17 +00:00
7855e4d032
Commute vector_shuffle to match more movlhps, movlp{s|d} cases.
...
llvm-svn: 27840
2006-04-19 20:35:22 +00:00
5421206c4b
Use movss to insert_vector_elt(v, s, 0).
...
llvm-svn: 27782
2006-04-17 22:45:49 +00:00
6e5e205841
Use two pinsrw to insert an element into v4i32 / v4f32 vector.
...
llvm-svn: 27779
2006-04-17 22:04:06 +00:00
5022b3426e
Implement v8i16, v16i8 splat using unpckl + pshufd.
...
llvm-svn: 27768
2006-04-17 20:43:08 +00:00
c070c621ac
implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
...
llvm-svn: 27767
2006-04-17 20:32:50 +00:00
b3b41c4f3d
FP SETOLT, SETOLT, SETUGE, SETUGT conditions were implemented incorrectly
...
llvm-svn: 27755
2006-04-17 07:24:10 +00:00
6222cf2a36
Silly bug
...
llvm-svn: 27719
2006-04-15 05:37:34 +00:00
65bb720a8b
Do not use movs{h|l}dup for a shuffle with a single non-undef node.
...
llvm-svn: 27718
2006-04-15 03:13:24 +00:00
5d247f81c1
Last few SSE3 intrinsics.
...
llvm-svn: 27711
2006-04-14 21:59:03 +00:00
e4f97ccf7f
X86 SSE2 supports v8i16 multiplication
...
llvm-svn: 27644
2006-04-13 05:10:25 +00:00
92232307d0
All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
...
Clean up and fix various logical ops issues.
llvm-svn: 27633
2006-04-12 21:21:57 +00:00
e2157c6e41
Promote v4i32, v8i16, v16i8 load to v2i64 load.
...
llvm-svn: 27612
2006-04-12 17:12:36 +00:00
12ba3e23d0
Added support for _mm_move_ss and _mm_move_sd.
...
llvm-svn: 27575
2006-04-11 00:19:04 +00:00
617a6a812e
Conditional move of vector types.
...
llvm-svn: 27556
2006-04-10 07:23:14 +00:00
ac847268c5
Code clean up.
...
llvm-svn: 27501
2006-04-07 21:53:05 +00:00
c995b45f67
- movlp{s|d} and movhp{s|d} support.
...
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
llvm-svn: 27474
2006-04-06 23:23:56 +00:00
780382946e
Support for comi / ucomi intrinsics.
...
llvm-svn: 27444
2006-04-05 23:38:46 +00:00
f3b52c84ea
Handle canonical form of e.g.
...
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 07:20:06 +00:00
6d196db40d
Bogus assert
...
llvm-svn: 27434
2006-04-05 06:11:20 +00:00
2cf4232ced
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
...
llvm-svn: 27433
2006-04-05 06:09:26 +00:00
59a6355e82
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
...
llvm-svn: 27427
2006-04-05 01:47:37 +00:00
b64827e662
Use movlpd to: store lower f64 extracted from v2f64.
...
Use movhpd to: store upper f64 extracted from v2f64.
llvm-svn: 27382
2006-04-03 22:30:54 +00:00
ebf1006d16
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
5fd7c69473
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
...
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
llvm-svn: 27314
2006-03-31 21:55:24 +00:00
cbffa4656b
Add support to use pextrw and pinsrw to extract and insert a word element
...
from a 128-bit vector.
llvm-svn: 27304
2006-03-31 19:22:53 +00:00
1b0d294de0
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
...
llvm-svn: 27275
2006-03-31 01:30:39 +00:00
d9d0bbb5ac
Typo
...
llvm-svn: 27272
2006-03-31 00:33:57 +00:00
99d7205fba
Ok for vector_shuffle mask to contain undef elements.
...
llvm-svn: 27271
2006-03-31 00:30:29 +00:00
7e2ff11a42
Make sure all possible shuffles are matched.
...
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
llvm-svn: 27259
2006-03-30 19:54:57 +00:00
b7fedffc78
- Added some SSE2 128-bit packed integer ops.
...
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
llvm-svn: 27252
2006-03-29 23:07:14 +00:00
acc336475e
Need to special case splat after all. Make the second operand of splat
...
vector_shuffle undef.
llvm-svn: 27250
2006-03-29 19:02:40 +00:00
500ec16578
- More shuffle related bug fixes.
...
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
llvm-svn: 27246
2006-03-29 03:04:49 +00:00
da59b0d2a8
- Only use pshufd for v4i32 vector shuffles.
...
- Other shuffle related fixes.
llvm-svn: 27244
2006-03-29 01:30:51 +00:00
8160fd3d42
Fixing buggy code.
...
llvm-svn: 27239
2006-03-28 23:41:33 +00:00
457e54efc1
Added missing paren on behalf of Ramana Radhakrishnan.
...
llvm-svn: 27223
2006-03-28 10:17:11 +00:00
21e5476deb
Missed X86::isUNPCKHMask
...
llvm-svn: 27222
2006-03-28 08:27:15 +00:00
1a194a5264
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
...
* Bug fixes.
llvm-svn: 27218
2006-03-28 06:50:32 +00:00
Chris Lattner