2f93128109
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
...
llvm-svn: 123170
2011-01-10 12:39:04 +00:00
1f4dfbbcb0
DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code.
...
example code:
unsigned foo(unsigned x, unsigned y) {
if (x != 0) y--;
return y;
}
before:
_foo: ## @foo
cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01]
sbbl %eax, %eax ## encoding: [0x19,0xc0]
notl %eax ## encoding: [0xf7,0xd0]
addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08]
ret ## encoding: [0xc3]
after:
_foo: ## @foo
cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01]
movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08]
adcl $-1, %eax ## encoding: [0x83,0xd0,0xff]
ret ## encoding: [0xc3]
llvm-svn: 122455
2010-12-22 23:17:45 +00:00
cafc1e60bb
Fix a bug in ReduceLoadWidth that wasn't handling extending
...
loads properly. We miscompiled the testcase into:
_test: ## @test
movl $128, (%rdi)
movzbl 1(%rdi), %eax
ret
Now we get a proper:
_test: ## @test
movl $128, (%rdi)
movsbl (%rdi), %eax
movzbl %ah, %eax
ret
This fixes PR8757.
llvm-svn: 122392
2010-12-22 08:02:57 +00:00
9a499e96eb
more cleanups, move a check for "roundedness" earlier to reject
...
unhanded cases faster and simplify code.
llvm-svn: 122391
2010-12-22 08:01:44 +00:00
222374d886
reduce indentation and improve comments, no functionality change.
...
llvm-svn: 122389
2010-12-22 07:36:50 +00:00
a94e36bbee
Reapply 122353-122355 with fixes. 122354 was wrong;
...
the shift type was needed one place, the shift count
type another. The transform in 123555 had the same
problem.
llvm-svn: 122366
2010-12-21 21:55:50 +00:00
87c47499c6
Revert 122353-122355 for the moment, they broke stuff.
...
llvm-svn: 122360
2010-12-21 21:22:27 +00:00
caf42aa6a4
Add a new transform to DAGCombiner.
...
llvm-svn: 122355
2010-12-21 20:10:51 +00:00
fa5dc82fda
Get the type of a shift from the shift, not from its shift
...
count operand. These should be the same but apparently are
not always, and this is cleaner anyway. This improves the
code in an existing test.
llvm-svn: 122354
2010-12-21 20:06:19 +00:00
d64931df77
Shift by the word size is invalid IR; don't create it.
...
llvm-svn: 122353
2010-12-21 20:00:06 +00:00
2a7ff99979
fix some typos
...
llvm-svn: 122349
2010-12-21 18:05:22 +00:00
3e5fbd74ed
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
...
something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
2010-12-21 02:38:05 +00:00
0a291a36f2
Cosmetic changes.
...
llvm-svn: 122259
2010-12-20 20:10:50 +00:00
5408144add
Fix a DAGCombiner crash when folding binary vector operations with constant
...
BUILD_VECTOR operands where the element type is not legal. I had previously
changed this code to insert TRUNCATE operations, but that was just wrong.
llvm-svn: 122102
2010-12-17 23:06:49 +00:00
cd538afa52
Add a transform to DAG Combiner. This improves the
...
code for the case where 32-bit divide by constant is
turned into 64-bit multiply by constant. 8771012.
llvm-svn: 122090
2010-12-17 21:45:49 +00:00
15090e1eb0
take care of some todos, transforming [us]mul_lohi into
...
a wider mul if the wider mul is legal.
llvm-svn: 121848
2010-12-15 06:04:19 +00:00
b86dceea1b
when transforming a MULHS into a wider MUL, there is no need to SRA the
...
result, the top bits are truncated off anyway, just use SRL.
llvm-svn: 121846
2010-12-15 05:51:39 +00:00
10bd29f1d4
Add a couple dag combines to transform mulhi/mullo into a wider multiply
...
when the wider type is legal. This allows us to compile:
define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
%div = udiv i16 %x, 33
ret i16 %div
}
into:
test1: # @test1
movzwl 4(%esp), %eax
imull $63551, %eax, %eax # imm = 0xF83F
shrl $21, %eax
ret
instead of:
test1: # @test1
movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F
mulw 4(%esp)
andl $65504, %edx # imm = 0xFFE0
movl %edx, %eax
shrl $5, %eax
ret
Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320
We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.
llvm-svn: 121696
2010-12-13 08:39:01 +00:00
d9e8eac235
80-col fixups.
...
llvm-svn: 121356
2010-12-09 04:48:06 +00:00
583abbc4df
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
...
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
llvm-svn: 121120
2010-12-07 08:25:19 +00:00
f9b96c474f
Fix a comment typo.
...
llvm-svn: 120235
2010-11-28 06:51:19 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
...
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
c92331b984
Fix thinko: we must turn select(anyext, sext) into sext(select)
...
not anyext(select). Spotted by Frits van Bommel.
llvm-svn: 119739
2010-11-18 21:16:28 +00:00
12f3b3b44f
The DAGCombiner was threading select over pairs of extending loads even
...
if the extension types were not the same. The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext). Reported
and diagnosed by Sebastien Deldon.
llvm-svn: 119728
2010-11-18 20:05:18 +00:00
5db8921422
Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl
...
in order to fold it into a load.
llvm-svn: 118471
2010-11-09 01:54:35 +00:00
c6418b105a
Just return undef for invalid masks or elts, and since we're doing that,
...
just do it earlier too.
llvm-svn: 118195
2010-11-03 20:44:42 +00:00
fcc9e6848a
If we have an undef mask our Elt will be -1 for our access, handle
...
this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
2010-11-03 09:36:40 +00:00
68fb004616
Fix DAGCombiner to avoid going into an infinite loop when it
...
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
2010-11-03 01:47:46 +00:00
08882be86c
Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
...
llvm-svn: 117720
2010-10-29 22:03:02 +00:00
f63da12be9
Teach the DAG combiner to fold a splat of a splat. Radar 8597790.
...
Also do some minor refactoring to reduce indentation.
llvm-svn: 117558
2010-10-28 17:06:14 +00:00
a94cc6dfe8
Make CodeGen TBAA-aware.
...
llvm-svn: 116890
2010-10-20 00:31:05 +00:00
c8d6cfd730
This DAG combine BRCOND transformation can look pass truncate of the operand:
...
// %a = ...
// %b = and i32 %a, 2
// %c = srl i32 %b, 1
// brcond i32 %c ...
//
// into
//
// %a = ...
// %b = and i32 %a, 2
// %c = setcc eq %b, 0
// brcond %c ...
Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.
This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.
llvm-svn: 115571
2010-10-04 22:41:01 +00:00
a205055857
fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
...
llvm-svn: 115294
2010-10-01 05:36:09 +00:00
3231d13ddd
A select between a constant and zero, when fed by a bit test, can be efficiently
...
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.
llvm-svn: 114599
2010-09-22 22:58:22 +00:00
5e65dfbb97
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
...
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
llvm-svn: 114473
2010-09-21 20:42:50 +00:00
676c61db0e
update a bunch of code to use the MachinePointerInfo version of getStore.
...
llvm-svn: 114461
2010-09-21 18:41:36 +00:00
6963c1f789
eliminate an old SelectionDAG::getTruncStore method, propagating
...
MachinePointerInfo around more.
llvm-svn: 114452
2010-09-21 17:42:31 +00:00
3d178ed4d4
propagate MachinePointerInfo through various uses of the old
...
SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
2010-09-21 17:04:51 +00:00
f72c3c08a4
convert dagcombine off the old form of getLoad. This fixes several bugs
...
with SVOffset computation.
llvm-svn: 114442
2010-09-21 16:08:50 +00:00
e32675253f
simplify DAGCombiner::SimplifySelectOps step #2/2.
...
llvm-svn: 114437
2010-09-21 15:58:55 +00:00
254c445e63
substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.
...
no functionality change (step #1 )
llvm-svn: 114436
2010-09-21 15:46:59 +00:00
a35499e2af
a few more trivial updates. This fixes PerformInsertVectorEltInMemory to not
...
pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.
llvm-svn: 114411
2010-09-21 07:32:19 +00:00
272ff94916
When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
...
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.
This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.
llvm-svn: 114348
2010-09-20 20:39:59 +00:00
7b8d2ae912
Revert r114312 while I sort out some issues.
...
llvm-svn: 114313
2010-09-19 21:01:26 +00:00
ff82f8a35b
Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,
...
r114268 fixed the last of the blockers to enabling it. I will be monitoring
for failures.
llvm-svn: 114312
2010-09-19 19:51:55 +00:00
3c9b5f394b
Don't narrow the load and store in a load+twiddle+store sequence unless
...
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
2010-09-02 21:18:42 +00:00
317b969ac5
Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
...
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.
llvm-svn: 109519
2010-07-27 18:02:18 +00:00
9c271e2835
Remove r108639 now that it is handled by InstCombine instead.
...
llvm-svn: 108688
2010-07-19 08:10:24 +00:00
f7f9c8a2f7
Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions.
...
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.
This fixed <rdar://problem/8197504>.
llvm-svn: 108639
2010-07-18 08:47:54 +00:00
41b4a6b36a
Convert some tab stops into spaces.
...
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
Anton Korobeynikov