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17047 Commits

Author SHA1 Message Date
Rafael Espindola 4b7b7fba38 Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

llvm-svn: 124059
 2011-01-23 05:43:40 +00:00
Rafael Espindola 0e7e34e476 Remove more duplicated code. 
llvm-svn: 124056
 2011-01-23 04:43:11 +00:00
Rafael Espindola aea4958ea6 Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Venkatraman Govindaraju cc91b7a3f6 Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 
llvm-svn: 124030
 2011-01-22 13:05:16 +00:00
Venkatraman Govindaraju 7a0c350079 Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
llvm-svn: 124027
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju ef8cf45eb1 Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997
 2011-01-21 22:00:00 +00:00
Evan Cheng 2f2435d026 Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
 2011-01-21 18:55:51 +00:00
Bruno Cardoso Lopes 4bd612384a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Venkatraman Govindaraju 0594789f07 Implement support for byval arguments in Sparc backend. 
llvm-svn: 123974
 2011-01-21 14:00:01 +00:00
Andrew Trick 47ff14b091 Convert -enable-sched-cycles and -enable-sched-hazard to -disable 
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969
 2011-01-21 05:51:33 +00:00
Evan Cheng 028ccbfcbf Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative 
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.

llvm-svn: 123949
 2011-01-20 23:55:07 +00:00
Bruno Cardoso Lopes e965f06f7f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes ef8cab9079 Change instruction names for consistency 
llvm-svn: 123930
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes d8f9b37f31 Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes 33461ecc82 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes 4d4b490fb7 Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes cf99dc7eb9 Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Kalle Raiskila 6e5a54b36c Allow sign-extending of i8 and i16 to i128 on SPU. 
llvm-svn: 123912
 2011-01-20 15:49:06 +00:00
Bruno Cardoso Lopes 32f9b756a3 Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
llvm-svn: 123910
 2011-01-20 13:17:59 +00:00
Evan Cheng 7af85533f8 Correct itinerary entry for t2MOV_pic_ga_add_pc. 
llvm-svn: 123907
 2011-01-20 08:43:03 +00:00
Evan Cheng b8b0ad80a8 Sorry, several patches in one. 
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
 2011-01-20 08:34:58 +00:00
Venkatraman Govindaraju 058e12476c Sparc backend: Implements a delay slot filler that attempt to fill delay slots 
with useful instructions.

llvm-svn: 123884
 2011-01-20 05:08:26 +00:00
Bruno Cardoso Lopes d6335ce508 Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Daniel Dunbar e0cd9ac096 ARM/ISel: Factor out isScaledConstantInRange() helper. 
llvm-svn: 123823
 2011-01-19 15:12:16 +00:00
Andrew Trick 43f2563114 For ARM subtargets with useNEONForSinglePrecisionFP, double count uses 
of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.

llvm-svn: 123811
 2011-01-19 02:35:27 +00:00
Andrew Trick 5eb0a30216 whitespace 
llvm-svn: 123810
 2011-01-19 02:26:13 +00:00
Evan Cheng 68aec147b7 Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols. 
llvm-svn: 123809
 2011-01-19 02:16:49 +00:00
Bruno Cardoso Lopes 2082057b18 Create two new generic classes to represent the following VMRS/VMSR variations: 
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
 2011-01-18 21:58:20 +00:00
Bruno Cardoso Lopes cba727f291 Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes e86a7ad01a Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes e6290ccf9b Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes 7f639c11d7 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Jim Grosbach ec86bac8b3 Add a FIXME. 
llvm-svn: 123769
 2011-01-18 19:59:19 +00:00
Bruno Cardoso Lopes 95dbfac459 Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic 
llvm-svn: 123768
 2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes b02a9dfa55 Negative zero is not legal on mips. Patch by Sasa Stankovic 
llvm-svn: 123766
 2011-01-18 19:41:41 +00:00
Bruno Cardoso Lopes ac517fa9f7 Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic 
llvm-svn: 123763
 2011-01-18 19:38:25 +00:00
Bruno Cardoso Lopes 4dc73fa075 Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Chris Lattner a56c8279e8 add a note 
llvm-svn: 123752
 2011-01-18 07:47:48 +00:00
Venkatraman Govindaraju c386f8a1f6 SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments. 
llvm-svn: 123749
 2011-01-18 06:09:55 +00:00
Daniel Dunbar 62ea26fb6f McARM: Use accessors where appropriate. 
llvm-svn: 123746
 2011-01-18 05:55:27 +00:00
Daniel Dunbar bcd8eb0bac McARM: Fill in ASMOperand::dump() for memory operands. 
llvm-svn: 123745
 2011-01-18 05:55:21 +00:00
Daniel Dunbar 510740eea7 McARM: Make ARMOperand use a union where appropriate. 
llvm-svn: 123744
 2011-01-18 05:55:15 +00:00
Daniel Dunbar f5164f40c5 McARM: Unify ParseMemory() successfull return. 
llvm-svn: 123740
 2011-01-18 05:34:24 +00:00
Daniel Dunbar 1d5e954965 McARM: Early exit on failure (NEFC). 
llvm-svn: 123739
 2011-01-18 05:34:17 +00:00
Daniel Dunbar 7ed455990d McARM: Always keep an offset expression, if used (instead of assuming == 0 if used but not present), and simplify logic. 
Also, clean up various non-sensicalisms in isMemModeRegThumb() and isMemModeImmThumb().

llvm-svn: 123738
 2011-01-18 05:34:11 +00:00
Daniel Dunbar 5d99420e11 McARM: Add a variety of asserts on the sanity of memory operands. 
llvm-svn: 123737
 2011-01-18 05:34:05 +00:00
Daniel Dunbar d8da9e0fe6 McARM: Use a consistent marker for not-set OffsetRegNum. 
llvm-svn: 123736
 2011-01-18 05:33:57 +00:00
Daniel Dunbar 66e91d4a58 McARM: Start marking T2 address operands as such, for the benefit of the parser. 
llvm-svn: 123722
 2011-01-18 03:06:03 +00:00
Eric Christopher 542f8a5221 The stub routine that we're calling uses test and so clobbers 
the flags.

llvm-svn: 123712
 2011-01-18 01:37:20 +00:00
Chris Lattner ea4e983d70 minor change to rafael's recent patches: if something is 
constant but requires a unique address, we can still put it in a
readonly section, just not a mergable one.

llvm-svn: 123711
 2011-01-18 01:23:44 +00:00