ce02486d16
Support for microMIPS FPU instructions 1.
...
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
05bcde6d9a
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
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llvm-svn: 190780
2013-09-16 10:29:42 +00:00
6379121694
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
...
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
llvm-svn: 190235
2013-09-07 00:52:30 +00:00
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
9a1fb6b9fc
[mips] Add support for mfhc1 and mthc1.
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llvm-svn: 188848
2013-08-20 23:47:25 +00:00
8dd951bc9f
[mips] Remove predicates that were incorrectly or unnecessarily added.
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llvm-svn: 188845
2013-08-20 23:21:55 +00:00
14e31a2fe7
[mips] Define register class FGRH32 for the high half of the 64-bit floating
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point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
llvm-svn: 188842
2013-08-20 22:58:56 +00:00
6781fc1648
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
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load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
2013-08-20 21:08:22 +00:00
00fcf2e169
[mips] Rename accumulator register classes and FP register operands.
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llvm-svn: 188020
2013-08-08 21:54:26 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
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llvm-svn: 187832
2013-08-06 23:08:38 +00:00
643b398786
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
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llvm-svn: 187410
2013-07-30 10:12:14 +00:00
8bce21c154
[mips] Fix FP conditional move instructions to have explicit FP condition code
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register operands.
llvm-svn: 187242
2013-07-26 20:51:20 +00:00
1fb1b8b811
[mips] Fix FP branch instructions to have explicit FP condition code register
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operands.
llvm-svn: 187238
2013-07-26 20:13:47 +00:00
55f69b302c
[mips] Fix floating point branch, comparison, and conditional move instructions
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to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.
No intended functionality change.
llvm-svn: 187233
2013-07-26 19:01:56 +00:00
5bcb2407a5
[mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
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No functionality change.
llvm-svn: 186642
2013-07-19 01:19:52 +00:00
64828a1f73
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
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llvm-svn: 186397
2013-07-16 10:07:14 +00:00
b34ad7860f
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
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floating point loads and stores.
No changes in functionality.
llvm-svn: 185399
2013-07-02 00:00:02 +00:00
233dd51b13
This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
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llvm-svn: 184716
2013-06-24 10:05:34 +00:00
252f54f769
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
...
Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
llvm-svn: 182053
2013-05-16 21:17:15 +00:00
39d40f7baf
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
...
invalid instruction sequence.
Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.
mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.
llvm-svn: 182042
2013-05-16 19:48:37 +00:00
21bab5badc
[mips] Fix indentation.
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llvm-svn: 182036
2013-05-16 18:42:42 +00:00
9edae02db8
[mips] Add option -mno-ldc1-sdc1.
...
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
llvm-svn: 181718
2013-05-13 18:23:35 +00:00
b1457304cc
[mips] Define reg+imm load/store pattern templates.
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llvm-svn: 178407
2013-03-30 02:01:48 +00:00
69fb3d11ec
[mips] Split SelectAddr, which was used to match address patterns, into two
...
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
llvm-svn: 175300
2013-02-15 21:20:45 +00:00
28aed9ca85
[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
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llvm-svn: 173401
2013-01-25 00:20:39 +00:00
873c724b4a
This patch tackles the problem of parsing Mips
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register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
b1527b7505
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
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parameter.
llvm-svn: 170661
2012-12-20 04:20:09 +00:00
b2cc8a756f
[mips] Delete all floating point instruction classes that are no longer used.
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No functionality change.
llvm-svn: 170084
2012-12-13 02:05:02 +00:00
79e1cdb00b
[mips] Modify definitions of floating point comparison instructions.
...
No functionality change.
llvm-svn: 170077
2012-12-13 01:34:09 +00:00
fd9163b74c
[mips] Modify definitions of floating point branch instructions.
...
No functionality change.
llvm-svn: 170076
2012-12-13 01:32:36 +00:00
cd3dfd238e
[mips] Modify definitions of floating point indexed load and store instructions.
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No functionality change.
llvm-svn: 170075
2012-12-13 01:30:49 +00:00
b0d4acbc65
[mips] Modify definitions of floating point multiply-add/sub instructions.
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No functionality change.
llvm-svn: 170073
2012-12-13 01:27:48 +00:00
92994f4846
[mips] Modify definitions of floating point load and store instructions.
...
No functionality change.
llvm-svn: 170072
2012-12-13 01:24:00 +00:00
2b75dde5fa
[mips] Modify definitions of move from/to coprocessor instructions.
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No functionality change.
llvm-svn: 170071
2012-12-13 01:16:49 +00:00
dea8f61ae0
[mips] Modify definitions of two register operand floating point instructions.
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No functionality change.
llvm-svn: 170069
2012-12-13 01:14:07 +00:00
29b513871a
[mips] Modify definitions of three register operand floating point instructions
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and separate encoding information from the rest.
llvm-svn: 170066
2012-12-13 01:07:37 +00:00
84693d5606
[mips] Move classes that do not belong in MipsInstrFormats.td into
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MipsInstrFPU.td.
llvm-svn: 170061
2012-12-13 00:49:23 +00:00
db49b39200
[mips] Set isCommutable flag in a more explicit way.
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llvm-svn: 170060
2012-12-13 00:46:23 +00:00
193e1f738a
[mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.
...
llvm-svn: 170057
2012-12-13 00:38:59 +00:00
caaf4dd516
[mips] Remove single-precision floating point instruction from multiclass
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FFR2P_M.
llvm-svn: 170055
2012-12-13 00:35:54 +00:00
e986a59ad9
[mips] Remove single-precision floating point instructions from multiclasses
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FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
llvm-svn: 170053
2012-12-13 00:29:29 +00:00
97e179f9e4
[mips] Shorten predicate name.
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llvm-svn: 169579
2012-12-07 03:06:09 +00:00
3bc1beb696
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
...
support and use it in place of HasMips32r2Or64.
llvm-svn: 168089
2012-11-15 21:17:13 +00:00
da1980f697
[mips] Set flag neverHasSideEffects flag on floating point conversion
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instructions.
llvm-svn: 167348
2012-11-03 00:53:12 +00:00
3e7ba76157
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
...
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
llvm-svn: 163960
2012-09-15 01:52:08 +00:00
7605630c48
Add stub methods for mips assembly matcher.
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Patch by Vladimir Medic.
llvm-svn: 162124
2012-08-17 20:16:42 +00:00
a66d676b20
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
...
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
llvm-svn: 161071
2012-07-31 19:13:07 +00:00
4ce7c4060d
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
...
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
llvm-svn: 161063
2012-07-31 18:16:49 +00:00
d8ab16b86f
1. introduce MipsPat in place of Pat in order to exclude those from
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being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
llvm-svn: 158470
2012-06-14 21:03:23 +00:00
cdf4fd8267
This patch adds a predicate to existing mips32 and mips64 so that those
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instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
llvm-svn: 157234
2012-05-22 03:10:09 +00:00
71928e681b
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
47ad674f67
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
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otherwise expand FNEG during legalization.
llvm-svn: 154546
2012-04-11 22:59:08 +00:00
7f4c9d1429
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
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Invalid operation is signaled if the operand of these instructions is NaN.
llvm-svn: 154545
2012-04-11 22:49:04 +00:00
55059262aa
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
6bbe1f0d10
Fix bugs which were introduced when support for base+index floating point loads
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and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
f54f60f3ce
remove blanks, and some code format
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llvm-svn: 151625
2012-02-28 07:46:26 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
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load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
b260f206d2
Remove unnecessary template parameters.
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llvm-svn: 151540
2012-02-27 19:17:53 +00:00
3c5cab4730
Fix instruction predicates that were not set correctly.
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llvm-svn: 151538
2012-02-27 19:09:08 +00:00
60f7a8e710
Add definitions of floating point multiply add/sub and negative multiply
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add/sub instructions.
llvm-svn: 151415
2012-02-25 00:21:52 +00:00
4705b0cc1c
Remove trailing whitespace. Add newline.
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llvm-svn: 150706
2012-02-16 17:48:20 +00:00
77dbd786c8
Pattern for f32 to i64 conversion.
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llvm-svn: 148869
2012-01-24 22:05:25 +00:00
2216f73676
Various Mips64 floating point instruction patterns.
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llvm-svn: 144019
2011-11-07 21:38:58 +00:00
b2d37760a2
Add definition of the base class for floating point comparison instructions
...
and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
1537e297e1
Add definitions of 64-bit instructions which move data between integer and
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floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
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llvm-svn: 142220
2011-10-17 18:43:19 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
6be7d6c976
Simplify definition of FP move instructions.
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llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
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llvm-svn: 141474
2011-10-08 03:29:22 +00:00
13ae13bdc2
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
...
conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
...
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
dde4aac02b
Use tabs to separate opcode and operand strings.
...
llvm-svn: 132718
2011-06-07 18:16:51 +00:00
6af5bd2537
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
...
llvm-svn: 131927
2011-05-23 22:16:43 +00:00
e50a3d16e9
Fix setting of isCommutable flag.
...
llvm-svn: 131233
2011-05-12 17:42:08 +00:00
5dc19f916c
Fix td file comments for Mips.
...
Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
...
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
...
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
ed874eff93
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
...
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
72a364c107
fix emacs language spec's, patch by Edmund Grimley-Evans!
...
llvm-svn: 111241
2010-08-17 16:20:04 +00:00
e83591c616
the FPCmp node returns an i32.
...
llvm-svn: 99737
2010-03-28 05:12:57 +00:00
7ee71912ed
Fix mov.d out register by using the FFR register class directly
...
llvm-svn: 94914
2010-01-30 18:29:19 +00:00
5bf807688e
Disable ldc1/sdc1 instructions for mips1 targets.
...
llvm-svn: 88887
2009-11-16 04:35:29 +00:00
626d49f684
A real solution for the first part of PR5445
...
llvm-svn: 86895
2009-11-11 23:09:33 +00:00
05671ea10a
Fix PR5445
...
llvm-svn: 86651
2009-11-10 02:35:13 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Zoran Jovanovic