Craig Topper
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ed7aa46366
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Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
llvm-svn: 150873
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2012-02-18 08:19:49 +00:00 |
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Anton Korobeynikov
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c6b4017ce2
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Add support for implicit TLS model used with MS VC runtime.
Patch by Kai Nacke!
llvm-svn: 150307
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2012-02-11 17:26:53 +00:00 |
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Craig Topper
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4ed7278ff4
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Convert assert(0) to llvm_unreachable in X86 Target directory.
llvm-svn: 149809
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2012-02-05 05:38:58 +00:00 |
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Craig Topper
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cd93de93fa
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Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
llvm-svn: 147366
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2011-12-30 04:48:54 +00:00 |
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Jan Sjödin
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6dd2488383
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XOP encoding bits and logic.
llvm-svn: 146397
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2011-12-12 19:12:26 +00:00 |
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Bruno Cardoso Lopes
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0f9a1f5e6c
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This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
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2011-11-25 19:33:42 +00:00 |
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Craig Topper
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980d59832a
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Add X86 RORX instruction
llvm-svn: 142741
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2011-10-23 07:34:00 +00:00 |
|
Craig Topper
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96fa597828
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Add X86 PEXTR and PDEP instructions.
llvm-svn: 142141
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2011-10-16 16:50:08 +00:00 |
|
Craig Topper
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aea148c366
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Add X86 BZHI instruction as well as BMI2 feature detection.
llvm-svn: 142122
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2011-10-16 07:55:05 +00:00 |
|
Craig Topper
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25ea4e5ad3
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Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
llvm-svn: 142105
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2011-10-16 03:51:13 +00:00 |
|
Craig Topper
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27ad12539d
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Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
llvm-svn: 142082
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2011-10-15 20:46:47 +00:00 |
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Craig Topper
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f18c896337
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Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
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2011-10-04 06:30:42 +00:00 |
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Evan Cheng
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7e763d86ba
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Refactor X86 target to separate MC code from Target code.
llvm-svn: 135930
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2011-07-25 18:43:53 +00:00 |