Commit Graph

5 Commits

Author SHA1 Message Date
Matheus Almeida 784f797d4c [mips] SYNC $stype instruction was added in Mips32
but SYNC with an implied operand ($stype = 0) is valid since Mips2.

llvm-svn: 211185
2014-06-18 17:10:30 +00:00
Daniel Sanders 3d3ea53f32 [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

llvm-svn: 210787
2014-06-12 15:00:17 +00:00
Matheus Almeida 595fcab2d0 [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4019

llvm-svn: 210654
2014-06-11 15:05:56 +00:00
Matheus Almeida 39796a2ec5 [mips] Fix triple.
Mips2 is a 32-bit architecture.

llvm-svn: 210254
2014-06-05 12:07:14 +00:00
Daniel Sanders aadc357e5f [mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.

Depends on D3695

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3696

llvm-svn: 208549
2014-05-12 13:04:32 +00:00