00fcb0017e
Handling zero extension of 1 bit value.
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llvm-svn: 24722
2005-12-15 01:02:48 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
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base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
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first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
0d6cfee704
* Added X86 store patterns.
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* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
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false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
4b02426130
Proper support for shifts with register shift value.
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llvm-svn: 24559
2005-12-01 00:43:55 +00:00
af2e0373dd
SelectNodeTo now returns its result, we must pay attention to it.
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llvm-svn: 24550
2005-11-30 22:59:19 +00:00
4eb7af9bc9
Added support to STORE and shifts to DAG to DAG isel.
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llvm-svn: 24525
2005-11-30 02:51:20 +00:00
3f0f71b92b
Add load and other support to the dag-dag isel. Patch contributed by Evan
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Cheng!
llvm-svn: 24419
2005-11-19 02:11:08 +00:00
5930d3df3d
Add patterns for several simple instructions that take i32 immediates.
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Patch contributed by Evan Cheng!
llvm-svn: 24382
2005-11-16 22:59:19 +00:00
655e7dfd0d
initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
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by Evan Cheng!
llvm-svn: 24371
2005-11-16 01:54:32 +00:00
Evan Cheng