llvm-project

Commit Graph

Author	SHA1	Message	Date
Geoff Berry	43ec15e57e	[AArch64] Improved bitfield instruction selection. Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006	2015-09-18 17:11:53 +00:00
Arnaud A. de Grandmaison	f40f99e3a4	[AArch64] Select SBFIZ or UBFIZ instead of left + right shifts And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology. llvm-svn: 241803	2015-07-09 14:33:38 +00:00

Author

SHA1

Message

Date

Geoff Berry

43ec15e57e

[AArch64] Improved bitfield instruction selection.

Summary:
For bitfield insert OR matching, check both operands for larger pattern
first before checking for smaller pattern.

Add pattern for unsigned bitfield insert-in-zero done with SHL+AND.

Resolves PR21631.

Reviewers: jmolloy, t.p.northover

Subscribers: aemerson, rengolin, llvm-commits, mcrosier

Differential Revision: http://reviews.llvm.org/D12908

llvm-svn: 248006

2015-09-18 17:11:53 +00:00

Arnaud A. de Grandmaison

f40f99e3a4

[AArch64] Select SBFIZ or UBFIZ instead of left + right shifts

And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

llvm-svn: 241803

2015-07-09 14:33:38 +00:00

2 Commits