2 Commits

Author	SHA1	Message	Date
Hsiangkai Wang	8b33839f01	[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR. ... Differential Revision: https://reviews.llvm.org/D107139	2021-08-01 05:58:17 +08:00
Hsiangkai Wang	5821a58d8e	[RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'. ... Add asm constraint 'vr' for vector registers. Add asm constraint 'vm' for vector mask registers. Differential Revision: https://reviews.llvm.org/D98616	2021-03-30 09:47:27 +08:00