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Author SHA1 Message Date
Hsiangkai Wang b358a2be52 [RISCV] Remove riscv32 test cases for vector intrinsics. 2021-04-28 15:54:25 +08:00
Zakk Chen ca9e52f67c [RISCV][Clang] Drop the assembly tests for RVV intrinsics. 
We had verified the correctness of all intrinsics in downstream, so
dropping the assembly tests to decrease the check-clang time.
It would remove 1/3 of the RUN lines.

https://reviews.llvm.org/D99151#2654154 mentions why we need to have
the ASM tests before.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100617
 2021-04-16 09:30:12 -07:00
Zakk Chen fe252b509e [RISCV][Clang] Add more RVV Integer intrinsic functions. 
Support below instructions.
1. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2. Vector Integer Comparison Instructions
3. Vector Widening Integer Multiply-Add Instructions

Reviewed By: HsiangKai

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99528
 2021-04-06 03:11:28 -07:00