ab9521aaeb
[Hexagon] Use 'vnot' instead of 'not' in patterns with vectors
...
'not' expands to checking for an xor with a -1 constant. Since
this looks for a ConstantSDNode it will never match for a vector.
Co-authored-by: Craig Topper <craig.topper@sifive.com>
Differential Revision: https://reviews.llvm.org/D100687
2021-04-22 15:36:20 -05:00
849412270b
[Hexagon] Add more patterns for HVX loads and stores
...
In particular, add patterns for loads/stores to the stack
(with a frame index as address).
2021-03-17 21:01:52 -05:00
c4628460b7
[Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
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Followup to D92112 now that I've learnt about HVX type splitting.
This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.
Differential Revision: https://reviews.llvm.org/D92169
2020-11-27 15:46:11 +00:00
1b5baa42bc
[Hexagon] Handle selection between HVX vector predicates
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Make sure that (select i1 q0 q1) is handled properly.
2020-10-23 18:22:03 -05:00
97533b10b2
[Hexagon] Fix license headers in some .td files, NFC
2020-10-16 10:03:05 -05:00
670cd3c6e3
[Hexagon] Generate better splat code on v62+
2020-10-14 12:55:20 -05:00
9237e73ae8
[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
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This removes VSPLAT and VZERO. VZERO is now SPLAT_VECTOR of (i32 0).
Included is also a testcase for the previous (target-independent)
commit.
2020-10-10 19:49:47 -05:00
6fd994b4b7
[Hexagon] Remove ISD node VSPLATW, use VSPLAT instead
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This is a step towards improving HVX codegen for splat.
2020-10-09 15:38:02 -05:00
f528816d58
[Hexagon] Move selection of HVX multiply from lowering to patterns
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Also, change i32*i32 to V6_vmpyieoh + V6_vmpyiewuh_acc, which works
on V60 as well.
2020-10-02 16:04:34 -05:00
5f4abb7fab
[Hexagon] Replace incorrect pattern for vpackl HWI32 -> HVi8
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V6_vdealb4w is not correct for pairs, use V6_vpackeh/V6_vpackeb instead.
2020-09-15 20:34:50 -05:00
bb877d1af2
[Hexagon] Widen loads and handle any-/sign-/zero-extensions
2020-09-14 18:10:23 -05:00
0ee54cf883
[Hexagon] Account for truncating pairs to non-pairs when widening truncates
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Added missing selection patterns for vpackl.
2020-09-09 14:31:52 -05:00
c2b7b9b642
[Hexagon] Fix order of operands in V6_vdealb4w
2020-09-08 22:09:28 -05:00
1387f96ab3
[Hexagon] Handle widening of vector truncate
2020-09-05 15:07:38 -05:00
e15143d31b
[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX
2020-08-26 13:10:22 -05:00
f97fdf5792
[Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX
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llvm-svn: 372616
2019-09-23 14:33:27 +00:00
ac83aab035
[Hexagon] Generate min/max instructions for 64-bit vectors
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llvm-svn: 369124
2019-08-16 16:16:27 +00:00
8460301d58
[Hexagon] Generate vector min/max for HVX
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llvm-svn: 369014
2019-08-15 16:13:17 +00:00
d8b780dcd6
[Hexagon] Remove 'T' from HasVNN predicates, NFC
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Patch by Sumanth Gundapaneni.
llvm-svn: 335124
2018-06-20 13:56:09 +00:00
c1e712baa5
[Hexagon] Implement vector-pair zero as V6_vsubw_dv
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llvm-svn: 334123
2018-06-06 19:34:40 +00:00
aec2c0c9b6
[Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ
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llvm-svn: 333760
2018-06-01 14:52:58 +00:00
840b02bccf
[Hexagon] Add patterns for accumulating HVX compares
...
llvm-svn: 333009
2018-05-22 18:27:02 +00:00
f18009dbc6
[Hexagon] Fix the order of operands when selecting QCAT
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llvm-svn: 332526
2018-05-16 21:02:43 +00:00
e8a0ae7346
[Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns
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llvm-svn: 332525
2018-05-16 21:00:24 +00:00
cff73a2118
[Hexagon] Add patterns for vector shift-and-accumulate
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llvm-svn: 331918
2018-05-09 21:10:41 +00:00
41a24b7b13
[Hexagon] Improve HVX instruction selection (bitcast, vsplat)
...
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.
llvm-svn: 330471
2018-04-20 19:38:37 +00:00
d92c37e090
[Hexagon] Generate code for vector bswap intrinsics
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llvm-svn: 330333
2018-04-19 14:46:44 +00:00
2c3edf0567
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
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This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
llvm-svn: 326915
2018-03-07 17:27:18 +00:00
ad83ce4cb4
[Hexagon] Split HVX vector pair loads/stores, expand unaligned loads
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llvm-svn: 325169
2018-02-14 20:46:06 +00:00
9b48e8d233
[Hexagon] Add code to select QTRUE and QFALSE
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Fixes http://llvm.org/PR36320 .
llvm-svn: 324763
2018-02-09 19:10:46 +00:00
8abaf8954a
[Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC
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llvm-svn: 324392
2018-02-06 20:22:20 +00:00
Krzysztof Parzyszek